OpenASIP 2.2
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HWGen/HDLPort.hh
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1/*
2 Copyright (c) 2018 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file Port.hh
26 *
27 * Port classes for HDLGenerator
28 *
29 * @author Aleksi Tervo 2018 (aleksi.tervo-no.spam-tut.fi)
30 */
31
32#include "HWGenTools.hh"
33
34namespace HDLGenerator {
35 /**
36 * Entity/module port base class.
37 */
38 class Port {
39 public:
40 Port(std::string name, Direction dir, int width = 1,
43 Port(std::string name, Direction dir, std::string parametricWidth,
45 : name_(name), dir_(dir), parametricWidth_(parametricWidth),
47
48 virtual ~Port() = default;
49
50 void declare(std::ostream& stream, Language lang, int level = 0) {
51 stream << StringTools::indent(level);
52 if (lang == Language::VHDL) {
53 stream << name_;
54 if (dir_ == Direction::In) {
55 stream << " : in ";
56 } else {
57 stream << " : out ";
58 }
59 if (!parametricWidth_.empty()) {
60 stream << "std_logic_vector(" << parametricWidth_
61 << "-1 downto 0)";
62 } else if (wireType_ == WireType::Vector || width_ > 1) {
63 stream << "std_logic_vector("
64 << std::to_string(width_) << "-1 downto 0)";
65 } else {
66 stream << "std_logic";
67 }
68 } else if (lang == Language::Verilog) {
69 if (dir_ == Direction::In) {
70 stream << "input ";
71 } else {
72 stream << "output reg ";
73 }
74 if (!parametricWidth_.empty()) {
75 stream << "[" << parametricWidth_ << "-1:0] ";
76 } else if (wireType_ == WireType::Vector || width_ > 1) {
77 stream << "[" << std::to_string(width_ - 1) << ":0] ";
78 }
79 stream << name_;
80 } else {
81 throw std::runtime_error(__PRETTY_FUNCTION__);
82 }
83 };
84
85 std::string name() { return name_; }
86
88
89 WireType wireType() const { return wireType_; }
90
91 protected:
92 std::string name_;
94 std::string parametricWidth_;
95 int width_;
97 };
98
99 class OutPort : public Port {
100 public:
101 OutPort(std::string name, int width = 1,
104 OutPort(std::string name, std::string parametricWidth,
106 : Port(name, Direction::Out, parametricWidth, wireType) {}
107
108 };
109
110 class InPort : public Port {
111 public:
112 InPort(std::string name, int width = 1,
115 InPort(std::string name, std::string parametricWidth,
117 : Port(name, Direction::In, parametricWidth, wireType) {}
118 };
119}
InPort(std::string name, std::string parametricWidth, WireType wireType=WireType::Auto)
InPort(std::string name, int width=1, WireType wireType=WireType::Auto)
OutPort(std::string name, std::string parametricWidth, WireType wireType=WireType::Auto)
OutPort(std::string name, int width=1, WireType wireType=WireType::Auto)
Port(std::string name, Direction dir, int width=1, WireType wireType=WireType::Auto)
WireType wireType() const
Port(std::string name, Direction dir, std::string parametricWidth, WireType wireType=WireType::Auto)
std::string parametricWidth_
std::string name()
void declare(std::ostream &stream, Language lang, int level=0)
virtual ~Port()=default
static std::string indent(int level)