LLVMTCEIRBuilder.hh

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/*
    Copyright (c) 2002-2015 Tampere University.
 
    This file is part of TTA-Based Codesign Environment (TCE).
 
    Permission is hereby granted, free of charge, to any person obtaining a
    copy of this software and associated documentation files (the "Software"),
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    the rights to use, copy, modify, merge, publish, distribute, sublicense,
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    Software is furnished to do so, subject to the following conditions:
 
    The above copyright notice and this permission notice shall be included in
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    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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/**
 * @file LLVMTCEIRBuilder.hh
 *
 * This builder builds a CFG and DDG from the new LLVM TTA backend format.
 *
 * @author Heikki Kultala 2011
 * @author Pekka Jääskeläinen 2011,2015
 * @note reting: red
 */
 
#ifndef LLVM_TCE_IR_BUILDER_H
#define LLVM_TCE_IR_BUILDER_H
 
#include <llvm/CodeGen/MachineFunctionPass.h>
#include <llvm/Analysis/AliasAnalysis.h>
 
#include "LLVMTCEBuilder.hh"
#include "DataDependenceGraphBuilder.hh"
#include "CopyingDelaySlotFiller.hh"
 
class InterPassData;
class LLVMTCECmdLineOptions;
class BBSchedulerController;
class CopyingDelaySlotFiller;
class CycleLookBackSoftwareBypasser;
struct InnerLoopFinder;
 
namespace TTAMachine {
    class Machine;
}
 
namespace llvm {
 
    FunctionPass* createLLVMTCECFGBuilderPass(
        TCETargetMachine& tm, TTAMachine::Machine* mach, InterPassData& ipd);
 
    class LLVMTCEIRBuilder : public LLVMTCEBuilder {
    public:
        static char ID;
 
        LLVMTCEIRBuilder(
            const TargetMachine& tm, TTAMachine::Machine* mach, 
            InterPassData& ipd, AliasAnalysis* AA,
            bool functionAtATime=false, bool modifyMF=false);
 
        bool writeMachineFunction(MachineFunction& mf);
 
        virtual ~LLVMTCEIRBuilder();
 
        virtual bool doInitialization(Module& m );
        virtual bool doFinalization(Module& m );
 
        virtual void emitSPInitialization() {}
 
        void getAnalysisUsage(AnalysisUsage &AU) const;
 
        virtual StringRef getPassName() const {
            return "TCE: build TCE scheduler IR from MachineFunctions";
        }
 
        void setInnerLoopFinder(InnerLoopFinder* loopFinder) { 
            loopFinder_ = loopFinder; }
 
    protected:
 
        // TODO: copy-paste from LLVMPomBuilder.hh
        virtual unsigned spDRegNum() const { 
            return dynamic_cast<const TCETargetMachine&>(
                targetMachine()).spDRegNum(); 
        }
 
        // the return address register's llvm reg number
        virtual unsigned raPortDRegNum() const { 
            if (isTTATarget()) {
                return dynamic_cast<const TCETargetMachine&>(
                    targetMachine()).raPortDRegNum(); 
            } else {
                abortWithError("Unimplemented for non-TTA targets.");
            }
        }
 
        // the ADF register file name of the llvm reg number
        virtual TCEString registerFileName(unsigned llvmRegNum) const;
 
        // the ADF register index of the llvm reg number
        virtual int registerIndex(unsigned llvmRegNum) const;
 
        // operation name from a LLVM MachineInstr or OSAL Operation
        virtual TCEString operationName(const MachineInstr& mi) const; 
 
        virtual TTAProgram::Terminal* createFUTerminal(
            const MachineOperand&) const {
            // no FU terminals in the RISC-style backend, always through GPRs
            return NULL; 
        }
 
        virtual TTAProgram::Terminal* createMBBReference(
            const MachineOperand& mo);
 
        virtual TTAProgram::Terminal* createSymbolReference(
            const TCEString& symbolName);
            
        virtual void createMoveNode(
            ProgramOperationPtr& po,
            std::shared_ptr<TTAProgram::Move> m,
            bool isDestination) override;
 
    private:
 
        bool isHotFunction(llvm::MachineFunction& mf) const;
        bool isRealInstruction(const MachineInstr& instr) const;
        bool hasRealInstructions(
            MachineBasicBlock::const_iterator i, 
            const MachineBasicBlock& mbb);
 
        void convertProcedureToMachineFunction(
            const TTAProgram::Procedure& proc,
            llvm::MachineFunction& mf);
 
        void compileFast(ControlFlowGraph& cfg);
        void compileOptimized(
            ControlFlowGraph& cfg, 
            llvm::AliasAnalysis* llvmAA);
 
        bool isExplicitReturn(const llvm::MachineInstr& mi) const;
 
        CopyingDelaySlotFiller& delaySlotFiller();
        BBSchedulerController& scheduler();
 
        ControlFlowGraph* buildTCECFG(llvm::MachineFunction& mf);
        void markJumpTableDestinations(
            llvm::MachineFunction& mf, 
            ControlFlowGraph& cfg);
        void fixJumpTableDestinations(
            llvm::MachineFunction& mf, 
            ControlFlowGraph& cfg);
        
        InterPassData* ipData_;
        // TODO: how to get these?
        std::set<TCEString> allParamRegs_;
 
        // todo: information about sp and param regs, how to give?
        DataDependenceGraphBuilder ddgBuilder_;
 
        std::map<const MachineBasicBlock*,BasicBlockNode*> bbMapping_;
 
        std::vector<std::vector<BasicBlockNode*> > jumpTableRecord_;
 
        AliasAnalysis* AA_;
                
        // write back the scheduled instructions to the machine function?
        bool modifyMF_;
 
        std::map<const MachineBasicBlock*, BasicBlockNode*> skippedBBs_;
 
        bool delaySlotFilling_;
 
        BBSchedulerController* scheduler_;
        CopyingDelaySlotFiller* dsf_;
        CycleLookBackSoftwareBypasser* bypasser_;
 
        InnerLoopFinder* loopFinder_;
    };
}
 
#endif