OpenASIP 2.2
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NetlistFactories.cc
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1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * @file NetlistFactories.cc
26 *
27 * Implementation of NetlistFactories class.
28 *
29 * Created on: 25.5.2015
30 * @author Henry Linjamäki 2015 (henry.linjamaki-no.spam-tut.fi)
31 * @note rating: red
32 */
33
34#include "NetlistFactories.hh"
35
36#include "NetlistPort.hh"
37#include "NetlistPortGroup.hh"
38#include "ProGeTypes.hh"
39
40#include "AssocTools.hh"
41
42namespace ProGe {
43
44PortFactory* PortFactory::instance_ = NULL;
47
49// : machine_(NULL),
50// implementation_(NULL)
51{}
52
54 const TTAMachine::Machine& /*machine*/,
55 const IDF::MachineImplementation& /*impl*/)
56// : machine_(&machine),
57// implementation_(&impl)
58{}
59
61 PortPrototypeContainer::iterator port_it = portPrototypes_.begin();
62 while (port_it != portPrototypes_.end()) {
63 delete port_it->second;
64 port_it->second = NULL;
65 port_it++;
66 }
67 PortGroupPrototypeContainer::iterator portGroup_it =
69 while (portGroup_it != portGroupPrototypes_.end()) {
70 delete portGroup_it->second;
71 portGroup_it->second = NULL;
72 portGroup_it++;
73 }
74}
75
76void
79 portPrototypes_.insert(std::make_pair(type, port));
80}
81
82void
87
88void
94
95void
97 SignalGroupType type, const NetlistPortGroup* portGroup) {
99 portGroupPrototypes_.insert(std::make_pair(type, portGroup));
100}
101
102void
104 assert(
105 portGroup->assignedSignalGroup().type() !=
107
108 registerPortGroup(portGroup->assignedSignalGroup().type(), portGroup);
109}
110
111void
115 new OutBitPort(
117 new OutPort(
118 "imem_addr", "IMEMADDRWIDTH", BIT_VECTOR,
120 new InPort(
121 "imem_data", "IMEMWIDTHINMAUS*IMEMMAUWIDTH", BIT_VECTOR,
123 new InBitPort("busy", Signal(SignalType::STALL))));
124}
125
126/**
127 * Creates new NetlistPort for the given signal type.
128 *
129 * @param type The signal type.
130 * @return Pointer to newly created NetlistPort. Returns nullptr if there is
131 * no prototype for the given signal type.
132 */
135 if (portPrototypes_.count(type)) {
136 NetlistPort* found = portPrototypes_.find(type)->second->clone();
137 if (found->direction() != direction) {
138 return NetlistTools::mirror(found);
139 } else {
140 return found;
141 }
142 }
143 return NULL;
144}
145
148 return instance()->createPort(type, direction);
149}
150
153 if (portGroupPrototypes_.count(type)) {
154 return portGroupPrototypes_.find(type)->second->clone();
155 }
156 return NULL;
157}
158
163
164/**
165 * Initializes factory context for the singleton factory. This function may
166 * be called only once.
167 */
168void
171 const IDF::MachineImplementation& impl) {
172 assert(
173 staticMachine_ == NULL && staticImplementation_ == NULL &&
174 "Attempted to initialize twice.");
176 staticImplementation_ = &impl;
177}
178
179/**
180 * Global access to the factory as singleton. initializeContext() must be
181 * called once before this.
182 */
185 if (instance_) {
186 return instance_;
187 } else {
188 assert(staticMachine_ != NULL && staticImplementation_ != NULL);
189 return (
190 instance_ =
192 }
193}
194
195/**
196 * Creates default clock port.
197 *
198 */
201 static const InBitPort clkPortPrototype("clk", Signal(SignalType::CLOCK));
202 return clkPortPrototype.clone(direction != IN);
203}
204
205/**
206 * Creates default active-low reset port.
207 */
210 static const InBitPort rstxPortPrototype(
212 return rstxPortPrototype.clone(direction != IN);
213}
214
215} /* namespace ProGe */
#define assert(condition)
TTAMachine::Machine * machine
the architecture definition of the estimated processor
static bool containsKey(const ContainerType &aContainer, const KeyType &aKey)
Convenience class for input bit ports.
Convenience class for input ports.
SignalGroup assignedSignalGroup() const
virtual NetlistPortGroup * clone(bool asMirrored=false) const
virtual NetlistPort * clone(bool asMirrored=false) const
Signal assignedSignal() const
Direction direction() const
static Direction mirror(Direction direction)
Convenience class for output bit ports.
Convenience class for output ports.
static NetlistPort * resetPort(Direction direction=IN)
PortPrototypeContainer portPrototypes_
The creation context.
static const IDF::MachineImplementation * staticImplementation_
The creation context for singleton instance.
PortGroupPrototypeContainer portGroupPrototypes_
Registered NetlistPortGroup prototypes.
static NetlistPort * create(SignalType type, Direction direction=IN)
void registerPort(SignalType, const NetlistPort *port)
static PortFactory * instance_
Singleton instance of the factory.
static const TTAMachine::Machine * staticMachine_
The creation context for singleton instance.
NetlistPort * createPort(SignalType type, Direction direction=IN) const
NetlistPortGroup * createPortGroup(SignalGroupType type) const
static void initializeContext(const TTAMachine::Machine &machine, const IDF::MachineImplementation &impl)
static NetlistPort * clockPort(Direction direction=IN)
void registerPortGroup(SignalGroupType type, const NetlistPortGroup *portGroup)
static PortFactory * instance()
SignalGroupType type() const
SignalType type() const
Definition Signal.cc:55
Definition FUGen.hh:54
@ BIT_VECTOR
Several bits.
Definition ProGeTypes.hh:48
@ INSTRUCTION_LINE
Signal group type for serial TTA instruction bus.
Direction
Direction of the port.
Definition ProGeTypes.hh:52
@ IN
Input port.
Definition ProGeTypes.hh:53
@ UNDEFINED
Signal does not have specified usage.
@ READ_REQUEST
Signal to make read request.
@ ADDRESS
Signal holds address.
@ FETCHBLOCK
Signal is TTA instruction block block containing (compressed) instruction.
@ RESET
Reset signal.
@ STALL
Signal to stopping destination device.
@ CLOCK
Clock signal.