63 delete port_it->second;
64 port_it->second = NULL;
67 PortGroupPrototypeContainer::iterator portGroup_it =
70 delete portGroup_it->second;
71 portGroup_it->second = NULL;
121 "imem_data",
"IMEMWIDTHINMAUS*IMEMMAUWIDTH",
BIT_VECTOR,
174 "Attempted to initialize twice.");
202 return clkPortPrototype.
clone(direction !=
IN);
210 static const InBitPort rstxPortPrototype(
212 return rstxPortPrototype.
clone(direction !=
IN);
#define assert(condition)
TTAMachine::Machine * machine
the architecture definition of the estimated processor
Convenience class for input bit ports.
Convenience class for input ports.
SignalGroup assignedSignalGroup() const
virtual NetlistPortGroup * clone(bool asMirrored=false) const
virtual NetlistPort * clone(bool asMirrored=false) const
Signal assignedSignal() const
Direction direction() const
Convenience class for output bit ports.
Convenience class for output ports.
static NetlistPort * resetPort(Direction direction=IN)
void registerPortGroups()
PortPrototypeContainer portPrototypes_
The creation context.
static const IDF::MachineImplementation * staticImplementation_
The creation context for singleton instance.
PortGroupPrototypeContainer portGroupPrototypes_
Registered NetlistPortGroup prototypes.
static NetlistPort * create(SignalType type, Direction direction=IN)
void registerPort(SignalType, const NetlistPort *port)
static PortFactory * instance_
Singleton instance of the factory.
static const TTAMachine::Machine * staticMachine_
The creation context for singleton instance.
NetlistPort * createPort(SignalType type, Direction direction=IN) const
NetlistPortGroup * createPortGroup(SignalGroupType type) const
static void initializeContext(const TTAMachine::Machine &machine, const IDF::MachineImplementation &impl)
static NetlistPort * clockPort(Direction direction=IN)
void registerPortGroup(SignalGroupType type, const NetlistPortGroup *portGroup)
static PortFactory * instance()
SignalGroupType type() const
@ BIT_VECTOR
Several bits.
@ INSTRUCTION_LINE
Signal group type for serial TTA instruction bus.
Direction
Direction of the port.
@ UNDEFINED
Signal does not have specified usage.
@ READ_REQUEST
Signal to make read request.
@ ADDRESS
Signal holds address.
@ FETCHBLOCK
Signal is TTA instruction block block containing (compressed) instruction.
@ STALL
Signal to stopping destination device.