OpenASIP 2.2
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NetlistPort.hh
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1/*
2 Copyright (c) 2002-2009 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file NetlistPort.hh
26 *
27 * Declaration of NetlistPort class.
28 *
29 * @author Lasse Laasonen 2005 (lasse.laasonen-no.spam-tut.fi)
30 * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
31 * @author Henry Linjamäki 2015 (henry.linjamaki-no.spam-tut.fi)
32 * @note rating: red
33 */
34
35#ifndef TTA_NETLIST_PORT_HH
36#define TTA_NETLIST_PORT_HH
37
38#include <string>
39
40#include "ProGeTypes.hh"
41#include "Exception.hh"
42#include "Signal.hh"
43#include "NetlistTools.hh"
44
45namespace ProGe {
46
48public:
49 enum State {
50 GND, ///< All port signals set to low.
51 VCC, ///< All port signals set to high.
52 MIXED, ///< Port has signals both the low and high states.
53 OPEN ///< Port is left open/unused.
54 };
55
56 StaticSignal(State state) : state_(state) {}
57 bool is(State state) { return state_ == state; }
58private:
60};
61
62class NetlistBlock;
64
65/**
66 * Represents a port in the netlist. Ports are the vertices of the graph
67 * that represents the netlist. From the ports, it is possible to reach the
68 * parent netlist blocks.
69 */
71public:
72 friend class BaseNetlistBlock;
73
75 const std::string& name,
76 const std::string& widthFormula,
77 int realWidth,
80 BaseNetlistBlock& parent,
81 Signal signal = Signal());
83 const std::string& name,
84 int realWidth,
87 BaseNetlistBlock& parent,
88 Signal signal = Signal());
90 const std::string& name,
91 const std::string& widthFormula,
94 BaseNetlistBlock& parent,
95 Signal signal = Signal());
97 const std::string& name,
98 const std::string& widthFormula,
101 Signal signal = Signal());
102 virtual ~NetlistPort();
103
104 bool resolveRealWidth(int& width) const;
106 BaseNetlistBlock& newParent,
107 std::string newName="") const;
108 virtual NetlistPort* clone(bool asMirrored = false) const;
109
110 std::string name() const;
111 void rename(const std::string& newname);
112 std::string widthFormula() const;
113 void setWidthFormula(const std::string& newFormula);
114 bool realWidthAvailable() const;
115 int realWidth() const;
116 DataType dataType() const;
117 Direction direction() const;
119
120 bool hasParentBlock() const;
121 const BaseNetlistBlock& parentBlock() const;
123
124 void setToStatic(StaticSignal value) const;
125 void unsetStatic() const;
126 bool hasStaticValue() const;
128
129 void assignSignal(Signal signal);
130 Signal assignedSignal() const;
131
132private:
133
134 void setParent(BaseNetlistBlock* parent);
135 NetlistPort(const NetlistPort& other, bool asMirrored = false);
136
137 /// Name of the port.
138 std::string name_;
139 /// Formula for the width of the port.
140 std::string widthFormula_;
141 /// Real width of the port.
143 /// Data type of the port.
145 /// Direction of the port.
147 /// The parent netlist block.
149 /// Indicates if port is connected to vcc or gnd
150 mutable bool hasStaticValue_;
151 /// Static signal value
153 /// Assigned port usage.
155};
156
157/// Convenience class for output ports.
158class OutPort : public NetlistPort {
159public:
160 OutPort(
161 const std::string& name,
162 const std::string& widthFormula,
163 int realWidth,
165 BaseNetlistBlock& parent,
166 Signal signal = Signal());
167 OutPort(
168 const std::string& name,
169 const std::string& widthFormula,
171 BaseNetlistBlock& parent,
172 Signal signal = Signal());
173 OutPort(
174 const std::string& name,
175 const std::string& widthFormula,
177 Signal signal = Signal());
178};
179
180/// Convenience class for output bit ports.
181class OutBitPort : public NetlistPort {
182public:
184 const std::string& name,
185 BaseNetlistBlock& parent,
186 Signal signal = Signal());
188 const std::string& name,
189 Signal signal = Signal());
190};
191
192/// Convenience class for input ports.
193class InPort : public NetlistPort {
194public:
195 InPort(
196 const std::string& name,
197 const std::string& widthFormula,
198 int realWidth,
200 BaseNetlistBlock& parent,
201 Signal signal = Signal());
202 InPort(
203 const std::string& name,
204 const std::string& widthFormula,
206 BaseNetlistBlock& parent,
207 Signal signal = Signal());
208 InPort(
209 const std::string& name,
210 const std::string& widthFormula,
212 Signal signal = Signal());
213};
214
215/// Convenience class for input bit ports.
216class InBitPort : public NetlistPort {
217public:
218 InBitPort(
219 const std::string& name,
220 BaseNetlistBlock& parent,
221 Signal signal = Signal());
222 InBitPort(
223 const std::string& name,
224 Signal signal = Signal());
225};
226
227}
228
229#endif
Convenience class for input bit ports.
Convenience class for input ports.
virtual NetlistPort * clone(bool asMirrored=false) const
void setToStatic(StaticSignal value) const
NetlistPort * copyTo(BaseNetlistBlock &newParent, std::string newName="") const
void setParent(BaseNetlistBlock *parent)
DataType dataType_
Data type of the port.
bool resolveRealWidth(int &width) const
BaseNetlistBlock * parentBlock_
The parent netlist block.
void setWidthFormula(const std::string &newFormula)
bool hasStaticValue() const
bool realWidthAvailable() const
std::string widthFormula() const
Signal assignedSignal() const
bool hasParentBlock() const
DataType dataType() const
std::string widthFormula_
Formula for the width of the port.
void setDirection(Direction direction)
int realWidth_
Real width of the port.
bool hasStaticValue_
Indicates if port is connected to vcc or gnd.
StaticSignal staticValue_
Static signal value.
void unsetStatic() const
Direction direction_
Direction of the port.
const BaseNetlistBlock & parentBlock() const
Signal signal_
Assigned port usage.
Direction direction() const
std::string name_
Name of the port.
std::string name() const
StaticSignal staticValue() const
int realWidth() const
void rename(const std::string &newname)
void assignSignal(Signal signal)
Convenience class for output bit ports.
Convenience class for output ports.
StaticSignal(State state)
bool is(State state)
@ OPEN
Port is left open/unused.
@ GND
All port signals set to low.
@ VCC
All port signals set to high.
@ MIXED
Port has signals both the low and high states.
Definition FUGen.hh:54
DataType
Data types of hardware ports.
Definition ProGeTypes.hh:46
@ BIT_VECTOR
Several bits.
Definition ProGeTypes.hh:48
Direction
Direction of the port.
Definition ProGeTypes.hh:52