#include <InverterBlock.hh>

Inheritance diagram for ProGe::InverterBlock:

Collaboration diagram for ProGe::InverterBlock:

Public Member Functions
	InverterBlock (const NetlistPort &input, const NetlistPort &output)

virtual	~InverterBlock ()

const NetlistPort &	inputPort () const

const NetlistPort &	outputPort () const

Public Member Functions inherited from ProGe::BaseNetlistBlock
	BaseNetlistBlock ()

	BaseNetlistBlock (BaseNetlistBlock *parent)

	BaseNetlistBlock (const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=nullptr)

virtual	~BaseNetlistBlock ()

const std::string &	instanceName () const

void	setInstanceName (const std::string &name)

const std::string &	moduleName () const

const std::string	name () const

virtual size_t	subBlockCount () const

virtual const BaseNetlistBlock &	subBlock (size_t index) const

virtual bool	hasSubBlock (const std::string &instanceName) const

virtual bool	isSubBlock (const BaseNetlistBlock &block) const

virtual bool	hasParameter (const std::string &name) const

virtual const Parameter &	parameter (const std::string &name) const

virtual size_t	parameterCount () const

virtual const Parameter &	parameter (size_t index) const

virtual size_t	portCount () const

virtual const NetlistPort &	port (size_t index) const

virtual std::vector< const NetlistPort * >	portsBy (SignalType type) const

virtual const NetlistPort &	portBy (SignalType type, size_t index=0) const

virtual bool	hasPortsBy (SignalType type) const

virtual const NetlistPort *	port (const std::string &portName, bool partialMatch=true) const

virtual size_t	portGroupCount () const

virtual const NetlistPortGroup &	portGroup (size_t index) const

virtual std::vector< const NetlistPortGroup * >	portGroupsBy (SignalGroupType type) const

virtual const Netlist &	netlist () const

virtual bool	hasParentBlock () const

virtual const BaseNetlistBlock &	parentBlock () const

virtual bool	isVirtual () const

virtual void	build () override

virtual void	connect () override

virtual void	finalize () override

virtual void	write (const Path &targetBaseDir, HDL targetLang=VHDL) const override

virtual void	writeSelf (const Path &targetBaseDir, HDL targetLang=VHDL) const

virtual size_t	packageCount () const

virtual const std::string &	package (size_t idx) const

PortContainerType &	ports ()

virtual bool	isLeaf () const

BaseNetlistBlock *	shallowCopy (const std::string &instanceName="") const

Public Member Functions inherited from ProGe::IGenerationPhases
virtual	~IGenerationPhases ()

Private Member Functions
	InverterBlock ()

Private Attributes
const NetlistPort *	input_

const NetlistPort *	invertedOut_

Additional Inherited Members
Public Types inherited from ProGe::BaseNetlistBlock
typedef std::vector< BaseNetlistBlock * >	BlockContainerType

typedef std::vector< Parameter >	ParameterContainerType

typedef std::vector< NetlistPort * >	PortContainerType

typedef std::vector< NetlistPortGroup * >	PortGroupContainerType

Protected Member Functions inherited from ProGe::BaseNetlistBlock
Netlist &	netlist ()

virtual NetlistPort &	port (size_t index)

virtual BaseNetlistBlock &	subBlock (size_t index)

virtual BaseNetlistBlock &	parentBlock ()

void	setModuleName (const std::string &name)

void	addSubBlock (BaseNetlistBlock *subBlock, const std::string &instanceName="")

void	deleteSubBlock (BaseNetlistBlock *subBlock)

void	removeSubBlock (BaseNetlistBlock *subBlock)

NetlistPort *	addPort (NetlistPort *port)

void	removePort (NetlistPort *port)

void	addPortGroup (NetlistPortGroup *portGroup)

void	removePortGroup (NetlistPortGroup *portGroup)

void	setParameter (const Parameter &param)

void	addParameter (const Parameter &param)

Parameter &	parameter (const std::string &name)

NetlistPort *	findPort (const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const

void	addPackage (const std::string &packageName)

void	connectClocks ()

void	connectResets ()

Detailed Description

Definition at line 47 of file InverterBlock.hh.

Constructor & Destructor Documentation

◆ InverterBlock() [1/2]

ProGe::InverterBlock::InverterBlock	(	const NetlistPort &	input,
		const NetlistPort &	output
	)

Definition at line 47 of file InverterBlock.cc.

    : BaseNetlistBlock(
          "util_inverter", input.name() + "_" + "util_inverter") {
    input_ = new InBitPort("data_in", *this);
    invertedOut_ = new OutBitPort("data_out", *this);
}

References input_, and invertedOut_.

◆ ~InverterBlock()

ProGe::InverterBlock::~InverterBlock ( )

virtual

Definition at line 45 of file InverterBlock.cc.

45{}

◆ InverterBlock() [2/2]

ProGe::InverterBlock::InverterBlock ( )

private

Definition at line 43 of file InverterBlock.cc.

43: input_(NULL), invertedOut_(NULL) {}

Member Function Documentation

◆ inputPort()

const NetlistPort & ProGe::InverterBlock::inputPort ( ) const

Definition at line 56 of file InverterBlock.cc.

                               {
    return *input_;
}

References input_.

Referenced by MemoryGenerator::connectPorts().

◆ outputPort()

const NetlistPort & ProGe::InverterBlock::outputPort ( ) const

Definition at line 61 of file InverterBlock.cc.

                                {
    return *invertedOut_;
}

References invertedOut_.

Referenced by MemoryGenerator::connectPorts().

Member Data Documentation

◆ input_

const NetlistPort* ProGe::InverterBlock::input_

private

Definition at line 60 of file InverterBlock.hh.

Referenced by inputPort(), and InverterBlock().

◆ invertedOut_

const NetlistPort* ProGe::InverterBlock::invertedOut_

private

Definition at line 61 of file InverterBlock.hh.

Referenced by InverterBlock(), and outputPort().

The documentation for this class was generated from the following files:

Public Member Functions

Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ InverterBlock() [1/2]

◆ ~InverterBlock()

◆ InverterBlock() [2/2]

Member Function Documentation

◆ inputPort()

◆ outputPort()

Member Data Documentation

◆ input_

◆ invertedOut_