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Public Types | Public Member Functions | Protected Member Functions | Private Member Functions | Private Attributes | Friends | List of all members
ProGe::BaseNetlistBlock Class Reference

#include <BaseNetlistBlock.hh>

Inheritance diagram for ProGe::BaseNetlistBlock:
Inheritance graph
Collaboration diagram for ProGe::BaseNetlistBlock:
Collaboration graph

Public Types

typedef std::vector< BaseNetlistBlock * > BlockContainerType
 
typedef std::vector< ParameterParameterContainerType
 
typedef std::vector< NetlistPort * > PortContainerType
 
typedef std::vector< NetlistPortGroup * > PortGroupContainerType
 

Public Member Functions

 BaseNetlistBlock ()
 
 BaseNetlistBlock (BaseNetlistBlock *parent)
 
 BaseNetlistBlock (const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=nullptr)
 
virtual ~BaseNetlistBlock ()
 
const std::string & instanceName () const
 
void setInstanceName (const std::string &name)
 
const std::string & moduleName () const
 
const std::string name () const
 
virtual size_t subBlockCount () const
 
virtual const BaseNetlistBlocksubBlock (size_t index) const
 
virtual bool hasSubBlock (const std::string &instanceName) const
 
virtual bool isSubBlock (const BaseNetlistBlock &block) const
 
virtual bool hasParameter (const std::string &name) const
 
virtual const Parameterparameter (const std::string &name) const
 
virtual size_t parameterCount () const
 
virtual const Parameterparameter (size_t index) const
 
virtual size_t portCount () const
 
virtual const NetlistPortport (size_t index) const
 
virtual std::vector< const NetlistPort * > portsBy (SignalType type) const
 
virtual const NetlistPortportBy (SignalType type, size_t index=0) const
 
virtual bool hasPortsBy (SignalType type) const
 
virtual const NetlistPortport (const std::string &portName, bool partialMatch=true) const
 
virtual size_t portGroupCount () const
 
virtual const NetlistPortGroupportGroup (size_t index) const
 
virtual std::vector< const NetlistPortGroup * > portGroupsBy (SignalGroupType type) const
 
virtual const Netlistnetlist () const
 
virtual bool hasParentBlock () const
 
virtual const BaseNetlistBlockparentBlock () const
 
virtual bool isVirtual () const
 
virtual void build () override
 
virtual void connect () override
 
virtual void finalize () override
 
virtual void write (const Path &targetBaseDir, HDL targetLang=VHDL) const override
 
virtual void writeSelf (const Path &targetBaseDir, HDL targetLang=VHDL) const
 
virtual size_t packageCount () const
 
virtual const std::string & package (size_t idx) const
 
PortContainerTypeports ()
 
virtual bool isLeaf () const
 
BaseNetlistBlockshallowCopy (const std::string &instanceName="") const
 
- Public Member Functions inherited from ProGe::IGenerationPhases
virtual ~IGenerationPhases ()
 

Protected Member Functions

Netlistnetlist ()
 
virtual NetlistPortport (size_t index)
 
virtual BaseNetlistBlocksubBlock (size_t index)
 
virtual BaseNetlistBlockparentBlock ()
 
void setModuleName (const std::string &name)
 
void addSubBlock (BaseNetlistBlock *subBlock, const std::string &instanceName="")
 
void deleteSubBlock (BaseNetlistBlock *subBlock)
 
void removeSubBlock (BaseNetlistBlock *subBlock)
 
NetlistPortaddPort (NetlistPort *port)
 
void removePort (NetlistPort *port)
 
void addPortGroup (NetlistPortGroup *portGroup)
 
void removePortGroup (NetlistPortGroup *portGroup)
 
void setParameter (const Parameter &param)
 
void addParameter (const Parameter &param)
 
Parameterparameter (const std::string &name)
 
NetlistPortfindPort (const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const
 
void addPackage (const std::string &packageName)
 
void connectClocks ()
 
void connectResets ()
 

Private Member Functions

 BaseNetlistBlock (const BaseNetlistBlock &)
 
BaseNetlistBlockoperator= (const BaseNetlistBlock &)
 
virtual void setParent (BaseNetlistBlock *parent)
 

Private Attributes

BaseNetlistBlockparent_
 The reference to parent block of this block.
 
BlockContainerType subBlocks_
 The sub blocks of this netlist block.
 
ParameterContainerType parameters_
 The parameters of the block.
 
PortContainerType ports_
 The ports of the block.
 
PortGroupContainerType portGroups_
 The ports of the block.
 
Netlistnetlist_
 The netlist of the block.
 
std::string instanceName_
 The instance name of the block.
 
std::string moduleName_
 The module name of the block.
 
std::vector< std::string > packages_
 The referenced packages by the module.
 

Friends

class NetlistPort
 
class NetlistPortGroup
 
class Parameter
 

Detailed Description

Definition at line 59 of file BaseNetlistBlock.hh.

Member Typedef Documentation

◆ BlockContainerType

Definition at line 65 of file BaseNetlistBlock.hh.

◆ ParameterContainerType

Definition at line 66 of file BaseNetlistBlock.hh.

◆ PortContainerType

Definition at line 67 of file BaseNetlistBlock.hh.

◆ PortGroupContainerType

Definition at line 68 of file BaseNetlistBlock.hh.

Constructor & Destructor Documentation

◆ BaseNetlistBlock() [1/4]

ProGe::BaseNetlistBlock::BaseNetlistBlock ( )

Definition at line 53 of file BaseNetlistBlock.cc.

54 : parent_(nullptr),
55 subBlocks_(),
57 ports_(),
59 netlist_(new Netlist()),
60 instanceName_("defaultInstanceName_inst0"),
61 moduleName_("defaultModuleName"),
62 packages_() {}
PortContainerType ports_
The ports of the block.
std::string moduleName_
The module name of the block.
BlockContainerType subBlocks_
The sub blocks of this netlist block.
PortGroupContainerType portGroups_
The ports of the block.
std::string instanceName_
The instance name of the block.
BaseNetlistBlock * parent_
The reference to parent block of this block.
Netlist * netlist_
The netlist of the block.
ParameterContainerType parameters_
The parameters of the block.
std::vector< std::string > packages_
The referenced packages by the module.

Referenced by shallowCopy().

◆ BaseNetlistBlock() [2/4]

ProGe::BaseNetlistBlock::BaseNetlistBlock ( BaseNetlistBlock parent)
explicit

Definition at line 64 of file BaseNetlistBlock.cc.

65 : parent_(parent),
66 subBlocks_(),
68 ports_(),
70 netlist_(new Netlist()),
71 instanceName_("defaultInstanceName_inst0"),
72 moduleName_("defaultModuleName"),
73 packages_() {
74 if (parent_ != nullptr) {
75 parent_->addSubBlock(this);
76 }
77}
void addSubBlock(BaseNetlistBlock *subBlock, const std::string &instanceName="")

References addSubBlock(), and parent_.

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◆ BaseNetlistBlock() [3/4]

ProGe::BaseNetlistBlock::BaseNetlistBlock ( const std::string &  moduleName,
const std::string &  instanceName,
BaseNetlistBlock parent = nullptr 
)

Definition at line 79 of file BaseNetlistBlock.cc.

82 : parent_(parent),
83 subBlocks_(),
85 ports_(),
87 netlist_(new Netlist()),
90 packages_() {
91 if (instanceName.empty()) {
92 setInstanceName(moduleName + "_inst0");
93 }
94
95 if (parent_ != nullptr) {
96 parent_->addSubBlock(this);
97 }
98}
void setInstanceName(const std::string &name)
const std::string & instanceName() const
const std::string & moduleName() const

◆ ~BaseNetlistBlock()

ProGe::BaseNetlistBlock::~BaseNetlistBlock ( )
virtual

Definition at line 100 of file BaseNetlistBlock.cc.

100 {
101 if (parent_ != nullptr) {
102 parent_->removeSubBlock(this);
103 parent_ = nullptr;
104 }
105
106 for (PortGroupContainerType::reverse_iterator it = portGroups_.rbegin();
107 it != portGroups_.rend();) {
108 NetlistPortGroup* toDeleted = *it;
109 it++;
110 portGroups_.pop_back();
111 delete toDeleted;
112 }
113
114 for (PortContainerType::reverse_iterator it = ports_.rbegin();
115 it != ports_.rend();) {
116 NetlistPort* toDeleted = *it;
117 it++;
118 ports_.pop_back();
119 delete toDeleted;
120 }
121
122 for (BlockContainerType::reverse_iterator it = subBlocks_.rbegin();
123 it != subBlocks_.rend();) {
124 BaseNetlistBlock* toDeleted = *it;
125 it++;
126 subBlocks_.pop_back();
127 delete toDeleted;
128 }
129
130 delete netlist_;
131 netlist_ = nullptr;
132}
void removeSubBlock(BaseNetlistBlock *subBlock)

References parent_, portGroups_, and removeSubBlock().

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◆ BaseNetlistBlock() [4/4]

ProGe::BaseNetlistBlock::BaseNetlistBlock ( const BaseNetlistBlock )
private

Member Function Documentation

◆ addPackage()

void ProGe::BaseNetlistBlock::addPackage ( const std::string &  packageName)
protected

Definition at line 687 of file BaseNetlistBlock.cc.

687 {
688 if (!ContainerTools::containsValue(packages_, packageName)) {
689 packages_.push_back(packageName);
690 }
691}
static bool containsValue(const ContainerType &aContainer, const ElementType &aKey)

References ContainerTools::containsValue(), and packages_.

Referenced by addParameter(), ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock(), and shallowCopy().

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◆ addParameter()

void ProGe::BaseNetlistBlock::addParameter ( const Parameter param)
protected

Adds new parameter to the block. Throws exception if the block has the parameter by the name already.

Definition at line 547 of file BaseNetlistBlock.cc.

547 {
548 // Check for uniqueness //
549 for (Parameter& p : parameters_) {
550 if (p.name() == param.name()) {
552 __FILE__, __LINE__,
553 "The block \"" + name() + "\" already has parameter\"" +
554 param.name() + "\"");
555 }
556 }
557
558 // Check if parameter's value refers to a constant //
559 if (param.valueIsConstant()) {
560 std::string packageName = param.packageNameOfConstant();
561 assert(!packageName.empty());
562 addPackage(packageName);
563 }
564
565 parameters_.push_back(param);
566}
#define assert(condition)
void addPackage(const std::string &packageName)
const std::string name() const

References addPackage(), assert, name(), ProGe::Parameter::name(), ProGe::Parameter::packageNameOfConstant(), parameters_, and ProGe::Parameter::valueIsConstant().

Referenced by ProGe::LoopBufferBlock::LoopBufferBlock(), ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock(), and ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock().

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◆ addPort()

NetlistPort * ProGe::BaseNetlistBlock::addPort ( NetlistPort port)
protected

Adds port to this block and acquires ownership of it.

Added port will point to this block after the call.

Exceptions
ObjectAlreadyExistsThrown if the netlist block already has a port by same name.

Definition at line 467 of file BaseNetlistBlock.cc.

467 {
468 assert(port != nullptr && "Attempted to add null port.");
469 if (findPort(port->name(), false, false)) {
472 "Given port by name (" + port->name() +
473 ") already exists in the netlist block (" +
474 this->instanceName() + " : " + this->moduleName() + ").");
475 }
476
477 if (!port->hasParentBlock() || &port->parentBlock() != this) {
478 port->setParent(this);
479 }
480 ports_.push_back(port);
482 if (parent_ != nullptr) {
484 }
485 return port;
486}
#define THROW_EXCEPTION(exceptionType, message)
Exception wrapper macro that automatically includes file name, line number and function name where th...
Definition Exception.hh:39
virtual const NetlistPort & port(size_t index) const
NetlistPort * findPort(const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const
void setParent(BaseNetlistBlock *parent)
bool hasParentBlock() const
const BaseNetlistBlock & parentBlock() const
std::string name() const
size_t registerPort(NetlistPort &port)
Definition Netlist.cc:309

References assert, findPort(), ProGe::NetlistPort::hasParentBlock(), ProGe::NetlistPort::name(), netlist_, parent_, ProGe::NetlistPort::parentBlock(), port(), ports_, ProGe::Netlist::registerPort(), ProGe::NetlistPort::setParent(), and THROW_EXCEPTION.

Referenced by addPortGroup(), ProGe::LoopBufferBlock::LoopBufferBlock(), ProGe::NetlistPort::NetlistPort(), ProGe::NetlistPort::NetlistPort(), ProGe::NetlistPort::NetlistPort(), ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock(), ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock(), and ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock().

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◆ addPortGroup()

void ProGe::BaseNetlistBlock::addPortGroup ( NetlistPortGroup portGroup)
protected

Definition at line 508 of file BaseNetlistBlock.cc.

508 {
509 portGroups_.push_back(portGroup);
510 portGroup->setParent(this);
511 for (size_t i = 0; i < portGroup->portCount(); i++) {
512 if (!netlist().isRegistered(portGroup->portAt(i))) {
514 }
515 }
516}
NetlistPort * addPort(NetlistPort *port)
virtual const NetlistPortGroup & portGroup(size_t index) const
virtual const Netlist & netlist() const
const NetlistPort & portAt(size_t index) const
void setParent(BaseNetlistBlock *newParent)

References addPort(), netlist(), ProGe::NetlistPortGroup::portAt(), ProGe::NetlistPortGroup::portCount(), portGroup(), portGroups_, and ProGe::NetlistPortGroup::setParent().

Referenced by shallowCopy(), ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock(), and ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock().

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◆ addSubBlock()

void ProGe::BaseNetlistBlock::addSubBlock ( BaseNetlistBlock subBlock,
const std::string &  instanceName = "" 
)
protected

Adds sub block to this block and acquires ownership of it.

Parameters
subBlockThe block to be added.
instanceNameThe instance base name to be given for sub block. If the given or sub block's instance name is not unique within the block The name will be prefixed with a running number.

Definition at line 405 of file BaseNetlistBlock.cc.

406 {
407 if (!instanceName.empty()) {
410 } else {
411 if (subBlock->instanceName().empty()) {
413 *this, subBlock->moduleName() + "_inst0"));
414 } else {
416 *this, subBlock->instanceName()));
417 }
418 }
419
421 subBlock->setParent(this);
422 subBlocks_.push_back(subBlock);
423
424 // Register ports of the subblock so connections can be made.
425 for (size_t i = 0; i < subBlock->portCount(); i++) {
427 }
428}
virtual const BaseNetlistBlock & subBlock(size_t index) const
virtual bool hasParentBlock() const
virtual size_t portCount() const
virtual const BaseNetlistBlock & parentBlock() const
virtual void setParent(BaseNetlistBlock *parent)
static std::string getUniqueInstanceName(const BaseNetlistBlock &within, const std::string &basename)

References assert, ProGe::NetlistTools::getUniqueInstanceName(), hasParentBlock(), instanceName(), instanceName_, moduleName(), netlist_, parentBlock(), port(), portCount(), ProGe::Netlist::registerPort(), setInstanceName(), setParent(), subBlock(), and subBlocks_.

Referenced by ProGe::ProcessorWrapperBlock::addInstructionMemory(), BaseNetlistBlock(), and ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock().

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◆ build()

void ProGe::BaseNetlistBlock::build ( )
overridevirtual

Implements ProGe::IGenerationPhases.

Definition at line 602 of file BaseNetlistBlock.cc.

602{}

◆ connect()

void ProGe::BaseNetlistBlock::connect ( )
overridevirtual

Implements ProGe::IGenerationPhases.

Definition at line 605 of file BaseNetlistBlock.cc.

605{}

◆ connectClocks()

void ProGe::BaseNetlistBlock::connectClocks ( )
protected

Connects all unconnected clock ports of sub block to this block's clock port if there is one.

Definition at line 722 of file BaseNetlistBlock.cc.

722 {
723 auto clkPorts = this->portsBy(SignalType::CLOCK);
724 assert(clkPorts.size() == 1);
725 const NetlistPort& thisClk = *clkPorts.at(0);
726
727 for (size_t i = 0; i < subBlockCount(); i++) {
728 const BaseNetlistBlock& block = subBlock(i);
729 for (auto port : block.portsBy(SignalType::CLOCK)) {
730 if (!netlist().isPortConnected(*port) &&
731 thisClk.direction() == port->direction()) {
732 netlist().connect(thisClk, *port);
733 }
734 }
735 }
736}
virtual size_t subBlockCount() const
virtual std::vector< const NetlistPort * > portsBy(SignalType type) const
Direction direction() const
bool connect(const NetlistPort &port1, const NetlistPort &port2, int port1FirstBit, int port2FirstBit, int width=1)
Definition Netlist.cc:83
@ CLOCK
Clock signal.

References assert, ProGe::CLOCK, ProGe::Netlist::connect(), ProGe::NetlistPort::direction(), ProGe::Netlist::isPortConnected(), netlist(), port(), portsBy(), subBlock(), and subBlockCount().

Referenced by ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock().

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◆ connectResets()

void ProGe::BaseNetlistBlock::connectResets ( )
protected

Connects all unconnected reset ports of sub block to this block's reset port if there is one.

Definition at line 743 of file BaseNetlistBlock.cc.

743 {
744 auto resetPorts = this->portsBy(SignalType::RESET);
745 assert(resetPorts.size() == 1);
746 const NetlistPort& thisReset = *resetPorts.at(0);
747
748 for (size_t i = 0; i < subBlockCount(); i++) {
749 const BaseNetlistBlock& block = subBlock(i);
750 for (auto port : block.portsBy(SignalType::RESET)) {
751 if (!netlist().isPortConnected(*port) &&
752 thisReset.direction() == port->direction()) {
753 netlist().connect(thisReset, *port);
754 }
755 }
756 }
757}
@ RESET
Reset signal.

References assert, ProGe::Netlist::connect(), ProGe::NetlistPort::direction(), ProGe::Netlist::isPortConnected(), netlist(), port(), portsBy(), ProGe::RESET, subBlock(), and subBlockCount().

Referenced by ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock().

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◆ deleteSubBlock()

void ProGe::BaseNetlistBlock::deleteSubBlock ( BaseNetlistBlock subBlock)
protected

Deletes given sub block and its all sub blocks.

Definition at line 434 of file BaseNetlistBlock.cc.

434 {
435 // todo remove port descriptions of deleted block in the netlist.
436 for (size_t i = 0; i < subBlocks_.size(); i++) {
437 if (subBlocks_.at(i) == subBlock) {
438 BaseNetlistBlock* toDeleted = subBlocks_.at(i);
440 delete toDeleted;
441 }
442 }
443}
static void swapRemoveValue(std::vector< E > &aContainer, I index)

References subBlock(), subBlocks_, and ContainerTools::swapRemoveValue().

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◆ finalize()

void ProGe::BaseNetlistBlock::finalize ( )
overridevirtual

Implements ProGe::IGenerationPhases.

Definition at line 608 of file BaseNetlistBlock.cc.

608{}

◆ findPort()

NetlistPort * ProGe::BaseNetlistBlock::findPort ( const std::string &  portName,
bool  recursiveSearch = false,
bool  partialMatch = true 
) const
protected

Returns a port that matches (partially) the given name.

If not found, returns nullptr

Definition at line 574 of file BaseNetlistBlock.cc.

576 {
577 if (recursiveSearch) {
578 assert(
579 false &&
580 "BaseNetlistBlock::findPort(): "
581 "recursive search not implemented.");
582 }
583
584 NetlistPort* portPtr = nullptr;
585 for (size_t i = 0; i < portCount(); i++) {
586 if (ports_.at(i)->name() == portName) {
587 return ports_.at(i);
588 }
589 }
590 if (partialMatch) {
591 for (size_t i = 0; i < portCount(); i++) {
592 if (ports_.at(i)->name().find(portName) != std::string::npos) {
593 return ports_.at(i);
594 }
595 }
596 }
597
598 return portPtr;
599}

References assert, portCount(), and ports_.

Referenced by addPort(), ProGe::NetlistBlock::port(), and port().

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◆ hasParameter()

bool ProGe::BaseNetlistBlock::hasParameter ( const std::string &  name) const
virtual

Definition at line 183 of file BaseNetlistBlock.cc.

183 {
184 for (size_t i = 0; i < parameterCount(); i++) {
185 if (parameter(i).name() == name) {
186 return true;
187 }
188 }
189 return false;
190}
virtual size_t parameterCount() const
virtual const Parameter & parameter(const std::string &name) const
const TCEString & name() const
Definition Parameter.cc:133

References name(), ProGe::Parameter::name(), parameter(), and parameterCount().

Referenced by AlteraMemGenerator::addGenerics(), ProGe::LoopBufferBlock::setIterationPortWidthParameter(), and ProGe::VHDLNetlistWriter::usesParameterWidth().

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◆ hasParentBlock()

bool ProGe::BaseNetlistBlock::hasParentBlock ( ) const
virtual

◆ hasPortsBy()

bool ProGe::BaseNetlistBlock::hasPortsBy ( SignalType  type) const
virtual

Return true if the netlist block has at least one port by given Signal Type.

Definition at line 300 of file BaseNetlistBlock.cc.

300 {
301 std::vector<const NetlistPort*> result;
302 for (size_t i = 0; i < portCount(); i++) {
303 const NetlistPort& port = this->port(i);
304 if (port.assignedSignal().type() == type) {
305 return true;
306 }
307 }
308 return false;
309}
Signal assignedSignal() const
SignalType type() const
Definition Signal.cc:55

References ProGe::NetlistPort::assignedSignal(), port(), portCount(), and ProGe::Signal::type().

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◆ hasSubBlock()

bool ProGe::BaseNetlistBlock::hasSubBlock ( const std::string &  instanceName) const
virtual

Definition at line 160 of file BaseNetlistBlock.cc.

160 {
161 for (size_t i = 0; i < subBlockCount(); i++) {
162 if (subBlock(i).instanceName() == instanceName) {
163 return true;
164 }
165 }
166 return false;
167}

References subBlockCount().

Referenced by ProGe::NetlistTools::getUniqueInstanceName(), and setInstanceName().

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◆ instanceName()

const std::string & ProGe::BaseNetlistBlock::instanceName ( ) const

◆ isLeaf()

virtual bool ProGe::BaseNetlistBlock::isLeaf ( ) const
inlinevirtual

Returns true if the netlist block in the block hierarchy is a leaf block.

Leaf block are not modifiable: No ports, sub blocks or ports may be added or removed.

Definition at line 134 of file BaseNetlistBlock.hh.

134{ return true; }

◆ isSubBlock()

bool ProGe::BaseNetlistBlock::isSubBlock ( const BaseNetlistBlock block) const
virtual

Returns true if the given netlist block is sub block of this block.

Definition at line 173 of file BaseNetlistBlock.cc.

173 {
175}

References ContainerTools::containsValue(), and subBlocks_.

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◆ isVirtual()

virtual bool ProGe::BaseNetlistBlock::isVirtual ( ) const
inlinevirtual

◆ moduleName()

const std::string & ProGe::BaseNetlistBlock::moduleName ( ) const

◆ name()

const std::string ProGe::BaseNetlistBlock::name ( ) const

◆ netlist() [1/2]

Netlist & ProGe::BaseNetlistBlock::netlist ( )
protected

Definition at line 681 of file BaseNetlistBlock.cc.

681 {
682 assert(netlist_ != nullptr);
683 return *netlist_;
684}

References assert, and netlist_.

◆ netlist() [2/2]

const Netlist & ProGe::BaseNetlistBlock::netlist ( ) const
virtual

◆ operator=()

BaseNetlistBlock & ProGe::BaseNetlistBlock::operator= ( const BaseNetlistBlock )
private

◆ package()

const std::string & ProGe::BaseNetlistBlock::package ( size_t  idx) const
virtual

◆ packageCount()

size_t ProGe::BaseNetlistBlock::packageCount ( ) const
virtual

◆ parameter() [1/3]

Parameter & ProGe::BaseNetlistBlock::parameter ( const std::string &  name)
protected

Returns a Parameter object by name.

Exceptions
NotAvailableThrown if the block does not have such Parameter.

Definition at line 217 of file BaseNetlistBlock.cc.

217 {
218 for (size_t i = 0; i < parameterCount(); i++) {
219 if (parameters_.at(i).name() == name) {
220 return parameters_.at(i);
221 }
222 }
223
224 throw NotAvailable(
225 __FILE__, __LINE__, __func__,
226 std::string("The block (") + instanceName() + ":" + moduleName() +
227 ") does not have parameter \"" + name + "\"");
228}
#define __func__

References __func__, instanceName(), moduleName(), name(), parameterCount(), and parameters_.

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◆ parameter() [2/3]

const Parameter & ProGe::BaseNetlistBlock::parameter ( const std::string &  name) const
virtual

Returns a Parameter object by name.

Exceptions
NotAvailableThrown if the block does not have such Parameter.

Reimplemented in ProGe::NetlistBlock.

Definition at line 198 of file BaseNetlistBlock.cc.

198 {
199 for (size_t i = 0; i < parameterCount(); i++) {
200 if (parameter(i).name() == name) {
201 return parameter(i);
202 }
203 }
204
205 throw NotAvailable(
206 __FILE__, __LINE__, __func__,
207 std::string("The block (") + instanceName() + ":" + moduleName() +
208 ") does not have parameter \"" + name + "\"");
209}

References __func__, instanceName(), moduleName(), name(), ProGe::Parameter::name(), parameter(), and parameterCount().

Referenced by hasParameter(), parameter(), ProGe::VHDLNetlistWriter::parameterWidthValue(), ProGe::NetlistVisualization::printBlockTree(), shallowCopy(), ProGe::VHDLNetlistWriter::writeComponentDeclarations(), ProGe::VerilogNetlistWriter::writeGenericDeclaration(), ProGe::VHDLNetlistWriter::writeGenericDeclaration(), ProGe::VerilogNetlistWriter::writePortMappings(), and ProGe::VHDLNetlistWriter::writePortMappings().

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◆ parameter() [3/3]

const Parameter & ProGe::BaseNetlistBlock::parameter ( size_t  index) const
virtual

Reimplemented in ProGe::NetlistBlock.

Definition at line 236 of file BaseNetlistBlock.cc.

236 {
237 if (index >= parameterCount()) {
238 throw OutOfRange(__FILE__, __LINE__, __func__);
239 }
240
241 return parameters_.at(index);
242}

References __func__, parameterCount(), and parameters_.

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◆ parameterCount()

size_t ProGe::BaseNetlistBlock::parameterCount ( ) const
virtual

◆ parentBlock() [1/2]

BaseNetlistBlock & ProGe::BaseNetlistBlock::parentBlock ( )
protectedvirtual

Reimplemented in ProGe::NetlistBlock.

Definition at line 364 of file BaseNetlistBlock.cc.

364 {
366 return *parent_;
367}

References assert, hasParentBlock(), and parent_.

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◆ parentBlock() [2/2]

const BaseNetlistBlock & ProGe::BaseNetlistBlock::parentBlock ( ) const
virtual

Reimplemented in ProGe::NetlistBlock.

Definition at line 358 of file BaseNetlistBlock.cc.

358 {
360 return *parent_;
361}

References assert, hasParentBlock(), and parent_.

Referenced by addSubBlock(), ProGe::NetlistTools::parent(), ProGe::NetlistBlock::parentBlock(), ProGe::NetlistBlock::parentBlock(), removePort(), and setInstanceName().

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◆ port() [1/3]

const NetlistPort * ProGe::BaseNetlistBlock::port ( const std::string &  portName,
bool  partialMatch = true 
) const
virtual

Returns a port that matches (partially) the given name.

Returns
The matching port. If not found, returns nullptr.

Reimplemented in ProGe::NetlistBlock.

Definition at line 317 of file BaseNetlistBlock.cc.

317 {
318 return findPort(portName, false, partialMatch);
319}

References findPort().

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◆ port() [2/3]

NetlistPort & ProGe::BaseNetlistBlock::port ( size_t  index)
protectedvirtual

Reimplemented in ProGe::NetlistBlock.

Definition at line 322 of file BaseNetlistBlock.cc.

322 {
323 return *ports_.at(index);
324}

References ports_.

◆ port() [3/3]

const NetlistPort & ProGe::BaseNetlistBlock::port ( size_t  index) const
virtual

◆ portBy()

const NetlistPort & ProGe::BaseNetlistBlock::portBy ( SignalType  type,
size_t  index = 0 
) const
virtual

Returns a port by Signal Type at given index.

Parameters
Thelist of ports by matching signal type at the index.
Exceptions
OutOfRangeIf the index is the number of found matches or larger.

Definition at line 284 of file BaseNetlistBlock.cc.

284 {
285 std::vector<const NetlistPort*> matches = portsBy(type);
286 if (index < matches.size()) {
287 return *matches.at(index);
288 } else {
291 "No port by signal at index " + Conversion::toString(index));
292 }
293}
static std::string toString(const T &source)

References portsBy(), THROW_EXCEPTION, and Conversion::toString().

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◆ portCount()

size_t ProGe::BaseNetlistBlock::portCount ( ) const
virtual

◆ portGroup()

const NetlistPortGroup & ProGe::BaseNetlistBlock::portGroup ( size_t  index) const
virtual

◆ portGroupCount()

size_t ProGe::BaseNetlistBlock::portGroupCount ( ) const
virtual

◆ portGroupsBy()

std::vector< const NetlistPortGroup * > ProGe::BaseNetlistBlock::portGroupsBy ( SignalGroupType  type) const
virtual

Definition at line 337 of file BaseNetlistBlock.cc.

337 {
338 std::vector<const NetlistPortGroup*> found;
339 for (size_t i = 0; i < portGroupCount(); i++) {
340 if (portGroup(i).assignedSignalGroup() == type) {
341 found.push_back(&portGroup(i));
342 }
343 }
344 return found;
345}
virtual size_t portGroupCount() const
SignalGroup assignedSignalGroup() const

References ProGe::NetlistPortGroup::assignedSignalGroup(), portGroup(), and portGroupCount().

Referenced by ProGe::ProcessorGenerator::instructionBus().

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◆ ports()

PortContainerType & ProGe::BaseNetlistBlock::ports ( )
inline

Definition at line 125 of file BaseNetlistBlock.hh.

125{return ports_;}

References ports_.

◆ portsBy()

std::vector< const NetlistPort * > ProGe::BaseNetlistBlock::portsBy ( SignalType  type) const
virtual

Returns list of ports by Signal Type.

Parameters
Thelist of ports by matching signal type in insertion order.

Definition at line 264 of file BaseNetlistBlock.cc.

264 {
265 std::vector<const NetlistPort*> result;
266 for (size_t i = 0; i < portCount(); i++) {
267 const NetlistPort& port = this->port(i);
268 if (port.assignedSignal().type() == type) {
269 result.push_back(&port);
270 }
271 }
272 return result;
273}

References ProGe::NetlistPort::assignedSignal(), port(), portCount(), and ProGe::Signal::type().

Referenced by connectClocks(), ProGe::Netlist::connectClocks(), connectResets(), ProGe::Netlist::connectResets(), and portBy().

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◆ removePort()

void ProGe::BaseNetlistBlock::removePort ( NetlistPort port)
protected

Removes the given port from the block.

After call the port is parent block reference is set to nullptr.

Definition at line 494 of file BaseNetlistBlock.cc.

494 {
495 assert(
496 &port->parentBlock() == this &&
497 "Attempted to remove a port the block does not have.");
498
500 if (this->hasParentBlock()) {
502 }
504 port->setParent(nullptr);
505}
static bool removeValueIfExists(ContainerType &aContainer, const ElementType &aKey)
void unregisterPort(NetlistPort &port)
Definition Netlist.cc:342

References assert, hasParentBlock(), netlist(), parentBlock(), ProGe::NetlistPort::parentBlock(), port(), ports_, ContainerTools::removeValueIfExists(), ProGe::NetlistPort::setParent(), and ProGe::Netlist::unregisterPort().

Referenced by ProGe::NetlistPort::~NetlistPort().

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◆ removePortGroup()

void ProGe::BaseNetlistBlock::removePortGroup ( NetlistPortGroup portGroup)
protected

Definition at line 519 of file BaseNetlistBlock.cc.

519 {
520 for (size_t i = 0; i < portGroups_.size(); i++) {
521 if (portGroups_.at(i) == port) {
523 break;
524 }
525 }
526}

References port(), portGroups_, and ContainerTools::swapRemoveValue().

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◆ removeSubBlock()

void ProGe::BaseNetlistBlock::removeSubBlock ( BaseNetlistBlock subBlock)
protected

Removes sub block from this block and does not delete it.

Definition at line 449 of file BaseNetlistBlock.cc.

449 {
450 // todo remove port descriptions of removed block in the netlist.
451 for (size_t i = 0; i < subBlocks_.size(); i++) {
452 if (subBlocks_.at(i) == subBlock) {
454 }
455 }
456}

References subBlock(), subBlocks_, and ContainerTools::swapRemoveValue().

Referenced by setParent(), and ~BaseNetlistBlock().

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◆ setInstanceName()

void ProGe::BaseNetlistBlock::setInstanceName ( const std::string &  name)

Replaces the instance name of the block.

The new name must be unique within sub blocks of parent block it is attached to.

Exceptions
ObjectAlreadyExistsThrown if the name is not unique.

Definition at line 379 of file BaseNetlistBlock.cc.

379 {
382 ObjectAlreadyExists, "New instance name of " + name +
383 " is not unique within parent "
384 "block of " +
385 parentBlock().instanceName() + " : " +
387 }
389}
virtual bool hasSubBlock(const std::string &instanceName) const

References hasParentBlock(), hasSubBlock(), instanceName(), instanceName_, moduleName(), name(), parentBlock(), and THROW_EXCEPTION.

Referenced by addSubBlock().

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◆ setModuleName()

void ProGe::BaseNetlistBlock::setModuleName ( const std::string &  name)
protected

Definition at line 392 of file BaseNetlistBlock.cc.

392 {
394}

References moduleName_, and name().

Referenced by ProGe::LoopBufferBlock::LoopBufferBlock().

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◆ setParameter()

void ProGe::BaseNetlistBlock::setParameter ( const Parameter param)
protected

◆ setParent()

void ProGe::BaseNetlistBlock::setParent ( BaseNetlistBlock newparent)
privatevirtual

Changes parent block to given one.

Definition at line 707 of file BaseNetlistBlock.cc.

707 {
708 if (parent_ != nullptr && parent_ != newparent) {
709 BaseNetlistBlock* oldParent = parent_;
710 parent_ = nullptr; // Prevent parent block causing recursive call of
711 // setParent() when calling detachSubBlock().
712 oldParent->removeSubBlock(this);
713 }
714 parent_ = newparent;
715}

References parent_, and removeSubBlock().

Referenced by addSubBlock().

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◆ shallowCopy()

BaseNetlistBlock * ProGe::BaseNetlistBlock::shallowCopy ( const std::string &  instanceName = "") const

Creates new netlist block that only includes without of its subblocks or interconnections.

Definition at line 640 of file BaseNetlistBlock.cc.

640 {
642 this->moduleName(),
643 (!instanceName.empty()) ? instanceName : this->instanceName(),
644 nullptr);
645
646 for (size_t i = 0; i < this->parameterCount(); i++) {
647 block->setParameter(this->parameter(i));
648 }
649 for (size_t i = 0; i < netlist().parameterCount(); i++) {
650 block->netlist().setParameter(this->netlist().parameter(i));
651 }
652 std::map<std::string, NetlistPort*> copiedPorts;
653 // Copy ports while preserving their insertion order.
654 for (size_t i = 0; i < portCount(); i++) {
655 NetlistPort* copiedPort = nullptr;
656 copiedPort = BaseNetlistBlock::port(i).copyTo(*block);
657 copiedPorts.insert({{copiedPort->name(), copiedPort}});
658 }
659 for (size_t i = 0; i < portGroupCount(); i++) {
660 const NetlistPortGroup* portGrp = &portGroup(i);
661 // Cloning to copy original class type, but clear ports as they are
662 // already created and added to the new block.
663 NetlistPortGroup* newGroup = portGrp->clone();
664 newGroup->clear();
665 for (auto port : *portGrp) {
666 newGroup->addPort(*copiedPorts.at(port->name()));
667 }
668 block->addPortGroup(newGroup);
669 }
670 for (size_t i = 0; i < packageCount(); i++) {
671 block->addPackage(this->package(i));
672 }
673
674 assert(
675 block->portCount() == this->portCount() &&
676 "Port count mismatch in shallow copy.");
677 return block;
678}
virtual size_t packageCount() const
virtual const std::string & package(size_t idx) const
NetlistPort * copyTo(BaseNetlistBlock &newParent, std::string newName="") const
size_t parameterCount() const
Definition Netlist.cc:422
Parameter parameter(size_t index) const
Definition Netlist.cc:434

References addPackage(), ProGe::NetlistPortGroup::addPort(), addPortGroup(), assert, BaseNetlistBlock(), ProGe::NetlistPortGroup::clear(), ProGe::NetlistPortGroup::clone(), ProGe::NetlistPort::copyTo(), instanceName(), moduleName(), ProGe::NetlistPort::name(), netlist(), package(), packageCount(), parameter(), ProGe::Netlist::parameter(), parameterCount(), ProGe::Netlist::parameterCount(), port(), portCount(), portGroup(), portGroupCount(), setParameter(), and ProGe::Netlist::setParameter().

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◆ subBlock() [1/2]

BaseNetlistBlock & ProGe::BaseNetlistBlock::subBlock ( size_t  index)
protectedvirtual

Reimplemented in ProGe::NetlistBlock.

Definition at line 178 of file BaseNetlistBlock.cc.

178 {
179 return *subBlocks_.at(index);
180}

References subBlocks_.

◆ subBlock() [2/2]

const BaseNetlistBlock & ProGe::BaseNetlistBlock::subBlock ( size_t  index) const
virtual

◆ subBlockCount()

size_t ProGe::BaseNetlistBlock::subBlockCount ( ) const
virtual

◆ write()

void ProGe::BaseNetlistBlock::write ( const Path targetBaseDir,
HDL  targetLang = VHDL 
) const
overridevirtual

Does nothing on self but calls write function on each sub block.

Implements ProGe::IGenerationPhases.

Reimplemented in ProGe::LoopBufferBlock, ProGe::NetlistBlock, ProGe::ProcessorWrapperBlock, ProGe::SinglePortByteMaskSSRAMBlock, ProGe::SinglePortSSRAMBlock, and ProGe::TestBenchBlock.

Definition at line 614 of file BaseNetlistBlock.cc.

614 {
615 // Call write of each sub block //
616 for (BaseNetlistBlock* subblock : subBlocks_) {
617 subblock->write(targetBaseDir, targetLang);
618 }
619}

References subBlocks_.

Referenced by ProGe::NetlistBlock::write(), and ProGe::ProcessorWrapperBlock::write().

◆ writeSelf()

void ProGe::BaseNetlistBlock::writeSelf ( const Path targetBaseDir,
HDL  targetLang = VHDL 
) const
virtual

Writes HDL source of itself only using default netlist writer.

Definition at line 625 of file BaseNetlistBlock.cc.

625 {
626 if (targetLang == HDL::VHDL) {
627 VHDLNetlistWriter(*this).write(targetBaseDir.string());
628 } else if (targetLang == HDL::Verilog) {
629 VerilogNetlistWriter(*this).write(targetBaseDir.string());
630 } else {
631 THROW_EXCEPTION(NotAvailable, "Given HDL language is not supported.");
632 }
633}
@ Verilog
Verilog.
Definition ProGeTypes.hh:42
@ VHDL
VHDL.
Definition ProGeTypes.hh:41

References THROW_EXCEPTION, ProGe::Verilog, ProGe::VHDL, ProGe::VerilogNetlistWriter::write(), and ProGe::VHDLNetlistWriter::write().

Referenced by ProGe::ProcessorWrapperBlock::write().

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Friends And Related Symbol Documentation

◆ NetlistPort

friend class NetlistPort
friend

Definition at line 61 of file BaseNetlistBlock.hh.

◆ NetlistPortGroup

friend class NetlistPortGroup
friend

◆ Parameter

friend class Parameter
friend

Member Data Documentation

◆ instanceName_

std::string ProGe::BaseNetlistBlock::instanceName_
private

The instance name of the block.

Definition at line 186 of file BaseNetlistBlock.hh.

Referenced by addSubBlock(), instanceName(), and setInstanceName().

◆ moduleName_

std::string ProGe::BaseNetlistBlock::moduleName_
private

The module name of the block.

Definition at line 188 of file BaseNetlistBlock.hh.

Referenced by setModuleName().

◆ netlist_

Netlist* ProGe::BaseNetlistBlock::netlist_
private

The netlist of the block.

Definition at line 184 of file BaseNetlistBlock.hh.

Referenced by addPort(), addSubBlock(), netlist(), and netlist().

◆ packages_

std::vector<std::string> ProGe::BaseNetlistBlock::packages_
private

The referenced packages by the module.

Definition at line 190 of file BaseNetlistBlock.hh.

Referenced by addPackage(), package(), and packageCount().

◆ parameters_

ParameterContainerType ProGe::BaseNetlistBlock::parameters_
private

The parameters of the block.

Definition at line 178 of file BaseNetlistBlock.hh.

Referenced by addParameter(), parameter(), parameter(), parameterCount(), and setParameter().

◆ parent_

BaseNetlistBlock* ProGe::BaseNetlistBlock::parent_
private

The reference to parent block of this block.

Definition at line 174 of file BaseNetlistBlock.hh.

Referenced by addPort(), BaseNetlistBlock(), hasParentBlock(), parentBlock(), parentBlock(), setParent(), and ~BaseNetlistBlock().

◆ portGroups_

PortGroupContainerType ProGe::BaseNetlistBlock::portGroups_
private

◆ ports_

PortContainerType ProGe::BaseNetlistBlock::ports_
private

The ports of the block.

Definition at line 180 of file BaseNetlistBlock.hh.

Referenced by addPort(), findPort(), port(), port(), portCount(), ports(), and removePort().

◆ subBlocks_

BlockContainerType ProGe::BaseNetlistBlock::subBlocks_
private

The sub blocks of this netlist block.

Definition at line 176 of file BaseNetlistBlock.hh.

Referenced by addSubBlock(), deleteSubBlock(), isSubBlock(), ProGe::NetlistBlock::package(), removeSubBlock(), subBlock(), and write().


The documentation for this class was generated from the following files: