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33 #ifndef TTA_ALTERA_HIBI_DP_RAM_GENERATOR_HH
34 #define TTA_ALTERA_HIBI_DP_RAM_GENERATOR_HH
59 virtual std::vector<TCEString>
65 const std::string fuPort,
66 std::vector<TCEString>& reasons)
const;
virtual std::vector< TCEString > generateComponentFile(TCEString outputPath)
virtual ~AlteraHibiDpRamGenerator()
virtual bool generatesComponentHdlFile() const
virtual TCEString instanceName(int coreId, int memIndex) const
static const TCEString COMPONENT_FILE
std::ostream & warningStream()
AlteraHibiDpRamGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
virtual bool checkFuPort(const std::string fuPort, std::vector< TCEString > &reasons) const
virtual void connectPorts(ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)
virtual TCEString moduleName() const
std::ostream & errorStream()