#include <NetlistBlock.hh>

Inheritance diagram for ProGe::NetlistBlock:

Collaboration diagram for ProGe::NetlistBlock:

Public Member Functions
	NetlistBlock (const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=NULL)

virtual	~NetlistBlock ()

void	setParameter (const std::string &name, const std::string &type, const std::string &value)

void	removePort (NetlistPort &port)

virtual NetlistPort *	port (const std::string &portName, bool partialMatch=true)

NetlistBlock &	subBlock (size_t index) override

virtual const NetlistBlock &	parentBlock () const override

virtual NetlistBlock &	parentBlock () override

NetlistBlock *	shallowCopy (const std::string &instanceName) const

virtual void	write (const Path &targetBaseDir, HDL targetLang=VHDL) const override

void	addParameter (const Parameter &param)

void	setParameter (const Parameter &param)

virtual const Parameter &	parameter (const std::string &name) const

virtual const Parameter &	parameter (size_t index) const

Parameter &	parameter (const std::string &name)

NetlistPort *	addPort (NetlistPort *port)

void	removePort (NetlistPort *port)

virtual size_t	portCount () const

virtual const NetlistPort &	port (size_t index) const

virtual const NetlistPort *	port (const std::string &portName, bool partialMatch=true) const

virtual NetlistPort &	port (size_t index)

void	addPortGroup (NetlistPortGroup *portGroup)

void	addSubBlock (BaseNetlistBlock *subBlock, const std::string &instanceName="")

virtual size_t	subBlockCount () const

virtual const Netlist &	netlist () const

Netlist &	netlist ()

void	addPackage (const std::string &packageName)

virtual size_t	packageCount () const

virtual const std::string &	package (size_t idx) const

Public Member Functions inherited from ProGe::BaseNetlistBlock
	BaseNetlistBlock ()

	BaseNetlistBlock (BaseNetlistBlock *parent)

	BaseNetlistBlock (const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=nullptr)

virtual	~BaseNetlistBlock ()

const std::string &	instanceName () const

void	setInstanceName (const std::string &name)

const std::string &	moduleName () const

const std::string	name () const

virtual size_t	subBlockCount () const

virtual const BaseNetlistBlock &	subBlock (size_t index) const

virtual bool	hasSubBlock (const std::string &instanceName) const

virtual bool	isSubBlock (const BaseNetlistBlock &block) const

virtual bool	hasParameter (const std::string &name) const

virtual const Parameter &	parameter (const std::string &name) const

virtual size_t	parameterCount () const

virtual const Parameter &	parameter (size_t index) const

virtual size_t	portCount () const

virtual const NetlistPort &	port (size_t index) const

virtual std::vector< const NetlistPort * >	portsBy (SignalType type) const

virtual const NetlistPort &	portBy (SignalType type, size_t index=0) const

virtual bool	hasPortsBy (SignalType type) const

virtual const NetlistPort *	port (const std::string &portName, bool partialMatch=true) const

virtual size_t	portGroupCount () const

virtual const NetlistPortGroup &	portGroup (size_t index) const

virtual std::vector< const NetlistPortGroup * >	portGroupsBy (SignalGroupType type) const

virtual const Netlist &	netlist () const

virtual bool	hasParentBlock () const

virtual bool	isVirtual () const

virtual void	build () override

virtual void	connect () override

virtual void	finalize () override

virtual void	writeSelf (const Path &targetBaseDir, HDL targetLang=VHDL) const

virtual size_t	packageCount () const

virtual const std::string &	package (size_t idx) const

PortContainerType &	ports ()

virtual bool	isLeaf () const

BaseNetlistBlock *	shallowCopy (const std::string &instanceName="") const

Public Member Functions inherited from ProGe::IGenerationPhases
virtual	~IGenerationPhases ()

Additional Inherited Members
Public Types inherited from ProGe::BaseNetlistBlock
typedef std::vector< BaseNetlistBlock * >	BlockContainerType

typedef std::vector< Parameter >	ParameterContainerType

typedef std::vector< NetlistPort * >	PortContainerType

typedef std::vector< NetlistPortGroup * >	PortGroupContainerType

Protected Member Functions inherited from ProGe::BaseNetlistBlock
Netlist &	netlist ()

virtual NetlistPort &	port (size_t index)

void	setModuleName (const std::string &name)

void	addSubBlock (BaseNetlistBlock *subBlock, const std::string &instanceName="")

void	deleteSubBlock (BaseNetlistBlock *subBlock)

void	removeSubBlock (BaseNetlistBlock *subBlock)

NetlistPort *	addPort (NetlistPort *port)

void	removePort (NetlistPort *port)

void	addPortGroup (NetlistPortGroup *portGroup)

void	removePortGroup (NetlistPortGroup *portGroup)

void	setParameter (const Parameter &param)

void	addParameter (const Parameter &param)

Parameter &	parameter (const std::string &name)

NetlistPort *	findPort (const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const

void	addPackage (const std::string &packageName)

void	connectClocks ()

void	connectResets ()

Detailed Description

Represents a hardware block in the netlist.

Definition at line 61 of file NetlistBlock.hh.

Constructor & Destructor Documentation

◆ NetlistBlock()

ProGe::NetlistBlock::NetlistBlock	(	const std::string &	moduleName,
		const std::string &	instanceName,
		BaseNetlistBlock *	parent = `NULL`
	)

Constructor. Creates a netlist with no ports.

The created is empty. Only its name, the parent netlist and the name of the instance module are defined.

Parameters

moduleName	Name of the module.
instanceName	Name of the instance of the module.
netlist	The netlist which the belongs to.

Definition at line 68 of file NetlistBlock.cc.

71 : BaseNetlistBlock(moduleName, instanceName, parent) {}

Referenced by shallowCopy().

◆ ~NetlistBlock()

ProGe::NetlistBlock::~NetlistBlock ( )

virtual

The destructor.

Deletes all the ports.

Definition at line 78 of file NetlistBlock.cc.

78 {

79 }

Member Function Documentation

◆ addPackage()

void ProGe::BaseNetlistBlock::addPackage

Definition at line 687 of file BaseNetlistBlock.cc.

                                                          {
     if (!ContainerTools::containsValue(packages_, packageName)) {
         packages_.push_back(packageName);
     }
 }

Referenced by PlatformIntegrator::copyProgeBlockToNetlist(), ProGe::NetlistGenerator::generate(), DefaultICDecoderGenerator::generateDebuggerCode(), and shallowCopy().

◆ addParameter()

void ProGe::BaseNetlistBlock::addParameter

Adds new parameter to the block. Throws exception if the block has the parameter by the name already.

Definition at line 547 of file BaseNetlistBlock.cc.

                                                      {
     // Check for uniqueness //
     for (Parameter& p : parameters_) {
         if (p.name() == param.name()) {
             throw ObjectAlreadyExists(
                 __FILE__, __LINE__,
                 "The block \"" + name() + "\" already has parameter\"" +
                     param.name() + "\"");
         }
     }
  
     // Check if parameter's value refers to a constant //
     if (param.valueIsConstant()) {
         std::string packageName = param.packageNameOfConstant();
         assert(!packageName.empty());
         addPackage(packageName);
     }
  
     parameters_.push_back(param);
 }

Referenced by ProGe::NetlistGenerator::addGCUToNetlist().

◆ addPort()

NetlistPort * ProGe::BaseNetlistBlock::addPort

Adds port to this block and acquires ownership of it.

Added port will point to this block after the call.

Exceptions

ObjectAlreadyExists Thrown if the netlist block already has a port by same name.

Definition at line 467 of file BaseNetlistBlock.cc.

                                            {
     assert(port != nullptr && "Attempted to add null port.");
     if (findPort(port->name(), false, false)) {
         THROW_EXCEPTION(
             ObjectAlreadyExists,
             "Given port by name (" + port->name() +
                 ") already exists in the netlist block (" +
                 this->instanceName() + " : " + this->moduleName() + ").");
     }
  
     if (!port->hasParentBlock() || &port->parentBlock() != this) {
         port->setParent(this);
     }
     ports_.push_back(port);
     netlist_->registerPort(*port);
     if (parent_ != nullptr) {
         parent_->netlist_->registerPort(*port);
     }
     return port;
 }

◆ addPortGroup()

void ProGe::BaseNetlistBlock::addPortGroup

Definition at line 508 of file BaseNetlistBlock.cc.

                                                           {
     portGroups_.push_back(portGroup);
     portGroup->setParent(this);
     for (size_t i = 0; i < portGroup->portCount(); i++) {
         if (!netlist().isRegistered(portGroup->portAt(i))) {
             addPort(&portGroup->portAt(i));
         }
     }
 }

Referenced by ProGe::NetlistGenerator::addFUExternalPortsToNetlist(), ProGe::NetlistGenerator::addGCUToNetlist(), AlmaIFIntegrator::initAlmaifBlock(), and shallowCopy().

◆ addSubBlock()

void ProGe::BaseNetlistBlock::addSubBlock

Adds sub block to this block and acquires ownership of it.

Parameters

subBlock	The block to be added.
instanceName	The instance base name to be given for sub block. If the given or sub block's instance name is not unique within the block The name will be prefixed with a running number.

Definition at line 405 of file BaseNetlistBlock.cc.

                                                                {
     if (!instanceName.empty()) {
         subBlock->instanceName_ =
             NetlistTools::getUniqueInstanceName(*this, instanceName);
     } else {
         if (subBlock->instanceName().empty()) {
             subBlock->setInstanceName(NetlistTools::getUniqueInstanceName(
                 *this, subBlock->moduleName() + "_inst0"));
         } else {
             subBlock->setInstanceName(NetlistTools::getUniqueInstanceName(
                 *this, subBlock->instanceName()));
         }
     }
  
     assert(!subBlock->hasParentBlock() || &subBlock->parentBlock() == this);
     subBlock->setParent(this);
     subBlocks_.push_back(subBlock);
  
     // Register ports of the subblock so connections can be made.
     for (size_t i = 0; i < subBlock->portCount(); i++) {
         netlist_->registerPort(subBlock->port(i));
     }
 }

Referenced by ProGe::NetlistGenerator::addBaseRFToNetlist(), ProGe::NetlistGenerator::addFUToNetlist(), ProGe::NetlistGenerator::addGCUToNetlist(), ProGe::NetlistGenerator::addGeneratableFUsToNetlist(), DefaultICGenerator::addICToNetlist(), XilinxBlockRamGenerator::addMemory(), MemoryGenerator::addMemory(), DefaultICDecoderGenerator::addRV32MicroCode(), MemoryGenerator::connectPorts(), PlatformIntegrator::copyProgeBlockToNetlist(), MemoryGenerator::createMemoryNetlistBlock(), and DefaultICDecoderGenerator::generateDebuggerCode().

◆ netlist() [1/2]

Netlist& ProGe::BaseNetlistBlock::netlist

◆ netlist() [2/2]

Netlist & ProGe::BaseNetlistBlock::netlist

Definition at line 348 of file BaseNetlistBlock.cc.

                                 {
     return *netlist_;
 }

Referenced by ProGe::NetlistGenerator::addBaseRFToNetlist(), ProGe::NetlistGenerator::addFUExternalPortsToNetlist(), ProGe::NetlistGenerator::addFUToNetlist(), ProGe::NetlistGenerator::addGCUToNetlist(), ProGe::NetlistGenerator::addGeneratableFUsToNetlist(), DefaultDecoderGenerator::addGlockPortToDecoder(), DefaultICGenerator::addICToNetlist(), DefaultDecoderGenerator::addLockReqPortToDecoder(), XilinxBlockRamGenerator::addMemory(), DefaultICDecoderGenerator::addRV32MicroCode(), DefaultDecoderGenerator::completeDecoderBlock(), ProGe::Netlist::connectClocks(), AlteraHibiDpRamGenerator::connectPorts(), MemoryGenerator::connectPorts(), ProGe::Netlist::connectResets(), PlatformIntegrator::connectToplevelPort(), PlatformIntegrator::copyProgeBlockToNetlist(), DefaultICDecoderGenerator::generateDebuggerCode(), AlmaIFIntegrator::initAlmaifBlock(), AlmaIFIntegrator::integrateCore(), PlatformIntegrator::integrateCore(), and shallowCopy().

◆ package()

const std::string & ProGe::BaseNetlistBlock::package

Definition at line 699 of file BaseNetlistBlock.cc.

                                           {
     return packages_.at(idx);
 }

Referenced by PlatformIntegrator::copyProgeBlockToNetlist().

◆ packageCount()

size_t ProGe::BaseNetlistBlock::packageCount

Definition at line 694 of file BaseNetlistBlock.cc.

                                      {
     return packages_.size();
 }

Referenced by PlatformIntegrator::copyProgeBlockToNetlist().

◆ parameter() [1/3]

Parameter & ProGe::BaseNetlistBlock::parameter

Returns a Parameter object by name.

Exceptions

NotAvailable Thrown if the block does not have such Parameter.

Definition at line 217 of file BaseNetlistBlock.cc.

                                                  {
     for (size_t i = 0; i < parameterCount(); i++) {
         if (parameters_.at(i).name() == name) {
             return parameters_.at(i);
         }
     }
  
     throw NotAvailable(
         __FILE__, __LINE__, __func__,
         std::string("The block (") + instanceName() + ":" + moduleName() +
             ") does not have parameter \"" + name + "\"");
 }

◆ parameter() [2/3]

const Parameter & ProGe::BaseNetlistBlock::parameter

Returns a Parameter object by name.

Exceptions

NotAvailable Thrown if the block does not have such Parameter.

Definition at line 198 of file BaseNetlistBlock.cc.

                                                        {
     for (size_t i = 0; i < parameterCount(); i++) {
         if (parameter(i).name() == name) {
             return parameter(i);
         }
     }
  
     throw NotAvailable(
         __FILE__, __LINE__, __func__,
         std::string("The block (") + instanceName() + ":" + moduleName() +
             ") does not have parameter \"" + name + "\"");
 }

Referenced by ProGe::NetlistGenerator::addBaseRFToNetlist(), ProGe::NetlistGenerator::addFUExternalPortsToNetlist(), PlatformIntegrator::copyProgeBlockToNetlist(), SOPCBuilderFileGenerator::writeGenerics(), and IPXactFileGenerator::writeProjectFiles().

◆ parameter() [3/3]

const Parameter & ProGe::BaseNetlistBlock::parameter

Definition at line 236 of file BaseNetlistBlock.cc.

                                               {
     if (index >= parameterCount()) {
         throw OutOfRange(__FILE__, __LINE__, __func__);
     }
  
     return parameters_.at(index);
 }

◆ parentBlock() [1/2]

NetlistBlock & ProGe::NetlistBlock::parentBlock ( ) const

overridevirtual

Returns the parent .

Returns: The parent .

Exceptions

InstanceNotFound If the does not have a parent .

Reimplemented from ProGe::BaseNetlistBlock.

Definition at line 126 of file NetlistBlock.cc.

                                 {
     if (!hasParentBlock()) {
         const string procName = "NetlistBlock::parentBlock";
         throw InstanceNotFound(__FILE__, __LINE__, procName);
     }
  
     // todo: fix parentblock may not be NetlistBlock.
     return *dynamic_cast<const NetlistBlock*>(
         &BaseNetlistBlock::parentBlock());
 }

References ProGe::BaseNetlistBlock::hasParentBlock(), and ProGe::BaseNetlistBlock::parentBlock().

Referenced by DefaultDecoderGenerator::addGlockPortToDecoder(), DefaultDecoderGenerator::addLockReqPortToDecoder(), and DefaultICDecoderGenerator::generateDebuggerCode().

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◆ parentBlock() [2/2]

virtual NetlistBlock& ProGe::NetlistBlock::parentBlock ( )

overridevirtual

Reimplemented from ProGe::BaseNetlistBlock.

◆ port() [1/4]

NetlistPort * ProGe::NetlistBlock::port	(	const std::string &	portName,
		bool	partialMatch = `true`
	)

virtual

Definition at line 97 of file NetlistBlock.cc.

                                                                {
     return BaseNetlistBlock::findPort(portName, false, partialMatch);
 }

References ProGe::BaseNetlistBlock::findPort().

Referenced by DefaultICGenerator::addICToNetlist(), ProGe::GeneratableFUNetlistBlock::addInOperand(), Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), MemoryGenerator::addMemory(), ProGe::GeneratableFUNetlistBlock::addOutOperand(), DefaultICDecoderGenerator::addRV32MicroCode(), SOPCBuilderFileGenerator::countAvalonMMMasters(), SOPCBuilderFileGenerator::createInterfaces(), AlmaIFIntegrator::exportUnconnectedPorts(), PlatformIntegrator::exportUnconnectedPorts(), DefaultICDecoderGenerator::generateDebuggerCode(), AlmaIFIntegrator::integrateCore(), PlatformIntegrator::integrateCore(), MemoryGenerator::isCompatible(), IPXactClkInterface::mapPortsToInterface(), IPXactResetInterface::mapPortsToInterface(), IPXactHibiInterface::mapPortsToInterface(), Stratix3DevKitIntegrator::mapToplevelPorts(), Stratix2DSPBoardIntegrator::mapToplevelPorts(), DefaultDecoderGenerator::opcodeWidth(), shallowCopy(), DefaultDecoderGenerator::writeControlRegisterMappings(), DefaultICGenerator::writeInterconnectionNetwork(), and IPXactFileGenerator::writeProjectFiles().

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◆ port() [2/4]

const NetlistPort * ProGe::BaseNetlistBlock::port

Returns a port that matches (partially) the given name.

Returns: The matching port. If not found, returns nullptr.

Definition at line 317 of file BaseNetlistBlock.cc.

                                                                          {
     return findPort(portName, false, partialMatch);
 }

◆ port() [3/4]

NetlistPort & ProGe::BaseNetlistBlock::port

Definition at line 322 of file BaseNetlistBlock.cc.

                                    {
     return *ports_.at(index);
 }

◆ port() [4/4]

const NetlistPort & ProGe::BaseNetlistBlock::port

Definition at line 253 of file BaseNetlistBlock.cc.

                                          {
     return *ports_.at(index);
 }

◆ portCount()

size_t ProGe::BaseNetlistBlock::portCount

Return port count in this block including ports from netlist port groups.

Definition at line 248 of file BaseNetlistBlock.cc.

                                   {
     return ports_.size();
 }

Referenced by XilinxBlockRamGenerator::addMemory(), MemoryGenerator::addMemory(), SOPCBuilderFileGenerator::countAvalonMMMasters(), SOPCBuilderFileGenerator::createInterfaces(), AlmaIFIntegrator::exportUnconnectedPorts(), PlatformIntegrator::exportUnconnectedPorts(), AlmaIFIntegrator::integrateCore(), IPXactClkInterface::mapPortsToInterface(), IPXactResetInterface::mapPortsToInterface(), IPXactHibiInterface::mapPortsToInterface(), Stratix3DevKitIntegrator::mapToplevelPorts(), Stratix2DSPBoardIntegrator::mapToplevelPorts(), and IPXactFileGenerator::writeProjectFiles().

◆ removePort() [1/2]

void ProGe::NetlistBlock::removePort ( NetlistPort & port )

◆ removePort() [2/2]

void ProGe::BaseNetlistBlock::removePort

Removes the given port from the block.

After call the port is parent block reference is set to nullptr.

Definition at line 494 of file BaseNetlistBlock.cc.

                                               {
     assert(
         &port->parentBlock() == this &&
         "Attempted to remove a port the block does not have.");
  
     netlist().unregisterPort(*port);
     if (this->hasParentBlock()) {
         parentBlock().netlist().unregisterPort(*port);
     }
     ContainerTools::removeValueIfExists(ports_, port);
     port->setParent(nullptr);
 }

◆ setParameter() [1/2]

void ProGe::BaseNetlistBlock::setParameter

Adds parameter to the block overwriting the existing one by name.

Definition at line 532 of file BaseNetlistBlock.cc.

                                                      {
     for (Parameter& p : parameters_) {
         if (p.name() == param.name()) {
             p = param;
             return;
         }
     }
     parameters_.push_back(param);
 }

◆ setParameter() [2/2]

void ProGe::NetlistBlock::setParameter	(	const std::string &	name,
		const std::string &	type,
		const std::string &	value
	)

Sets the given parameter for the .

Parameters

name	Name of the parameter.
type	Type of the parameter.
value	Value of the parameter.

Definition at line 89 of file NetlistBlock.cc.

                             {
     setParameter(Parameter(name, type, value));
 }

References ProGe::BaseNetlistBlock::name(), and ProGe::BaseNetlistBlock::Parameter.

Referenced by ProGe::NetlistGenerator::addBaseRFToNetlist(), ProGe::NetlistGenerator::addFUExternalPortsToNetlist(), ProGe::NetlistGenerator::addFUToNetlist(), AlteraMemGenerator::addGenerics(), DefaultICDecoderGenerator::addInstructioRegisterBypass(), Stratix2SramGenerator::addMemory(), AlmaIFIntegrator::connectCoreMemories(), PlatformIntegrator::copyProgeBlockToNetlist(), MemoryGenerator::createMemoryNetlistBlock(), DefaultICDecoderGenerator::generate(), AlmaIFIntegrator::initAlmaifBlock(), and shallowCopy().

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◆ shallowCopy()

NetlistBlock * ProGe::NetlistBlock::shallowCopy ( const std::string & instanceName ) const

Copies the block without its children or internal connections - leaving only the outer portion of the block.

Parameters

instanceName New instance name for the copy

Returns: Pointer to the netlist copy

Definition at line 161 of file NetlistBlock.cc.

                                                              {
     NetlistBlock* block =
         new NetlistBlock(this->moduleName(), instanceName, NULL);
  
     for (size_t i = 0; i < this->parameterCount(); i++) {
         block->setParameter(this->parameter(i));
     }
     for (size_t i = 0; i < netlist().parameterCount(); i++) {
         block->netlist().setParameter(this->netlist().parameter(i));
     }
     // Copy ports while preserving their insertion order.
     std::map<std::string, NetlistPort*> copiedPorts;
     for (size_t i = 0; i < portCount(); i++) {
         NetlistPort* copiedPort = nullptr;
         copiedPort = BaseNetlistBlock::port(i).copyTo(*block);
         copiedPorts.insert({{copiedPort->name(), copiedPort}});
     }
     for (size_t i = 0; i < portGroupCount(); i++) {
         const NetlistPortGroup* portGrp = &portGroup(i);
         // Cloning to copy original class type, but clear ports as they are
         // already created and added to the new block.
         NetlistPortGroup* newGroup = portGrp->clone();
         newGroup->clear();
         for (auto port : *portGrp) {
             newGroup->addPort(*copiedPorts.at(port->name()));
         }
         block->addPortGroup(newGroup);
     }
  
     for (size_t i = 0; i < packageCount(); i++) {
         block->addPackage(this->package(i));
     }
  
     return block;
 }

Referenced by PlatformIntegrator::copyProgeBlockToNetlist().

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◆ subBlock()

NetlistBlock & ProGe::NetlistBlock::subBlock ( size_t index )

overridevirtual

Returns a sub by the given index.

Parameters

index The index.

Returns: The sub .

Exceptions

OutOfRange If the given index is negative or not smaller than the number of sub blocks.

Reimplemented from ProGe::BaseNetlistBlock.

Definition at line 110 of file NetlistBlock.cc.

                                    {
     if (index >= subBlockCount()) {
         throw OutOfRange(__FILE__, __LINE__, __func__);
     }
  
     // todo check for and throw wrong subblass
     return *dynamic_cast<NetlistBlock*>(&BaseNetlistBlock::subBlock(index));
 }

References __func__, ProGe::BaseNetlistBlock::subBlock(), and ProGe::BaseNetlistBlock::subBlockCount().

Referenced by FUGen::FUGen(), and DefaultICDecoderGenerator::generateDebuggerCode().

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◆ subBlockCount()

size_t ProGe::BaseNetlistBlock::subBlockCount

Definition at line 150 of file BaseNetlistBlock.cc.

                                       {
     return subBlocks_.size();
 }

Referenced by ProGe::Netlist::connectClocks(), ProGe::Netlist::connectResets(), FUGen::FUGen(), and DefaultICDecoderGenerator::generateDebuggerCode().

◆ write()

void ProGe::NetlistBlock::write	(	const Path &	targetBaseDir,
		HDL	targetLang = `VHDL`
	)		const

overridevirtual

Writes self if non-empty and calls write() function of each sub block.

Reimplemented from ProGe::BaseNetlistBlock.

Definition at line 201 of file NetlistBlock.cc.

                                                                    {
     if (netlist().hasConnections()) {
         NetlistWriter* writer;
         std::string topLevelDir = "";
         if (targetLang == ProGe::VHDL) {
             writer = new VHDLNetlistWriter(*this);
             topLevelDir = targetBaseDir.string() +
                           FileSystem::DIRECTORY_SEPARATOR + "vhdl";
         } else if (targetLang == ProGe::Verilog) {
             writer = new VerilogNetlistWriter(*this);
             topLevelDir = targetBaseDir.string() +
                           FileSystem::DIRECTORY_SEPARATOR + "verilog";
         } else {
             assert(false && "Unsupported HDL.");
         }
  
         if (!FileSystem::fileExists(topLevelDir)) {
             bool directoryCreated = FileSystem::createDirectory(topLevelDir);
             if (!directoryCreated) {
                 std::string errorMsg =
                     "Unable to create directory " + topLevelDir + ".";
                 throw IOException(__FILE__, __LINE__, __func__, errorMsg);
             }
         }
  
         writer->write(topLevelDir);
         delete writer;
     }
  
     BaseNetlistBlock::write(targetBaseDir, targetLang);
 }

References __func__, assert, FileSystem::createDirectory(), FileSystem::DIRECTORY_SEPARATOR, FileSystem::fileExists(), ProGe::BaseNetlistBlock::netlist(), ProGe::Verilog, ProGe::VHDL, ProGe::NetlistWriter::write(), and ProGe::BaseNetlistBlock::write().

Referenced by ProGe::ProcessorGenerator::generateProcessor().

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The documentation for this class was generated from the following files:

Public Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ NetlistBlock()

◆ ~NetlistBlock()

Member Function Documentation

◆ addPackage()

◆ addParameter()

◆ addPort()

◆ addPortGroup()

◆ addSubBlock()

◆ netlist() [1/2]

◆ netlist() [2/2]

◆ package()

◆ packageCount()

◆ parameter() [1/3]

◆ parameter() [2/3]

◆ parameter() [3/3]

◆ parentBlock() [1/2]

◆ parentBlock() [2/2]

◆ port() [1/4]

◆ port() [2/4]

◆ port() [3/4]

◆ port() [4/4]

◆ portCount()

◆ removePort() [1/2]

◆ removePort() [2/2]

◆ setParameter() [1/2]

◆ setParameter() [2/2]

◆ shallowCopy()

◆ subBlock()

◆ subBlockCount()

◆ write()