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38 #include <boost/timer.hpp>
100 scheduledProcedure_(NULL), bigDDG_(bigDDG),
101 softwareBypasser_(bypasser), delaySlotFiller_(delaySlotFiller),
102 basicBlocksScheduled_(0), totalBasicBlocks_(0), progressBar_(NULL) {
127 static const TCEString SP_DATUM =
"STACK_POINTER";
128 static const TCEString FP_DATUM =
"FRAME_POINTER";
129 static const TCEString RV_DATUM =
"RV_REGISTER";
131 static const TCEString RV_HIGH_DATUM =
"RV_HIGH_REGISTER";
136 bool bbScheduled =
false;
154 std::vector<DDGPass*> bbSchedulers;
178 <<
"CFG detects single BB loop" << std::endl
179 <<
"tripcount: " << bb.
tripCount() << std::endl;
183 if (analysis != NULL) {
188 <<
"loop analyzis analyzed loop to have fixed trip count"
194 <<
"loop analyzis analyzed loop to have variable trip count"
209 setLoopLimits(analysis);
214 <<
"executing loop pass with trip count " << bb.
tripCount()
219 bb, targetMachine, irm, bbSchedulers, bbn) ) {
224 <<
"loop scheduler failed, using basic block "
225 <<
"scheduler instead" << std::endl;
235 bb, targetMachine, irm, bbSchedulers, bbn);
259 std::cerr <<
"Wargning: BB liverange data null for: "
262 for (
unsigned int i = 0; i < bbSchedulers.size(); i++)
263 delete bbSchedulers[i];
266 #ifdef DEBUG_REG_COPY_ADDER
267 static int graphCount = 0;
295 const bool enableProgressBar =
false;
297 if (enableProgressBar) {
325 (boost::format(
"proc_%s_before_scheduling.dot") %
331 (boost::format(
"proc_%s_before_scheduling.xml") %
340 #ifdef BIG_DDG_SNAPSHOTS
369 (boost::format(
"proc_%s_after_scheduling.dot") %
bigDDG_->
name())
375 (boost::format(
"proc_%s_after_scheduling.xml") %
bigDDG_->
name())
427 return "Instruction scheduler with a basic block scope.";
441 "Basic block scheduler that uses the longest path information of "
442 "data dependency graph to prioritize the ready list. Assumes that "
443 "the input has registers allocated and no connectivity missing.";
480 static int bbNumber = 0;
483 if (ddgPasses.size() > 1) {
484 for (
unsigned int i = 0; i < ddgPasses.size(); i++) {
492 ddgPasses[i]->handleDDG(*ddg, *rm, targetMachine, minCycle,
true);
522 std::string name =
"scheduling";
527 ddgPasses[fastest]->handleDDG(*ddg, *rm, targetMachine, minCycle);
538 std::string name =
"scheduling";
568 <<
"DDG height " << ddg->
height() << std::endl;
580 if (procName ==
"") procName = cfg.
name();
616 for (
int bbIndex = 0; bbIndex < nodeCount; ++bbIndex) {
629 for (
int bbIndex = 0; bbIndex < nodeCount; ++bbIndex) {
632 if (jumpDest !=
nullptr && jumpDest->isNormalBB()) {
643 for (
int bbIndex = cfg.
nodeCount() -1; bbIndex >= 0; --bbIndex) {
646 if (jumpDest ==
nullptr || !jumpDest->isNormalBB()) {
653 bbIndex = nodeCount -1;
658 for (
int bbIndex = cfg.
nodeCount() -1; bbIndex >= 0; --bbIndex) {
662 bbIndex = nodeCount -1;
void addResourceManager(TTAProgram::BasicBlock &bbn, SimpleResourceManager &rm)
@ SINGLE_BB_LOOP_ANTIDEPS
virtual bool isLoopOptDefined() const
virtual void handleCFGDDG(ControlFlowGraph &cfg, DataDependenceGraph *ddg, const TTAMachine::Machine &targetMachine)
std::string toString() const
void copyToProcedure(TTAProgram::Procedure &proc, TTAProgram::InstructionReferenceManager *irm=NULL)
Node & node(const int index) const
void bbnScheduled(BasicBlockNode &bbn)
DataDependenceGraph * bigDDG_
whole-procedure DDG.
virtual void handleProgram(TTAProgram::Program &program, const TTAMachine::Machine &targetMachine) override
MoveNodeUseMapSet regDefines_
LLVMTCECmdLineOptions * options_
void updateReferencesFromProcToCfg()
void setCFG(const ControlFlowGraph *cfg)
virtual DataDependenceGraphBuilder & ddgBuilder()
static int verboseLevel()
static std::ostream & logStream()
virtual bool executeLoopPass(TTAProgram::BasicBlock &bb, const TTAMachine::Machine &targetMachine, TTAProgram::InstructionReferenceManager &irm, std::vector< DDGPass * > ddgPasses, BasicBlockNode *bbn=NULL)
void initialize(ControlFlowGraph &cfg, DataDependenceGraph &ddg, const TTAMachine::Machine &machine)
TTAProgram::InstructionReferenceManager & instructionReferenceManager()
MoveNodeUseMapSet regDefReaches_
static LoopAnalysisResult * analyze(BasicBlockNode &bbn, DataDependenceGraph &ddg)
virtual bool dumpDDGsDot() const
static std::string toString(const T &source)
static const int MAXIMUM_II
bool useBUScheduler() const
virtual void clearOldResources()
virtual std::string longDescription() const override
bool handleBBNode(ControlFlowGraph &cfg, BasicBlockNode &bbn, const TTAMachine::Machine &targetMachine, int nodeCount)
TTAProgram::BasicBlock & basicBlock()
static const int DEFAULT_LOWMEM_MODE_THRESHOLD
DataDependenceGraph * createSubgraph(NodeSet &nodes, bool includeLoops=false)
void writeToXMLFile(std::string fileName) const
void updateHWloopLength(unsigned len)
virtual int lowMemModeThreshold() const
bool useBubbleFish2Scheduler() const
void fillDelaySlots(ControlFlowGraph &cfg, DataDependenceGraph &ddg, const TTAMachine::Machine &machine)
#define abortWithError(message)
void setTripCount(unsigned count)
MoveNode * counterValueNode
virtual ~BBSchedulerController()
LiveRangeData * liveRangeData_
virtual int instructionCount() const
CopyingDelaySlotFiller * delaySlotFiller_
static CmdLineOptions * cmdLineOptions()
ControlFlowGraph * cfg_
Control flow graph of the procedure.
MoveNodeUseMapSet regFirstDefines_
boost::progress_display * progressBar_
Fancy progress bar. Pointer because creation outputs the initial progress bar and we want it only on ...
MoveNodeUseMapSet regLastUses_
virtual void executeDDGPass(TTAProgram::BasicBlock &bb, const TTAMachine::Machine &targetMachine, TTAProgram::InstructionReferenceManager &irm, std::vector< DDGPass * > ddgPasses, BasicBlockNode *bbn=NULL) override
virtual Instruction & lastInstruction() const
std::string errorMessageStack(bool messagesOnly=false) const
int smallestCycle() const
static void disposeRM(SimpleResourceManager *rm, bool allowReuse=true)
BasicBlockNode * jumpSuccessor(BasicBlockNode &bbn)
bool isSingleBBLoop(const BasicBlockNode &node) const
bool allScheduledInBetween(const BasicBlockNode &src, const BasicBlockNode &dst) const
bool hasDatum(const std::string &key) const
virtual bool dumpDDGsXML() const
static void copyRMToBB(SimpleResourceManager &rm, TTAProgram::BasicBlock &bb, const TTAMachine::Machine &targetMachine, TTAProgram::InstructionReferenceManager &irm, int lastCycle=-1)
static SimpleResourceManager * createRM(const TTAMachine::Machine &machine, unsigned int ii=0)
virtual void writeToDotFile(const TCEString &fileName) const
static std::set< const TTAMachine::RegisterFile *, TTAMachine::MachinePart::Comparator > tempRegisterFiles(const TTAMachine::Machine &machine)
virtual std::string shortDescription() const override
static MachInfoCmdLineOptions options
void setScheduled(bool state=true)
InterPassData & interPassData()
std::set< TCEString > registersUsedAfter_
const BasicBlockNode * predecessor() const
void analyzePreSchedule()
unsigned tripCount() const
in case the BB is inside a loop and trip count is known, returns it, otherwise returns 0
virtual void handleControlFlowGraph(ControlFlowGraph &cfg, const TTAMachine::Machine &targetMachine) override
void setDDG(const DataDependenceGraph *ddg)
bool useTDScheduler() const
BBSchedulerController(const TTAMachine::Machine &targetMachine, InterPassData &data, SoftwareBypasser *bypasser=NULL, CopyingDelaySlotFiller *delaySlotFiller=NULL, DataDependenceGraph *bigDDG=NULL)
virtual DataDependenceGraph * build(ControlFlowGraph &cGraph, DataDependenceGraph::AntidependenceLevel antidependenceLevel, const TTAMachine::Machine &mach, const UniversalMachine *um=NULL, bool createMemAndFUDeps=true, bool createDeathInformation=true, llvm::AliasAnalysis *AA=NULL)
int totalBasicBlocks_
Total basic blocks in the CFG currently being scheduled.
virtual DataDependenceGraph * createDDGFromBB(TTAProgram::BasicBlock &bb, const TTAMachine::Machine &mach)
void setBBN(const BasicBlockNode *bbn)
SoftwareBypasser * softwareBypasser_
The software bypasser to use to bypass registers when possible.
bool printResourceConstraints() const
TCEString procedureName() const
void ddgSnapshot(DataDependenceGraph *ddg, std::string &name, DataDependenceGraph::DumpFileFormat format, bool final)
find Finds info of the inner loops in the program
bool isInInnerLoop() const
returns true in case the BB is known to be inside an inner loop
TTAProgram::Procedure * scheduledProcedure_
The currently scheduled procedure.
int basicBlocksScheduled_
Number of basic blocks scheduled so far.
virtual const TCEString & name() const
virtual void handleProcedure(TTAProgram::Procedure &procedure, const TTAMachine::Machine &targetMachine) override
virtual void handleBasicBlock(TTAProgram::BasicBlock &bb, const TTAMachine::Machine &targetMachine, TTAProgram::InstructionReferenceManager &irm, BasicBlockNode *bbn=NULL) override
virtual void handleControlFlowGraph(ControlFlowGraph &cfg, const TTAMachine::Machine &mach) override
static void executeProcedurePass(TTAProgram::Program &program, const TTAMachine::Machine &targetMachine, ProcedurePass &procedurePass)
MoveNodeUseMapSet regFirstUses_
std::string toString() const