Go to the documentation of this file.
91 endCycle_(INT_MAX), bypass_(true), dre_(true), bypassDistance_(3) {
170 bool movesRemoved =
false;
204 std::string message =
" Move(s) did not get scheduled: ";
205 for (
int i = 0; i < moves.
nodeCount(); i++) {
218 debugLog(
"All moves in the DDG didn't get scheduled.");
224 std::string wtf =
"0";
235 std::cerr <<
"rm largest cycle bigger than endCycle_!" <<
236 std::endl <<
"This may break delay slot filler!" <<
238 " end cycle: " <<
endCycle_ << std::endl;
313 bool movesRemoved =
false;
346 std::string(
"_dag.dot"));
357 debugLog(
"All moves in the DDG didn't get scheduled.");
370 <<
"No overlapping instructions."
371 <<
"Should Revert to ordinary scheduler."
384 if (overlap_count >= tripCount) {
399 if (jumpLimit != NULL) {
405 int loopCounterStep = 1;
424 (jumpOverlapCount * loopCounterStep),
441 #ifdef DEBUG_REG_COPY_ADDER
442 static int graphCount = 0;
462 bool operandsFailed =
true;
463 bool resultsFailed =
true;
465 int maxResult = resultsStartCycle;
467 #ifdef DEBUG_REG_COPY_ADDER
470 (boost::format(
"%s_before_ddg.dot") %
ddg_->
name()).str());
477 #ifdef DEBUG_REG_COPY_ADDER
478 const int tempsAdded = copies.
count_;
481 #ifdef DEBUG_REG_COPY_ADDER
482 if (tempsAdded > 0) {
484 (boost::format(
"%s_after_regcopy_ddg.dot") %
ddg_->
name()).str());
497 int stopingPoint = (ii == 0) ?
500 while ((operandsFailed || resultsFailed) &&
501 resultsStartCycle >= stopingPoint) {
503 moves, resultsStartCycle, bypass, bypassLate);
504 if (maxResult != -1) {
505 resultsFailed =
false;
514 for (
int i = 0; i < moves.
nodeCount(); i++){
523 resultsFailed =
true;
524 if (bypass && bypassLate) {
527 }
else if (bypass && !bypassLate) {
530 }
else if (!bypass && bypassLate) {
542 operandsFailed =
false;
573 std::vector<MoveNode*> outputMoves;
578 for (
unsigned int i = 0; i < outputMoves.size(); i++) {
580 MoveNode& moveNode = *outputMoves[i];
586 operandsFailed =
true;
587 if (bypass && bypassLate) {
590 }
else if (bypass && !bypassLate) {
593 }
else if (!bypass && bypassLate) {
598 resultsStartCycle = std::min(maxResult, resultsStartCycle);
610 (boost::format(
"bb_%s_2_failed_scheduling.dot")
616 "Results scheduling failed for \'" + moves.
toString());
619 if (operandsFailed) {
624 (boost::format(
"bb_%s_2_scheduling.dot")
630 "Operands scheduling failed for \'" + moves.
toString());
633 for (
int i = 0; i < moves.
nodeCount(); i++) {
637 #ifdef DEBUG_REG_COPY_ADDER
638 if (tempsAdded > 0) {
640 (boost::format(
"%s_after_scheduler_ddg.dot") %
643 <<
"(operation fix #" <<
ddg_->
name() <<
")" << std::endl
670 int unscheduledMoves = 0;
671 int scheduledMoves = 0;
674 for (
int i = 0; i < moves.
nodeCount(); i++) {
684 cycle = (limit < cycle) ? limit : cycle;
689 while (unscheduledMoves != scheduledMoves && counter < 5 && cycle >=0) {
702 cycle = trigger->
cycle();
716 if (triggerLatest != INT_MAX &&
717 triggerLatest > trigger->
cycle()) {
726 cycle = trigger->
cycle();
732 for (
int moveIndex = 0; moveIndex < moves.
nodeCount(); ++moveIndex) {
751 for (
int moveIndex = 0; moveIndex < moves.
nodeCount(); ++moveIndex) {
759 if (moveNode.
cycle() > cycle) {
762 std::cerr <<
"Move " << moveNode.
toString()
763 <<
" is scheduled after the trigger!" << std::endl;
771 if (scheduledMoves != unscheduledMoves) {
772 for (
int i = 0; i < moves.
nodeCount(); i++){
789 if (scheduledMoves != unscheduledMoves) {
806 MoveNodeGroup& moves,
int cycle,
bool bypass,
bool bypassLate) {
807 int maxResultCycle = cycle;
808 int tempRegLimitCycle = cycle;
809 int localMaximum = 0;
810 bool resultScheduled =
false;
811 for (
int moveIndex = 0; moveIndex < moves.
nodeCount(); ++moveIndex) {
816 bool bypassSuccess =
false;
821 (boost::format(
"Move to schedule '%s' is not "
822 "result move!") % moveNode.
toString()).str());
826 bypassSuccess =
bypassNode(moveNode, newMaximum);
828 (newMaximum > localMaximum) ? newMaximum : localMaximum;
829 if (
dre_ && bypassSuccess &&
834 resultScheduled =
true;
848 if (firstWrite != NULL) {
850 tempRegLimitCycle = firstWrite->
cycle();
854 moveNode, moveNode, tempRegLimitCycle);
858 tempRegLimitCycle = std::min(test->
cycle() -1, cycle);
862 ? std::min(localMaximum +1, tempRegLimitCycle)
876 (localMaximum < newMaximum) ? newMaximum : localMaximum;
877 localMaximum = (localMaximum > cycle) ? localMaximum : cycle;
878 int originalCycle = moveNode.
cycle();
887 resultScheduled =
true;
890 (localMaximum < moveNode.
cycle())
891 ? moveNode.
cycle() : localMaximum;
894 (moveNode.
cycle() > maxResultCycle) ?
895 moveNode.
cycle() : maxResultCycle;
899 return (resultScheduled) ? localMaximum : maxResultCycle;
913 #ifdef DEBUG_REG_COPY_ADDER
916 (boost::format(
"%s_before_ddg.dot") %
ddg_->
name()).str());
927 #ifdef DEBUG_REG_COPY_ADDER
928 const int tempsAdded =
932 #ifdef DEBUG_REG_COPY_ADDER
936 #ifdef DEBUG_REG_COPY_ADDER
937 if (tempsAdded > 0) {
939 (boost::format(
"%s_after_regcopy_ddg.dot") %
ddg_->
name()).str());
961 MoveNode& moveNode,
int latestCycle,
bool allowPredicationAndRenaming) {
966 (boost::format(
"Move '%s' is already scheduled!")
978 (boost::format(
"Move '%s' needs to be scheduled in %d,"
979 " but data dependence does not allow it!")
980 % moveNode.
toString() % ddgCycle).str());
985 if (
renamer_ != NULL && allowPredicationAndRenaming) {
986 int latestFromTrigger =
989 int minRenamedEC = std::min(
991 moveNode, ii,
true));
994 if (minRenamedEC > ddgCycle) {
996 if (minRenamedEC > ddgCycle) {
998 moveNode, ii != 0,
true,
true, minRenamedEC)) {
1001 #ifdef THIS_IS_BUGGY_WITH_REGCOPY_ADDER
1006 if (limitingAdep != NULL) {
1014 *limitingAdep,
false,
true,
true)) {
1035 if (allowPredicationAndRenaming) {
1039 bool guardNeeded =
false;
1073 ddgCycle = (ddgCycle == INT_MAX) ?
endCycle_ : ddgCycle;
1077 int minCycle = std::min(latestCycle, ddgCycle);
1115 if (minCycle < earliestDDG) {
1119 if (minCycle == -1 || minCycle == INT_MAX) {
1127 std::string msg =
"Assignment of MoveNode " + moveNode.
toString();
1128 msg +=
" failed! Most likely missing Long Immediate Unit";
1129 msg +=
" or Instruction Template!";
1131 __FILE__, __LINE__,
__func__, msg);
1140 int localMaximum = 0;
1144 localMaximum = std::max(temp.
cycle(), localMaximum);
1147 if (localMaximum != 0 && localMaximum < minCycle) {
1154 localMaximum = std::max(earliestDDG, localMaximum);
1157 if (rmEarliest != -1 &&
1158 rmEarliest != INT_MAX &&
1159 rmEarliest < minCycle) {
1160 minCycle = rmEarliest;
1169 (boost::format(
"Assignment of MoveNode '%s' failed!")
1180 unsigned int epEndCycle = moveNode.
cycle() + hwop.
latency();
1198 return "Bottom-up list scheduler with a basic block scope.";
1212 "Bottom-up list basic block scheduler that uses the longest path "
1213 "information of data dependency graph to prioritize the ready list."
1214 "Assumes that the input has registers allocated and no connectivity "
1243 if (tempMove1 == NULL)
1247 if (tempMove2 != NULL) {
1254 if (firstWrite != NULL && firstWrite->
isScheduled())
1255 firstWriteCycle = firstWrite->
cycle();
1257 if (tempMove2 != NULL && tempMove2->
isScheduled()){
1258 firstWriteCycle = tempMove2->
cycle() -1;
1261 bool bypassSuccess =
false;
1302 for (DataDependenceGraph::EdgeSet::iterator i = inEdges.begin();
1303 i != inEdges.end(); ++i) {
1318 assert(tempMove == NULL &&
1319 "Multiple unscheduled moves for the operand move, should have "
1320 "max. one (the temporary move)!");
1328 if (firstRead != NULL) {
1330 lastUse = firstRead->
cycle();
1339 if (tempMove == NULL)
1344 std::cerr <<
"temp move: " << tempMove->
toString()
1379 if (tempMove1 == NULL)
1383 if (tempMove2 != NULL) {
1388 if (firstWrite != NULL) {
1390 lastUse = firstWrite->
cycle();
1394 bool bypassSuccess =
false;
1402 std::cerr <<
"not scheduled: " << tempMove1->
toString() << std::endl;
1429 for (DataDependenceGraph::NodeSet::iterator i = pred.begin();
1430 i != pred.end(); ++i) {
1438 "Multiple candidates for the temp move of result read.");
1450 int tempRegLimitCycle = cycle;
1463 if (firstWrite != NULL) {
1465 tempRegLimitCycle = firstWrite->
cycle();
1468 cycle = std::min(cycle, tempRegLimitCycle);
1495 for (DataDependenceGraph::NodeSet::iterator j =
1496 rrDestinations.begin(); j != rrDestinations.end(); j++) {
1509 node, destinationPorts)) {
1516 okDestination.insert(n);
1518 destinationPorts.clear();
1520 return okDestination;
1531 if (single == NULL) {
1533 std::vector<MoveNode*> destinationsVector =
1535 std::vector<std::pair<MoveNode*, int> > rescheduleVector;
1537 for (
unsigned int j = 0; j < destinationsVector.size(); j++) {
1539 MoveNode* dest = destinationsVector[j];
1549 rescheduleVector.push_back(
1550 std::pair<MoveNode*, int>(dest, originalCycle));
1553 for (
unsigned int i = 0; i < rescheduleVector.size(); i++) {
1555 std::pair<MoveNode*, int> dest = rescheduleVector[i];
1558 if (!dest.first->isScheduled()) {
1560 std::cerr <<
" Source: " << moveNode.
toString()
1561 <<
", Original: " << dest.first->toString() <<
1562 ", original cycle: " << dest.second << std::endl<< std::endl;
1564 assert(dest.first->isScheduled());
1585 std::cerr <<
" Source: " << moveNode.
toString()
1586 <<
", Original: " << single->
toString() <<
", original cycle: "
1587 << oCycle << std::endl;
1604 int& maxResultCycle) {
1605 bool edgesCopied =
false;
1606 unsigned int bypassCount = 0;
1607 int localMaximum = 0;
1611 unsigned int rawDestinations =
1615 if (destinations.size() > 0) {
1616 for (OrderedSet::iterator it = destinations.begin();
1617 it != destinations.end(); it++) {
1622 if (!(*it)->isScheduled() && temp == (*it)) {
1629 std::cerr <<
"\t\tSkipping temporary outgoing move " <<
1630 (*it)->toString() << std::endl;
1633 assert((*it)->isScheduled());
1634 int originalCycle = (*it)->cycle();
1637 if ((*it)->isDestinationVariable() && temp == (*it)) {
1646 (*it)->move().destination().registerFile(),
1647 (*it)->move().destination().index(),
1649 if (lastRead != NULL) {
1651 earliestLimit = lastRead->
cycle();
1655 (*it)->move().destination().registerFile(),
1656 (*it)->move().destination().index(),
1658 if (firstRead != NULL) {
1660 latestLimit = firstRead->
cycle();
1672 assert(!(*it)->isScheduled());
1675 std::cerr <<
"Merge fail. moveNode=" << moveNode.
toString()
1676 <<
", **it=" << (*it)->toString() << std::endl;
1682 if ((**it).move().source().isImmediateRegister()) {
1683 (**it).move().setSource(
1690 assert((*it)->isScheduled() ==
false);
1691 int startCycle = std::min(latestLimit, maxResultCycle);
1695 std::cerr <<
"\t\t\tCreated " << (*it)->toString()
1696 <<
" with original cycle " << originalCycle << std::endl;
1698 if (!(*it)->isScheduled() ||
1699 (*it)->cycle() > latestLimit ||
1700 (*it)->cycle() < earliestLimit ||
1701 (*it)->cycle() < originalCycle) {
1710 ((*it)->cycle() > localMaximum) ?
1711 (*it)->cycle() : localMaximum;
1727 if (rrDestinations.size() == 0 &&
1735 if (bypassCount == rawDestinations && bypassCount != 0) {
1736 maxResultCycle = localMaximum;
1748 std::map<const MoveNode*, DataDependenceGraph::NodeSet >::
1752 for (DataDependenceGraph::NodeSet::iterator i =
1753 tempMoves.begin(); i != tempMoves.end(); i++) {
1760 std::cerr <<
"\tDroping node " << node.
toString() << std::endl;
1764 copyDepsOver(node,
true,
true);
1772 for (DataDependenceGraph::NodeSet::iterator i =
1773 preds.begin(); i != preds.end(); i++) {
1776 std::map<const MoveNode*, DataDependenceGraph::NodeSet >::
1780 for (DataDependenceGraph::NodeSet::iterator i =
1781 tempMoves.begin(); i != tempMoves.end(); i++) {
1782 if ((*i)->isScheduled()) {
1786 std::cerr <<
"\tDroping temp move for node "
1787 << node.
toString() <<
", " << (*i)->toString()
1792 copyDepsOver(**i,
true,
true);
1811 predecessors.erase(&node);
1817 copyDepsOver(node,
true,
true);
1823 for (DataDependenceGraph::NodeSet::iterator iter =
1824 predecessors.begin();
1825 iter != predecessors.end(); iter++) {
1833 __FILE__, __LINE__,
__func__, msg);
1844 for (DataDependenceGraph::NodeSet::iterator i = scheduled.begin();
1845 i != scheduled.end(); ++i) {
1849 i = scheduled.begin();
1855 std::vector<MoveNode*> destinationsVector = (*it).second;
1856 for (
unsigned int k = 0; k < destinationsVector.size(); k++) {
1858 MoveNode* dest = destinationsVector[k];
1876 for (std::set<MoveNode*>::iterator i =
droppedNodes_.begin();
1917 if (triggerOperand != 0) {
1919 int latestMinCycle = -1;
1920 int firstMinCycle = INT_MAX;
1930 if (operandIndex != triggerOperand) {
1940 if (minCycle > latestMinCycle) {
1942 latestMinCycle = minCycle;
1944 if (minCycle < firstMinCycle) {
1945 firstMinCycle = minCycle;
1952 if (latestMinCycle == firstMinCycle) {
1955 if (latestMinCycle - firstMinCycle > 1) {
1956 if (lastOperand == triggerOperand) {
1961 if (lastOperand != triggerOperand) {
1989 for (DataDependenceGraph::EdgeSet::iterator i = inEdges.begin();
1990 i != inEdges.end(); i++) {
1996 if (wawPred == NULL) {
2004 if (wawPred == NULL) {
2015 for (DataDependenceGraph::NodeSet::iterator i = consumers.begin();
2016 i != consumers.end(); i++) {
2018 if (consumers2.find(mn) == consumers2.end() &&
2038 bool revert =
false;
const Operation & operation() const
MoveNode * lastScheduledRegisterRead(const TTAMachine::BaseRegisterFile &rf, int registerIndex, int lastCycleToTest=INT_MAX) const
virtual std::string longDescription() const
virtual NodeSet predecessors(const Node &node, bool ignoreBackEdges=false, bool ignoreForwardEdges=false) const
virtual bool isTriggering() const
DataDependenceGraph * ddg_
DDG of the currently scheduled BB.
virtual void connectNodes(const Node &nTail, const Node &nHead, Edge &e)
virtual bool writesMemory() const
BUBasicBlockScheduler(InterPassData &data, SoftwareBypasser *bypasser=NULL, RegisterRenamer *registerRenamer=NULL)
void removeIncomingGuardEdges(MoveNode &node)
void unschedule(MoveNode &moveNode)
OrderedSet findBypassDestinations(MoveNode &node)
virtual void removeEdge(Edge &e)
NodeSet regRawSuccessors(const MoveNode &node) const
void scheduleResultReadTempMoves(MoveNode &resultMove, MoveNode &resultRead, int lastUse)
bool isDestinationVariable() const
virtual Node & tailNode(const Edge &edge) const
void undoBypass(MoveNode &node, MoveNode *single=NULL, int originalCycle=-1)
virtual int largestCycle() const override
int scheduledNodeCount() const
std::string toString() const
virtual bool hasSideEffects() const
MoveNode & node(int index) const
virtual int index() const
MoveNode * succeedingTempMove(MoveNode ¤t)
MoveNode * firstScheduledRegisterWrite(const TTAMachine::BaseRegisterFile &rf, int registerIndex) const
Node & node(const int index) const
bool resultUsed(MoveNode &resultNode)
virtual const TTAMachine::RegisterFile & registerFile() const
bool isDestinationOperation() const
void scheduleMove(MoveNode &move, int cycle, bool allowPredicationandRenaming)
std::pair< MoveNode *, MoveNode * > findLoopLimitAndIndex(MoveNode &jumpMove)
std::set< MoveNode *, typename MoveNode ::Comparator > NodeSet
MoveNodeSelector * selector_
virtual int smallestCycle() const override
bool isUnconditional() const
std::set< MoveNode *, ltstr > OrderedSet
bool isAnyOutputAssigned()
void setAnnotation(const ProgramAnnotation &annotation)
virtual bool killDeadResults() const
Terminal & destination() const
virtual MoveNodeGroup candidates()
NodeSet scheduledMoves() const
virtual int numberOfInputs() const
void switchInputs(int idx1=1, int idx2=2)
void setGuard(MoveGuard *guard)
bool isSourceConstant() const
void unscheduleResultReadTempMoves(MoveNode &resultMove)
virtual void mightBeReady(MoveNode &node)
LLVMTCECmdLineOptions * options_
virtual void assign(int cycle, MoveNode &node, const TTAMachine::Bus *bus=NULL, const TTAMachine::FunctionUnit *srcFU=NULL, const TTAMachine::FunctionUnit *dstFU=NULL, int immWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1) override
static std::ostream & logStream()
virtual unsigned initiationInterval() const
virtual TCEString name() const
DependenceType dependenceType() const
virtual void unassign(MoveNode &node) override
virtual void dropNode(Node &node)
MoveNode * onlyRegisterRawSource(const MoveNode &mn, int allowGuardEdges=2, int backEdges=0) const
virtual bool dumpDDGsDot() const
static std::string toString(const T &source)
bool tryToSwitchInputs(ProgramOperation &op)
void moveFUDependenciesToTrigger(MoveNode &trigger)
int minCycle_
The earliest cycle to schedule moves in. Used to leave room for sched_yield() by the sched_yield() em...
NodeSet onlyRegisterRawDestinations(const MoveNode &mn, bool allowGuardEdges=false, bool allowBackEdges=false) const
bool mergeAndKeepUser(MoveNode &resultNode, MoveNode &userNode, bool force=false)
virtual void setCycleGrouping(bool flag)
virtual bool canSwap(int id1, int id2) const
static MoveNode * findTrigger(const ProgramOperation &po, const TTAMachine::Machine &mach)
const TTAMachine::Machine * targetMachine_
The target machine we are scheduling the program against.
ProgramOperation & sourceOperation() const
#define assert(condition)
virtual ~BUBasicBlockScheduler()
void ddgSnapshot(DataDependenceGraph &ddg, const std::string &name, DataDependenceGraph::DumpFileFormat format, bool final, bool resetCounter=false) const
virtual ControlUnit * controlUnit() const
virtual int operationIndex() const
#define abortWithError(message)
bool bypassNode(MoveNode &node, int &maxResultCycle)
bool isControlFlowMove() const
std::set< DataDependenceEdge *, typename DataDependenceEdge ::Comparator > EdgeSet
AddedRegisterCopies addRegisterCopiesToRRMove(MoveNode &moveNode, DataDependenceGraph *ddg)
virtual void removeNode(Node &node)
void unscheduleAllNodes()
void scheduleRRTempMoves(MoveNode ®ToRegMove, MoveNode &firstMove, int lastUse)
void initialize(DataDependenceGraph &ddg)
MoveNode * firstScheduledRegisterRead(const TTAMachine::BaseRegisterFile &rf, int registerIndex, int firstCycleToTest=0) const
MoveGuard & guard() const
static CmdLineOptions * cmdLineOptions()
static int canSourceWriteToAnyDestinationPort(const MoveNode &src, PortSet &ports, bool ignoreGuard=false)
void operandsScheduled(AddedRegisterCopies &copies, DataDependenceGraph &ddg)
bool renameSourceRegister(MoveNode &node, bool loopScheduling, bool allowSameRf, bool differentRfOnlyDirectlyReachable, int latestCycle=INT_MAX)
int latestTriggerWriteCycle() const
virtual int earliestCycle(MoveNode &node, const TTAMachine::Bus *bus=NULL, const TTAMachine::FunctionUnit *srcFU=NULL, const TTAMachine::FunctionUnit *dstFU=NULL, int immWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1) const override
virtual bool isGPR() const
bool tryToOptimizeWaw(const MoveNode &moveNode)
bool isSourceOperation() const
int smallestCycle() const
virtual int handleDDG(DataDependenceGraph &ddg, SimpleResourceManager &rm, const TTAMachine::Machine &targetMachine, int minCycle=0, bool testOnly=false)
void copyIncomingGuardEdges(const MoveNode &src, MoveNode &dst)
void unscheduleInputOperandTempMoves(MoveNode &operandMove)
void finalizeSchedule(MoveNode &node, BUMoveNodeSelector &selector)
void unMergeUser(MoveNode &resultNode, MoveNode &mergedNode, bool loopBypass=false)
virtual std::string shortDescription() const
int inputMoveCount() const
MoveNode * findLimitingAntidependenceDestination(MoveNode &mn)
bool hasNode(const Node &) const
virtual bool dumpDDGsXML() const
bool hasAnnotations(ProgramAnnotation::Id id=ProgramAnnotation::ANN_UNDEF_ID) const
std::string toString() const
std::map< MoveNode *, std::vector< const TTAMachine::Bus * >, MoveNode::Comparator > bypassDestinationsBus_
virtual EdgeSet inEdges(const Node &node) const
virtual int handleLoopDDG(DataDependenceGraph &ddg, SimpleResourceManager &rm, const TTAMachine::Machine &targetMachine, int tripCount, SimpleResourceManager *prologRM=NULL, bool testOnly=false)
virtual void writeToDotFile(const TCEString &fileName) const
bool scheduleOperand(MoveNode &, int cycle)
int outputMoveCount() const
RegisterRenamer * renamer_
int earliestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegWaRs=false, bool ignoreRegWaWs=false, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false, bool assumeBypassing=false) const
virtual const TTAMachine::FunctionUnit & functionUnit() const
unsigned int unsignedValue() const
SimpleResourceManager * rm_
Resource Manager of the currently scheduled BB.
bool isSourceVariable() const
void scheduleInputOperandTempMoves(MoveNode &resultMove, MoveNode &resultRead)
ProgramOperation & destinationOperation(unsigned int index=0) const
TTAProgram::Move & move()
std::map< MoveNode *, std::vector< MoveNode * >, MoveNode::Comparator > bypassDestinations_
InterPassData & interPassData()
std::set< MoveNode * > droppedNodes_
@ ANN_STACKFRAME_PROCEDURE_RETURN
precedure return jmp
void resultsScheduled(AddedRegisterCopies &copies, DataDependenceGraph &ddg)
int getTriggerOperand(const Operation &operation, const TTAMachine::Machine &machine)
void setMaxCycle(unsigned int maxCycle)
void scheduleRRMove(MoveNode &moveNode)
virtual bool canTransportImmediate(const MoveNode &node, const TTAMachine::Bus *preAssignedBus=NULL) const
bool exclusingGuards(const MoveNode &mn1, const MoveNode &mn2) const
bool scheduleOperandWrites(MoveNodeGroup &moves, int cycle)
bool renameDestinationRegister(MoveNode &node, bool loopScheduling, bool allowSameRf, bool differentRfOnlyDirectlyReachable, int earliestCycle=-1)
bool guardsAllowBypass(const MoveNode &defNode, const MoveNode &useNode, bool loopBypass=false)
virtual void notifyScheduled(MoveNode &node)
void setSelector(MoveNodeSelector *selector)
void copyOutgoingGuardWarEdges(const MoveNode &src, MoveNode &dst)
virtual int latestCycle(MoveNode &node, const TTAMachine::Bus *bus=NULL, const TTAMachine::FunctionUnit *srcFU=NULL, const TTAMachine::FunctionUnit *dstFU=NULL, int immWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1) const override
std::map< const MoveNode *, DataDependenceGraph::NodeSet > scheduledTempMoves_
Stores the MoveNodes that were scheduled as temp moves during scheduling of the operand move.
bool isOperationMove() const
void scheduleOperation(MoveNodeGroup &moves, BUMoveNodeSelector &selector)
virtual bool equals(const Terminal &other) const =0
Terminal & source() const
@ ANN_CONNECTIVITY_MOVE
A reg to reg move that was added because of missing connectivity between the original target and dest...
virtual const TTAMachine::Port & port() const
virtual HWOperation * operation(const std::string &name) const
void removeOutgoingGuardWarEdges(MoveNode &node)
std::map< MoveNode *, std::vector< int >, MoveNode::Comparator > bypassDestinationsCycle_
static TTAProgram::MoveGuard * createInverseGuard(const TTAProgram::MoveGuard &mg, const TTAMachine::Bus *bus=NULL)
virtual int bypassDistance() const
virtual bool isRA() const
virtual const TCEString & name() const
MoveNode * precedingTempMove(MoveNode ¤t)
int scheduleResultReads(MoveNodeGroup &moves, int cycle, bool bypass=false, bool bypassLate=false)
EdgeSet copyDepsOver(MoveNode &node, bool anti, bool raw)
MoveNode & outputMove(int index) const
void setBus(const TTAMachine::Bus &bus)
virtual int affectsCount() const
std::set< const TTAMachine::Port *, const TTAMachine::MachinePart::Comparator > PortSet
EdgeReason edgeReason() const
void notifyScheduled(MoveNodeGroup &moves, MoveNodeSelector &selector)
void setSource(Terminal *src)
MoveNode & inputMove(int index) const
boost::timer schedulingTime_
Time for getting the scheduling time for current basic block.
int latestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegAntideps=false, bool ignoreUnscheduledSuccessors=true, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false) const
AddedRegisterCopies addMinimumRegisterCopies(ProgramOperation &programOperation, const TTAMachine::Machine &targetMachine, DataDependenceGraph *ddg)