OpenASIP  2.0
Public Types | Public Member Functions | Static Public Member Functions | Private Types | Private Attributes | Static Private Attributes | List of all members
ProGe::Netlist Class Reference

#include <Netlist.hh>

Inheritance diagram for ProGe::Netlist:
Inheritance graph
Collaboration diagram for ProGe::Netlist:
Collaboration graph

Public Types

typedef boost::graph_traits< Netlist >::edge_iterator iterator
 
typedef boost::graph_traits< const Netlist >::edge_iterator const_iterator
 
typedef DescriptorMap::iterator descriptor_iterator
 
typedef DescriptorMap::const_iterator const_descriptor_iterator
 

Public Member Functions

 Netlist ()
 
virtual ~Netlist ()
 
bool connect (const NetlistPort &port1, const NetlistPort &port2, int port1FirstBit, int port2FirstBit, int width=1)
 
bool connect (const NetlistPort &port1, const NetlistPort &port2)
 
bool connect (const NetlistPortGroup &group1, const NetlistPortGroup &group2)
 
bool connectBy (SignalType byType, const NetlistPortGroup &group1, const NetlistPortGroup &group2)
 
bool connect (const NetlistPortGroup &group1, const NetlistPortGroup &group2, std::map< SignalType, SignalType > connectionMap)
 
bool connectGroupByName (const NetlistPortGroup &group1, const NetlistPortGroup &group2)
 
void disconnectPorts (const NetlistPort &port1, const NetlistPort &port2)
 
bool isPortConnected (const NetlistPort &port) const
 
bool isEmpty () const
 
bool hasConnections () const
 
size_t registerPort (NetlistPort &port)
 
size_t descriptor (const NetlistPort &port) const
 
bool isRegistered (const NetlistPort &port) const
 
void unregisterPort (NetlistPort &port)
 
void setParameter (const std::string &name, const std::string &type, const std::string &value)
 
void setParameter (const Parameter &param)
 
void removeParameter (const std::string &name)
 
bool hasParameter (const std::string &name) const
 
size_t parameterCount () const
 
Parameter parameter (size_t index) const
 
iterator begin ()
 
iterator end ()
 
const_iterator begin () const
 
const_iterator end () const
 
descriptor_iterator descriptorBegin ()
 
descriptor_iterator descriptorEnd ()
 
const_descriptor_iterator descriptorBegin () const
 
const_descriptor_iterator descriptorEnd () const
 

Static Public Member Functions

static void connectClocks (NetlistBlock &block)
 
static void connectResets (NetlistBlock &block)
 

Private Types

typedef std::map< const NetlistPort *, size_t > DescriptorMap
 Map type for vertex descriptors. More...
 
typedef std::vector< ParameterParameterTable
 Vector type for parameters. More...
 

Private Attributes

DescriptorMap vertexDescriptorMap_
 Vertex descriptor map. More...
 
ParameterTable parameters_
 Parameters of the netlist. More...
 
TCEString coreEntityName_
 This should be set to the entity name of the generate core, if it's not the same as the toplevel module name. More...
 

Static Private Attributes

static const std::string INVERTER_MODULE
 
static const std::string INVERTER_INPUT
 
static const std::string INVERTER_OUTPUT
 

Detailed Description

Represents a netlist of port connections.

Definition at line 63 of file Netlist.hh.

Member Typedef Documentation

◆ const_descriptor_iterator

typedef DescriptorMap::const_iterator ProGe::Netlist::const_descriptor_iterator

Definition at line 133 of file Netlist.hh.

◆ const_iterator

typedef boost::graph_traits<const Netlist>::edge_iterator ProGe::Netlist::const_iterator

Definition at line 126 of file Netlist.hh.

◆ descriptor_iterator

typedef DescriptorMap::iterator ProGe::Netlist::descriptor_iterator

Definition at line 132 of file Netlist.hh.

◆ DescriptorMap

typedef std::map<const NetlistPort*, size_t> ProGe::Netlist::DescriptorMap
private

Map type for vertex descriptors.

Definition at line 68 of file Netlist.hh.

◆ iterator

typedef boost::graph_traits<Netlist>::edge_iterator ProGe::Netlist::iterator

Definition at line 125 of file Netlist.hh.

◆ ParameterTable

typedef std::vector<Parameter> ProGe::Netlist::ParameterTable
private

Vector type for parameters.

Definition at line 143 of file Netlist.hh.

Constructor & Destructor Documentation

◆ Netlist()

ProGe::Netlist::Netlist ( )

The constructor.

Definition at line 56 of file Netlist.cc.

56  : coreEntityName_("") {
57 }

◆ ~Netlist()

ProGe::Netlist::~Netlist ( )
virtual

The destructor.

Definition at line 63 of file Netlist.cc.

63  {
64 }

Member Function Documentation

◆ begin() [1/2]

Netlist::const_iterator ProGe::Netlist::begin ( )

Definition at line 443 of file Netlist.cc.

443  {
444  return boost::edges(*this).first;
445 }

Referenced by ProGe::NetlistVisualization::listConnections().

◆ begin() [2/2]

const_iterator ProGe::Netlist::begin ( ) const

◆ connect() [1/4]

bool ProGe::Netlist::connect ( const NetlistPort port1,
const NetlistPort port2 
)

Connects two netlist ports completely.

Each bit of the first port is connected to a bit of the second port. The bits are connected in the same order (the first bit of the first port is connected to the first bit of the second port).

Parameters
port1The first port to connect.
port2The second port to connect.
Returntrue, if connection was successful.

Definition at line 117 of file Netlist.cc.

117  {
118  size_t port1Descriptor = descriptor(port1);
119  size_t port2Descriptor = descriptor(port2);
120  bool needsInversion = port1.assignedSignal().activeState() !=
121  port2.assignedSignal().activeState();
122  PortConnectionProperty property(needsInversion);
123 
124  // create first edge
125  boost::add_edge(port1Descriptor, port2Descriptor, property, *this);
126  // create the opposite edge
127  boost::add_edge(port2Descriptor, port1Descriptor, property, *this);
128  return true;
129 }

References ProGe::Signal::activeState(), ProGe::NetlistPort::assignedSignal(), and descriptor().

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◆ connect() [2/4]

bool ProGe::Netlist::connect ( const NetlistPort port1,
const NetlistPort port2,
int  port1FirstBit,
int  port2FirstBit,
int  width = 1 
)

Partially connects two netlist ports.

Connects two given subsets of bits of two netlist ports. The bit subsets have equal cardinality and represent an ordered range of adjacent bits. The bits are connected in the same order (the first bit of the subset of the first port is connected to the first bit of the subset of the second port).

Parameters
port1The first port to connect.
port2The second port to connect.
port1FirstBitThe first bit of the first port to connect.
port2FirstBitThe first bit of the second port to connect.
widthThe width of the connection.
Returntrue, if connection was successful.

Definition at line 83 of file Netlist.cc.

85  {
86  // PortConnectionProperty regards width 0 as fully connected
87  if (width == 0 && (port1.dataType() != port2.dataType())) {
88  // BIT to/from BIT_VECTOR connection needs partial connectivity
89  width = 1;
90  }
91 
92  size_t port1Descriptor = descriptor(port1);
93  size_t port2Descriptor = descriptor(port2);
94 
95  // create first edge
96  PortConnectionProperty property1(port1FirstBit, port2FirstBit, width);
97  boost::add_edge(port1Descriptor, port2Descriptor, property1, *this);
98 
99  // create the opposite edge
100  PortConnectionProperty property2(port2FirstBit, port1FirstBit, width);
101  boost::add_edge(port2Descriptor, port1Descriptor, property2, *this);
102  return true;
103 }

References ProGe::NetlistPort::dataType(), and descriptor().

Referenced by ProGe::NetlistGenerator::addBaseRFToNetlist(), ProGe::NetlistGenerator::addFUExternalPortsToNetlist(), ProGe::NetlistGenerator::addFUToNetlist(), ProGe::NetlistGenerator::addGCUToNetlist(), ProGe::NetlistGenerator::addGeneratableFUsToNetlist(), DefaultDecoderGenerator::addGlockPortToDecoder(), DefaultICGenerator::addICToNetlist(), ProGe::ProcessorWrapperBlock::addInstructionMemory(), DefaultDecoderGenerator::addLockReqPortToDecoder(), XilinxBlockRamGenerator::addMemory(), DefaultICDecoderGenerator::addRV32MicroCode(), DefaultDecoderGenerator::completeDecoderBlock(), connect(), connectBy(), connectClocks(), ProGe::BaseNetlistBlock::connectClocks(), connectGroupByName(), AlteraHibiDpRamGenerator::connectPorts(), MemoryGenerator::connectPorts(), connectResets(), ProGe::BaseNetlistBlock::connectResets(), PlatformIntegrator::connectToplevelPort(), DefaultICDecoderGenerator::generateDebuggerCode(), AlmaIFIntegrator::initAlmaifBlock(), AlmaIFIntegrator::integrateCore(), and PlatformIntegrator::integrateCore().

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◆ connect() [3/4]

bool ProGe::Netlist::connect ( const NetlistPortGroup group1,
const NetlistPortGroup group2 
)

Trivially connect ports of the groups together by their signal types.

Parameters
Returntrue, if connection was successful.

Definition at line 149 of file Netlist.cc.

150  {
151  if (group1.portCount() != group2.portCount()) {
152  return false;
153  }
154 
155  std::map<SignalType, const NetlistPort*> portsOfGroup2;
156  for (const NetlistPort* port : group2) {
157  assert(
159  portsOfGroup2, port->assignedSignal().type()) &&
160  "Netlist::Connect(): Currently cannot handle groups with "
161  "multiply of same signal type");
162  portsOfGroup2.insert(
163  std::make_pair(port->assignedSignal().type(), port));
164  }
165 
166  for (const NetlistPort* from : group1) {
167  SignalType matchingType = from->assignedSignal().type();
168  assert(AssocTools::containsKey(portsOfGroup2, matchingType) && "");
169  const NetlistPort* to = portsOfGroup2.at(matchingType);
170  connect(*from, *to);
171  }
172 
173  return true;
174 }

References assert, connect(), AssocTools::containsKey(), and ProGe::NetlistPortGroup::portCount().

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◆ connect() [4/4]

bool ProGe::Netlist::connect ( const NetlistPortGroup group1,
const NetlistPortGroup group2,
std::map< SignalType, SignalType connectionMap 
)

Makes connection between two different netlist port group by connection map using their SignalTypes.

The connections are made from the first group to the second group by using the connection map. todo...

Parameters
group1The first port group.
group2The second port group.
connectionMapThe connection rules.

Definition at line 209 of file Netlist.cc.

211  {
212  for (const NetlistPort* port1 : group1) {
213  SignalType type1 = port1->assignedSignal().type();
215  if (connectionMap.count(type1)) {
216  type2 = connectionMap.at(type1);
217  } else {
218  continue;
219  }
220  if (type2 == SignalType::OPEN) {
221  continue;
222  }
223  const NetlistPort& port2 = group2.portBySignal(type2);
224 
225  connect(*port1, port2);
226  }
227 
228  return true;
229 }

References connect(), ProGe::OPEN, ProGe::NetlistPortGroup::portBySignal(), and ProGe::UNDEFINED.

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◆ connectBy()

bool ProGe::Netlist::connectBy ( SignalType  byType,
const NetlistPortGroup group1,
const NetlistPortGroup group2 
)

Make single port connection by given signal type.

Signal type is assumed to be unique within the both port groups.

Definition at line 182 of file Netlist.cc.

184  {
185  assert(group1.hasPortBySignal(byType));
186  assert(group2.hasPortBySignal(byType));
187 
188  const NetlistPort& port1 = group1.portBySignal(byType);
189  const NetlistPort& port2 = group2.portBySignal(byType);
190 
191  connect(port1, port2);
192 
193  return true;
194 }

References assert, connect(), ProGe::NetlistPortGroup::hasPortBySignal(), and ProGe::NetlistPortGroup::portBySignal().

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◆ connectClocks()

void ProGe::Netlist::connectClocks ( NetlistBlock block)
static

Definition at line 483 of file Netlist.cc.

483  {
484  const NetlistPort* topClock = nullptr;
485  {
486  std::vector<const NetlistPort*> clockOfBlock;
487  clockOfBlock = block.portsBy(SignalType::CLOCK);
488  assert(clockOfBlock.size() < 2);
489  if (clockOfBlock.empty()) {
490  return;
491  } else {
492  topClock = clockOfBlock.at(0);
493  }
494  }
495 
496  for (size_t i = 0; i < block.subBlockCount(); i++) {
497  std::vector<const NetlistPort*> clockOfSubBlock;
498  const BaseNetlistBlock& cblock = block;
499  clockOfSubBlock = cblock.subBlock(i).portsBy(SignalType::CLOCK);
500  assert(clockOfSubBlock.size() < 2);
501  if (clockOfSubBlock.empty() ||
502  block.netlist().isPortConnected(*clockOfSubBlock.at(0))) {
503  continue;
504  } else {
505  block.netlist().connect(*topClock, *clockOfSubBlock.at(0));
506  }
507  }
508 }

References assert, ProGe::CLOCK, connect(), isPortConnected(), ProGe::NetlistBlock::netlist(), ProGe::BaseNetlistBlock::portsBy(), ProGe::BaseNetlistBlock::subBlock(), and ProGe::NetlistBlock::subBlockCount().

Referenced by ProGe::NetlistGenerator::addGCUToNetlist().

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◆ connectGroupByName()

bool ProGe::Netlist::connectGroupByName ( const NetlistPortGroup group1,
const NetlistPortGroup group2 
)

Trivially connect ports of the groups together by their port names. Useful for exporting e.g. bus connections to higher-level netlist block

Parameters
Returntrue, if connection was successful.

Definition at line 238 of file Netlist.cc.

239  {
240  if (group1.portCount() != group2.portCount()) {
241  return false;
242  }
243 
244  std::map<std::string, const NetlistPort*> portsOfGroup2;
245  for (const NetlistPort* port : group2) {
246  assert(
247  !AssocTools::containsKey(portsOfGroup2, port->name()) &&
248  "Netlist::Connect(): group2 has multiple ports "
249  "with the same name");
250  portsOfGroup2.insert(std::make_pair(port->name(), port));
251  }
252 
253  for (const NetlistPort* from : group1) {
254  std::string matchingName = from->name();
255  assert(
256  AssocTools::containsKey(portsOfGroup2, matchingName) &&
257  "Netlist::connectByName: The two port groups' names "
258  "do not match");
259  const NetlistPort* to = portsOfGroup2.at(matchingName);
260  connect(*from, *to);
261  }
262 
263  return true;
264 }

References assert, connect(), AssocTools::containsKey(), and ProGe::NetlistPortGroup::portCount().

Referenced by AlmaIFIntegrator::initAlmaifBlock().

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◆ connectResets()

void ProGe::Netlist::connectResets ( NetlistBlock block)
static

Definition at line 511 of file Netlist.cc.

511  {
512  const NetlistPort* topClock = nullptr;
513  {
514  std::vector<const NetlistPort*> clockOfBlock;
515  clockOfBlock = block.portsBy(SignalType::RESET);
516  assert(clockOfBlock.size() < 2);
517  if (clockOfBlock.empty()) {
518  return;
519  } else {
520  topClock = clockOfBlock.at(0);
521  }
522  }
523 
524  for (size_t i = 0; i < block.subBlockCount(); i++) {
525  std::vector<const NetlistPort*> clockOfSubBlock;
526  const BaseNetlistBlock& cblock = block;
527  clockOfSubBlock = cblock.subBlock(i).portsBy(SignalType::RESET);
528  assert(clockOfSubBlock.size() < 2);
529  if (clockOfSubBlock.empty() ||
530  block.netlist().isPortConnected(*clockOfSubBlock.at(0))) {
531  continue;
532  } else {
533  block.netlist().connect(*topClock, *clockOfSubBlock.at(0));
534  }
535  }
536 }

References assert, connect(), isPortConnected(), ProGe::NetlistBlock::netlist(), ProGe::BaseNetlistBlock::portsBy(), ProGe::RESET, ProGe::BaseNetlistBlock::subBlock(), and ProGe::NetlistBlock::subBlockCount().

Referenced by ProGe::NetlistGenerator::addGCUToNetlist().

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◆ descriptor()

size_t ProGe::Netlist::descriptor ( const NetlistPort port) const

◆ descriptorBegin() [1/2]

Netlist::const_descriptor_iterator ProGe::Netlist::descriptorBegin ( )

Definition at line 463 of file Netlist.cc.

463  {
464  return vertexDescriptorMap_.begin();
465 }

References vertexDescriptorMap_.

Referenced by ProGe::NetlistVisualization::listNetlistDescriptors().

◆ descriptorBegin() [2/2]

const_descriptor_iterator ProGe::Netlist::descriptorBegin ( ) const

◆ descriptorEnd() [1/2]

Netlist::const_descriptor_iterator ProGe::Netlist::descriptorEnd ( )

Definition at line 468 of file Netlist.cc.

468  {
469  return vertexDescriptorMap_.end();
470 }

References vertexDescriptorMap_.

Referenced by ProGe::NetlistVisualization::listNetlistDescriptors().

◆ descriptorEnd() [2/2]

const_descriptor_iterator ProGe::Netlist::descriptorEnd ( ) const

◆ disconnectPorts()

void ProGe::Netlist::disconnectPorts ( const NetlistPort port1,
const NetlistPort port2 
)

Removes connection between two ports.

Definition at line 135 of file Netlist.cc.

135  {
136  size_t port1Descriptor = descriptor(port1);
137  size_t port2Descriptor = descriptor(port2);
138 
139  boost::remove_edge(port1Descriptor, port2Descriptor, *this);
140  boost::remove_edge(port2Descriptor, port1Descriptor, *this);
141 }

References descriptor().

Referenced by DefaultICDecoderGenerator::addRV32MicroCode().

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◆ end() [1/2]

Netlist::const_iterator ProGe::Netlist::end ( )

Definition at line 448 of file Netlist.cc.

448  {
449  return boost::edges(*this).second;
450 }

Referenced by ProGe::NetlistVisualization::listConnections().

◆ end() [2/2]

const_iterator ProGe::Netlist::end ( ) const

◆ hasConnections()

bool ProGe::Netlist::hasConnections ( ) const

Returns true if there are some connections between ports.

Definition at line 296 of file Netlist.cc.

296  {
297  return boost::num_edges(*this) != 0;
298 }

◆ hasParameter()

bool ProGe::Netlist::hasParameter ( const std::string &  name) const

Tells whether the netlist has the given parameter.

Parameters
nameName of the parameter.

Definition at line 403 of file Netlist.cc.

403  {
404 
405  for (ParameterTable::const_iterator iter = parameters_.begin();
406  iter != parameters_.end(); iter++) {
407  if (iter->name() == name) {
408  return true;
409  }
410  }
411 
412  return false;
413 }

References parameters_.

Referenced by ProGe::NetlistGenerator::addBaseRFToNetlist(), ProGe::NetlistGenerator::addFUExternalPortsToNetlist(), and setParameter().

◆ isEmpty()

bool ProGe::Netlist::isEmpty ( ) const

Tells whether the netlist is empty.

Returns
True if the netlist is empty, otherwise false.

Definition at line 288 of file Netlist.cc.

288  {
289  return boost::num_vertices(*this) == 0;
290 }

Referenced by ProGe::VerilogNetlistWriter::write().

◆ isPortConnected()

bool ProGe::Netlist::isPortConnected ( const NetlistPort port) const

Tells whether the netlist port is connected in this netlist instance

Parameters
portThe netlist port
Returns
True if port is connected

Definition at line 273 of file Netlist.cc.

273  {
274 
275  size_t vertDesc = descriptor(port);
276  boost::graph_traits<Netlist>::degree_size_type edges =
277  boost::out_degree(vertDesc, *this);
278  return edges != 0;
279 }

References descriptor().

Referenced by connectClocks(), and connectResets().

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◆ isRegistered()

bool ProGe::Netlist::isRegistered ( const NetlistPort port) const

Returns true if the netlist has the given port.

Definition at line 334 of file Netlist.cc.

334  {
336 }

References MapTools::containsKey(), and vertexDescriptorMap_.

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◆ parameter()

Parameter ProGe::Netlist::parameter ( size_t  index) const

Returns the parameter at the given position.

Parameters
indexThe position.
Exceptions
OutOfRangeIf the given index is negative or not smaller than the number of parameters.

Definition at line 434 of file Netlist.cc.

434  {
435  if (index >= parameterCount()) {
436  throw OutOfRange(__FILE__, __LINE__, __func__);
437  }
438 
439  return parameters_[index];
440 }

References __func__, parameterCount(), and parameters_.

Referenced by PlatformIntegrator::copyProgeBlockToNetlist(), ProGe::NetlistPort::resolveRealWidth(), ProGe::NetlistBlock::shallowCopy(), ProGe::BaseNetlistBlock::shallowCopy(), ProGe::VerilogNetlistWriter::writeNetlistParameterPackage(), and ProGe::VHDLNetlistWriter::writeNetlistParameterPackage().

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◆ parameterCount()

size_t ProGe::Netlist::parameterCount ( ) const

◆ registerPort()

size_t ProGe::Netlist::registerPort ( NetlistPort port)

Registers given port to the netlist to make connection possible.

This method does not need to be called by clients.

Parameters
portThe port.
Returns
Descriptor to the port.

Definition at line 309 of file Netlist.cc.

309  {
310  assert(
312  "The port is already registered");
313  size_t descriptor = boost::add_vertex(&port, *this);
314  vertexDescriptorMap_.insert(
315  std::pair<const NetlistPort*, size_t>(&port, descriptor));
316  return descriptor;
317 }

References assert, MapTools::containsKey(), descriptor(), and vertexDescriptorMap_.

Referenced by ProGe::BaseNetlistBlock::addPort(), and ProGe::BaseNetlistBlock::addSubBlock().

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◆ removeParameter()

void ProGe::Netlist::removeParameter ( const std::string &  name)

Removes the given parameter from the netlist.

Parameters
nameName of the parameter.

Definition at line 386 of file Netlist.cc.

386  {
387  for (ParameterTable::iterator iter = parameters_.begin();
388  iter != parameters_.end(); iter++) {
389  if (iter->name() == name) {
390  parameters_.erase(iter);
391  break;
392  }
393  }
394 }

References parameters_.

Referenced by setParameter().

◆ setParameter() [1/2]

void ProGe::Netlist::setParameter ( const Parameter param)

Definition at line 376 of file Netlist.cc.

376  {
377  setParameter(param.name(), param.type(), param.value());
378 }

References ProGe::Parameter::name(), setParameter(), ProGe::Parameter::type(), and ProGe::Parameter::value().

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◆ setParameter() [2/2]

void ProGe::Netlist::setParameter ( const std::string &  name,
const std::string &  type,
const std::string &  value 
)

[DEPRECATED] Adds a parameter for the netlist.

If the netlist already has a parameter with the given name, it is replaced by the new parameter.

Parameters
nameName of the parameter.
typeType of the parameter.
valueValue of the parameter.

Definition at line 362 of file Netlist.cc.

365  {
366 
367  if (hasParameter(name)) {
368  removeParameter(name);
369  }
370 
371  Parameter param = {name, type, value};
372  parameters_.push_back(param);
373 }

References hasParameter(), parameters_, and removeParameter().

Referenced by ProGe::NetlistGenerator::addBaseRFToNetlist(), ProGe::NetlistGenerator::addFUExternalPortsToNetlist(), PlatformIntegrator::copyProgeBlockToNetlist(), setParameter(), ProGe::NetlistBlock::shallowCopy(), and ProGe::BaseNetlistBlock::shallowCopy().

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◆ unregisterPort()

void ProGe::Netlist::unregisterPort ( NetlistPort port)

Removes port from the netlist and all connections related to it.

Definition at line 342 of file Netlist.cc.

342  {
344  boost::clear_vertex(this->descriptor(port), *this);
345  boost::remove_vertex(this->descriptor(port), *this);
346  vertexDescriptorMap_.erase(&port);
347  }
348 }

References MapTools::containsKey(), descriptor(), and vertexDescriptorMap_.

Referenced by ProGe::BaseNetlistBlock::removePort().

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Member Data Documentation

◆ coreEntityName_

TCEString ProGe::Netlist::coreEntityName_
private

This should be set to the entity name of the generate core, if it's not the same as the toplevel module name.

Definition at line 152 of file Netlist.hh.

◆ INVERTER_INPUT

const std::string ProGe::Netlist::INVERTER_INPUT
staticprivate

Definition at line 155 of file Netlist.hh.

◆ INVERTER_MODULE

const std::string ProGe::Netlist::INVERTER_MODULE
staticprivate

Definition at line 154 of file Netlist.hh.

◆ INVERTER_OUTPUT

const std::string ProGe::Netlist::INVERTER_OUTPUT
staticprivate

Definition at line 156 of file Netlist.hh.

◆ parameters_

ParameterTable ProGe::Netlist::parameters_
private

Parameters of the netlist.

Definition at line 148 of file Netlist.hh.

Referenced by hasParameter(), parameter(), parameterCount(), removeParameter(), and setParameter().

◆ vertexDescriptorMap_

DescriptorMap ProGe::Netlist::vertexDescriptorMap_
private

Vertex descriptor map.

Definition at line 146 of file Netlist.hh.

Referenced by descriptor(), descriptorBegin(), descriptorEnd(), isRegistered(), registerPort(), and unregisterPort().


The documentation for this class was generated from the following files:
ProGe::Netlist::removeParameter
void removeParameter(const std::string &name)
Definition: Netlist.cc:386
ProGe::Netlist::parameters_
ParameterTable parameters_
Parameters of the netlist.
Definition: Netlist.hh:148
AssocTools::containsKey
static bool containsKey(const ContainerType &aContainer, const KeyType &aKey)
OutOfRange
Definition: Exception.hh:320
ProGe::SignalType::RESET
@ RESET
Reset signal.
ProGe::SignalType::UNDEFINED
@ UNDEFINED
Signal does not have specified usage.
ProGe::Netlist::connect
bool connect(const NetlistPort &port1, const NetlistPort &port2, int port1FirstBit, int port2FirstBit, int width=1)
Definition: Netlist.cc:83
assert
#define assert(condition)
Definition: Application.hh:86
ProGe::Netlist::parameterCount
size_t parameterCount() const
Definition: Netlist.cc:422
ProGe::Netlist::hasParameter
bool hasParameter(const std::string &name) const
Definition: Netlist.cc:403
__func__
#define __func__
Definition: Application.hh:67
ProGe::Netlist::descriptor
size_t descriptor(const NetlistPort &port) const
Definition: Netlist.cc:325
ProGe::SignalType::OPEN
@ OPEN
Signal is left to unconnected.
ProGe::SignalType::CLOCK
@ CLOCK
Clock signal.
ProGe::SignalType
SignalType
Definition: SignalTypes.hh:42
MapTools::containsKey
static bool containsKey(const MapType &aMap, const KeyType &aKey)
ProGe::Netlist::setParameter
void setParameter(const std::string &name, const std::string &type, const std::string &value)
Definition: Netlist.cc:362
ProGe::Netlist::vertexDescriptorMap_
DescriptorMap vertexDescriptorMap_
Vertex descriptor map.
Definition: Netlist.hh:146
ProGe::Netlist::coreEntityName_
TCEString coreEntityName_
This should be set to the entity name of the generate core, if it's not the same as the toplevel modu...
Definition: Netlist.hh:152