OpenASIP 2.2
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BFDRELoop.cc
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1/*
2 Copyright (c) 2002-2014 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24
25/**
26 * @file BFDRELoop.cc
27 *
28 * Definition of BFDRELoop class
29 *
30 * Performs a dead-result elimination of a loop-bypassed move.
31 * The move which is eliminated from the loop body is still left
32 * in the epilog, to have correct value for the register after
33 * the loop.
34 *
35 * @author Heikki Kultala 2014-2020(heikki.kultala-no.spam-tuni.fi)
36 * @note rating: red
37 */
38
39#include "BFDRELoop.hh"
41#include "BF2Scheduler.hh"
42#include "MoveNodeDuplicator.hh"
44#include "Machine.hh"
45
47 if (!sched_.killDeadResults() || targetMachine().alwaysWriteResults()) {
48 return false;
49 }
50
51 if (srcCycle_ < ii()) {
52#ifdef DEBUG_BUBBLEFISH_SCHEDULER
53 std::cerr << "\t\t\t\tCannot loop-dre due too early result cycle"
54 << std::endl;
55#endif
56 return false;
57 }
58
59 if (!dreAllowed()) {
60 return false;
61 }
62
63 // Create a copy to prolog.
64 auto a = duplicator().duplicateMoveNode(mn_, true, true);
65 prologMN_ = a.first;
66 createdPrologCopy_ = a.second;
67
69 if (prologRM()->canAssign(prologCycle, *prologMN_)) {
70 prologRM()->assign(prologCycle, *prologMN_);
71#ifdef DEBUG_BUBBLEFISH_SCHEDULER
72 std::cerr << "\t\t\t\tAssigned loop-bypassed dead result to"
73 << " epilog, cycle:" << prologCycle << std::endl;
74#endif
75 // TODO: where to add to the epilog DDG?
76 createdEdges_ = ddg().copyDepsOver(mn_, true, false);
77 ddg().dropNode(mn_);
79 return true;
80 } else {
81#ifdef DEBUG_BUBBLEFISH_SCHEDULER
82 std::cerr << "\t\t\t\tProlog cycle assign fail for loop-dre: "
84 << " prolog cycle: " << prologCycle << std::endl;
85#endif
88 }
89 return false;
90 }
91}
92
94 assert(prologRM()!=NULL);
95 assert(&mn_ != NULL);
98 prologMoves_.erase(&mn_);
101 }
102
103
105}
106
109 for (auto edge: edges) {
110 if (edge->edgeReason() == DataDependenceEdge::EDGE_OPERATION) {
111 return false;
112 }
113 if ((edge->edgeReason() == DataDependenceEdge::EDGE_REGISTER ||
114 edge->edgeReason() ==DataDependenceEdge::EDGE_RA) &&
115 edge->dependenceType() == DataDependenceEdge::DEP_RAW) {
116 return false;
117 }
118 }
119 return true;
120}
#define assert(condition)
bool killDeadResults() const
void nodeKilled(MoveNode &mn)
static const int PROLOG_CYCLE_BIAS
void undoOnlyMe()
Definition BFDRELoop.cc:93
bool dreAllowed()
Definition BFDRELoop.cc:107
unsigned int srcCycle_
Definition BFDRELoop.hh:55
bool createdPrologCopy_
Definition BFDRELoop.hh:57
bool operator()()
Definition BFDRELoop.cc:46
MoveNode * prologMN_
Definition BFDRELoop.hh:56
DataDependenceGraph::EdgeSet createdEdges_
Definition BFKillNode.hh:51
MoveNode & mn_
Definition BFKillNode.hh:52
void undoOnlyMe()
Definition BFKillNode.cc:49
unsigned int ii() const
BF2Scheduler & sched_
virtual bool canAssign(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGWN=false)
SimpleResourceManager * prologRM() const
DataDependenceGraph & ddg()
const TTAMachine::Machine & targetMachine() const
MoveNodeDuplicator & duplicator() const
static std::map< MoveNode *, MoveNode *, MoveNode::Comparator > prologMoves_
virtual void dropNode(Node &node)
virtual EdgeSet outEdges(const Node &node) const
EdgeSet copyDepsOver(MoveNode &node, bool anti, bool raw)
std::set< GraphEdge *, typename GraphEdge::Comparator > EdgeSet
Definition Graph.hh:54
void disposeMoveNode(MoveNode *newMN)
std::pair< MoveNode *, bool > duplicateMoveNode(MoveNode &mn, bool addToDDG, bool ignoreSameBBBackEdges)
std::string toString() const
Definition MoveNode.cc:576
bool isScheduled() const
Definition MoveNode.cc:409
virtual void assign(int cycle, MoveNode &node, const TTAMachine::Bus *bus=NULL, const TTAMachine::FunctionUnit *srcFU=NULL, const TTAMachine::FunctionUnit *dstFU=NULL, int immWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1) override
virtual void unassign(MoveNode &node) override