OpenASIP 2.2
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BFOptimization.hh
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1/*
2 Copyright (c) 2002-2014 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24
25/**
26 * @file BFOptimization.hh
27 *
28 * Declaration of BFOptimization class.
29 *
30 * Base class for all optimizations and scheudling operations the
31 * BF2 instruction scheduler can perform. Contains an undo-mechanism
32 * To undo everything, and contains handling for scheudling mirror move
33 * to prolog/epilog in case of loop scheduling.
34 *
35 * @author Heikki Kultala 2014-2020(heikki.kultala-no.spam-tuni.fi)
36 * @note rating: red
37 */
38
39#ifndef BFOPTIMIZATION_HH
40#define BFOPTIMIZATION_HH
41
44class BF2Scheduler;
46class MoveNode;
47class Operation;
48
49#include <cassert>
50#include <map>
51#include "MoveNode.hh"
52#include "Reversible.hh"
53#include "TCEString.hh"
54
55namespace TTAMachine {
56 class Machine;
57 class FunctionUnit;
58 class Bus;
59 class ImmediateUnit;
60 class RegisterFile;
61}
62
63namespace TTAProgram {
64 class Terminal;
65}
66
68
69// debugging defines.
70//#define CHECK_DDG_EQUALITY 1
71//#define DEBUG_BUBBLEFISH_SCHEDULER
72
73class BFOptimization : public Reversible {
74public:
76#ifdef CHECK_DDG_EQUALITY
77 getDDGSnapshot();
78#endif
79}
80
81 virtual bool isFinishFront() { return false; }
82 static void clearPrologMoves();
84 const MoveNode& mn, const TTAMachine::Machine& mach);
85 // TODO: this list may contain moves that are demoved. egt rid of them!
86 virtual void mightBeReady(MoveNode& mn);
87
88#ifdef CHECK_DDG_EQUALITY
89 virtual void undo() override;
90#endif
91
92protected:
95 const DataDependenceGraph& ddg() const;
100 const TTAMachine::Machine& targetMachine() const;
101 unsigned int ii() const;
104
105 // wrappers over RM for loop scheduling
106 virtual bool assign(int cycle, MoveNode&,
107 const TTAMachine::Bus* bus = nullptr,
108 const TTAMachine::FunctionUnit* srcFU_ = nullptr,
109 const TTAMachine::FunctionUnit* dstFU = nullptr,
110 const TTAMachine::Bus* prologBus = nullptr,
111 int immWriteCycle = -1,
112 int prologImmWriteCycle = -1,
113 const TTAMachine::ImmediateUnit* immu = nullptr,
114 int immRegIndex = -1,
115 bool ignoreGuardWriteCycle = false);
116 virtual void unassign(MoveNode& mn,
117 bool disposePrologCopy = true);
118 virtual int rmEC(int cycle, MoveNode& mn,
119 const TTAMachine::Bus* bus = nullptr,
120 const TTAMachine::FunctionUnit* srcFU = nullptr,
121 const TTAMachine::FunctionUnit* dstFU = nullptr,
122 const TTAMachine::Bus* prologBus = nullptr,
123 int immWriteCycle = -1,
124 int prologImmWriteCycle = -1,
125 const TTAMachine::ImmediateUnit* immu = nullptr,
126 int immRegIndex = -1);
127 virtual int rmLC(int cycle, MoveNode& mn,
128 const TTAMachine::Bus* bus = nullptr,
129 const TTAMachine::FunctionUnit* srcFU = nullptr,
130 const TTAMachine::FunctionUnit* dstFU = nullptr,
131 const TTAMachine::Bus* prologBus = nullptr,
132 int immWriteCycle = -1,
133 int prologImmWriteCycle = -1,
134 const TTAMachine::ImmediateUnit* immu = nullptr,
135 int immRegIndex = -1);
136 virtual bool canAssign(int cycle, MoveNode& mn,
137 const TTAMachine::Bus* bus = nullptr,
138 const TTAMachine::FunctionUnit* srcFU = nullptr,
139 const TTAMachine::FunctionUnit* dstFU = nullptr,
140 const TTAMachine::Bus* prologBus = nullptr,
141 int immWriteCycle = -1,
142 int prologImmWriteCycle = -1,
143 const TTAMachine::ImmediateUnit* immu = nullptr,
144 int immRegIndex = -1,
145 bool ignoreGWN = false);
146 static std::map<MoveNode*, MoveNode*, MoveNode::Comparator> prologMoves_;
147
148 bool putAlsoToPrologEpilog(int cycle, MoveNode& mn);
149
150 void setPrologSrcFUAnno(MoveNode& prologMN, MoveNode& loopMN);
151 void setPrologDstFUAnno(MoveNode& prologMN, MoveNode& loopMN);
152 void setJumpGuard(MoveNode& mn);
153 void unsetJumpGuard(MoveNode& mn);
154 bool needJumpGuard(const MoveNode& mn, int cycle);
155 int jumpGuardAvailableCycle(const MoveNode& mn);
156 bool canBeSpeculated(const Operation& op);
157 bool canBeSpeculated(const MoveNode& mn);
158 bool usePrologMove(const MoveNode& mn);
159 bool canBeScheduled(const MoveNode& mn);
160
162 const MoveNode& mn);
163
164 bool immCountPreventsScheduling(const MoveNode& mn);
165
166#ifdef CHECK_DDG_EQUALITY
167
168 void getDDGSnapshot();
169 void checkDDGEquality();
170
171 TCEString ddgString_;
172 TCEString prologDDGString_;
173 int ddgECount_;
174 int prologDDGECount_;
175 int ddgNCount_;
176 int prologDDGNCount_;
177#endif
178
179private:
180 void unsetJumpGuardIfNeeded(MoveNode& mn, int cycle);
182 int cycle, MoveNode& mn, MoveNode& loopMN,
183 const TTAMachine::Bus* prologBus,
184 int prologImmWriteCycle);
186 MoveNode& mh, bool disposePrologCopy = true);
187 std::pair<MoveNode*,bool> createCopyForPrologEpilog(MoveNode& mn);
189 MoveNode& mn, int cycle, bool ignoreGuardWriteCycle = false);
190 void setPrologFUAnnos(MoveNode& prologMN, MoveNode& loopMN);
191 bool hasAmbiguousResources(MoveNode& mn) const;
192
196 const TTAProgram::Terminal& t);
197
198 void checkPrologDDG(MoveNode& prologEpilogMN);
199};
200
201#endif
bool usePrologMove(const MoveNode &mn)
void assignCopyToPrologEpilog(int cycle, MoveNode &mn, MoveNode &loopMN, const TTAMachine::Bus *prologBus, int prologImmWriteCycle)
bool needJumpGuard(const MoveNode &mn, int cycle)
DataDependenceGraph * prologDDG()
virtual void mightBeReady(MoveNode &mn)
const TTAMachine::FunctionUnit * sourceFU(const MoveNode &mn)
bool addJumpGuardIfNeeded(MoveNode &mn, int cycle, bool ignoreGuardWriteCycle=false)
unsigned int ii() const
BF2Scheduler & sched_
const TTAMachine::FunctionUnit * destinationFU(const MoveNode &mn)
virtual bool canAssign(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGWN=false)
void setJumpGuard(MoveNode &mn)
const TTAMachine::FunctionUnit * fuOfTerminal(const TTAProgram::Terminal &t)
void setPrologFUAnnos(MoveNode &prologMN, MoveNode &loopMN)
void unassignCopyFromPrologEpilog(MoveNode &mh, bool disposePrologCopy=true)
void setPrologSrcFUAnno(MoveNode &prologMN, MoveNode &loopMN)
static MoveNode * getSisterTrigger(const MoveNode &mn, const TTAMachine::Machine &mach)
void checkPrologDDG(MoveNode &prologEpilogMN)
SimpleResourceManager * prologRM() const
bool hasAmbiguousResources(MoveNode &mn) const
std::pair< MoveNode *, bool > createCopyForPrologEpilog(MoveNode &mn)
void setPrologDstFUAnno(MoveNode &prologMN, MoveNode &loopMN)
BUMoveNodeSelector & selector()
DataDependenceGraph & ddg()
const TTAMachine::RegisterFile * RFReadPortCountPreventsScheduling(const MoveNode &mn)
virtual void unassign(MoveNode &mn, bool disposePrologCopy=true)
DataDependenceGraph * rootDDG()
bool immCountPreventsScheduling(const MoveNode &mn)
bool putAlsoToPrologEpilog(int cycle, MoveNode &mn)
virtual bool isFinishFront()
int jumpGuardAvailableCycle(const MoveNode &mn)
virtual int rmLC(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1)
const TTAMachine::Machine & targetMachine() const
bool canBeScheduled(const MoveNode &mn)
virtual int rmEC(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1)
static void clearPrologMoves()
MoveNodeDuplicator & duplicator() const
SimpleResourceManager & rm() const
static std::map< MoveNode *, MoveNode *, MoveNode::Comparator > prologMoves_
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
BFOptimization(BF2Scheduler &sched)
void unsetJumpGuard(MoveNode &mn)
bool canBeSpeculated(const Operation &op)
void unsetJumpGuardIfNeeded(MoveNode &mn, int cycle)
virtual void undo()
Definition Reversible.cc:69