OpenASIP 2.2
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NetlistBlock.hh
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1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file NetlistBlock.hh
26 *
27 * Declaration of NetlistBlock class.
28 *
29 * @author Lasse Laasonen 2005 (lasse.laasonen-no.spam-tut.fi)
30 * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
31 * @author Henry Linjamäki 2015 (henry.linjamaki-no.spam-tut.fi)
32 * @note rating: red
33 */
34
35#ifndef TTA_NETLIST_BLOCK_HH
36#define TTA_NETLIST_BLOCK_HH
37
38#include <string>
39#include <vector>
40#include <map>
41
42#include "BaseNetlistBlock.hh"
43#include "SignalTypes.hh"
44
45#include "Exception.hh"
46#include "Netlist.hh"
47
48namespace HDB {
49 class HWBlockImplementationParameter;
50}
51
52namespace ProGe {
53
54class Netlist;
55class NetlistPort;
56class Parameter;
57
58/**
59 * Represents a hardware block in the netlist.
60 */
62public:
64 const std::string& moduleName,
65 const std::string& instanceName,
66 BaseNetlistBlock* parent = NULL);
67 virtual ~NetlistBlock();
68
69 void setParameter(
70 const std::string& name,
71 const std::string& type,
72 const std::string& value);
76
83
84 virtual NetlistPort* port(
85 const std::string& portName,
86 bool partialMatch = true);
87
90 NetlistBlock& subBlock(size_t index) override;
91
92 virtual const NetlistBlock& parentBlock() const override;
93 virtual NetlistBlock& parentBlock() override;
94
96
98 const std::string& instanceName) const;
99
103
104 virtual void write(
105 const Path& targetBaseDir, HDL targetLang = VHDL) const override;
106};
107
108}
109
110#endif
virtual size_t subBlockCount() const
virtual size_t packageCount() const
virtual const Parameter & parameter(const std::string &name) const
void addSubBlock(BaseNetlistBlock *subBlock, const std::string &instanceName="")
NetlistPort * addPort(NetlistPort *port)
virtual const std::string & package(size_t idx) const
void addParameter(const Parameter &param)
virtual const NetlistPort & port(size_t index) const
const std::string & instanceName() const
virtual size_t portCount() const
const std::string & moduleName() const
void addPackage(const std::string &packageName)
const std::string name() const
void addPortGroup(NetlistPortGroup *portGroup)
void setParameter(const Parameter &param)
virtual const Netlist & netlist() const
void removePort(NetlistPort *port)
NetlistBlock * shallowCopy(const std::string &instanceName) const
void setParameter(const std::string &name, const std::string &type, const std::string &value)
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const override
void removePort(NetlistPort &port)
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
NetlistBlock & subBlock(size_t index) override
virtual const NetlistBlock & parentBlock() const override
Definition FUGen.hh:54
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40
@ VHDL
VHDL.
Definition ProGeTypes.hh:41