OpenASIP 2.2
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BaseNetlistBlock.hh
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1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * @file BaseNetlistBlock.hh
26 *
27 * Declaration of BaseNetlistBlock class.
28 *
29 * Created on: 20.4.2015
30 * @author Henry Linjamäki 2015 (henry.linjamaki-no.spam-tut.fi)
31 * @note rating: red
32 */
33
34#ifndef BASENETLISTBLOCK_HH
35#define BASENETLISTBLOCK_HH
36
37#include <vector>
38#include <string>
39
40#include "IGenerationPhases.hh"
41
42#include "Parameter.hh"
43#include "ProGeContext.hh"
44#include "SignalTypes.hh"
45#include "SignalGroupTypes.hh"
46
47namespace ProGe {
48
49class NetlistPort;
50class NetlistPortGroup;
51class Netlist;
52class Parameter;
53class ProGeContext;
54
55/*
56 * Base netlist block class for all netlist blocks and non-modifiable view of
57 * block hierarchy.
58 */
60public:
61 friend class NetlistPort;
62 friend class NetlistPortGroup;
63 friend class Parameter;
64
65 typedef std::vector<BaseNetlistBlock*> BlockContainerType;
66 typedef std::vector<Parameter> ParameterContainerType;
67 typedef std::vector<NetlistPort*> PortContainerType;
68 typedef std::vector<NetlistPortGroup*> PortGroupContainerType;
69
71 explicit BaseNetlistBlock(BaseNetlistBlock* parent);
73 const std::string& moduleName,
74 const std::string& instanceName,
75 BaseNetlistBlock* parent = nullptr);
76 virtual ~BaseNetlistBlock();
77
78 const std::string& instanceName() const;
79 void setInstanceName(const std::string& name);
80 const std::string& moduleName() const;
81 const std::string name() const;
82
83 virtual size_t subBlockCount() const;
84 virtual const BaseNetlistBlock& subBlock(size_t index) const;
85 virtual bool hasSubBlock(const std::string& instanceName) const;
86 virtual bool isSubBlock(const BaseNetlistBlock& block) const;
87
88 virtual bool hasParameter(const std::string& name) const;
89 virtual const Parameter& parameter(const std::string& name) const;
90 virtual size_t parameterCount() const;
91 virtual const Parameter& parameter(size_t index) const;
92
93 virtual size_t portCount() const;
94 virtual const NetlistPort& port(size_t index) const;
95 virtual std::vector<const NetlistPort*> portsBy(SignalType type) const;
96 virtual const NetlistPort& portBy(SignalType type, size_t index = 0) const;
97 virtual bool hasPortsBy(SignalType type) const;
98 virtual const NetlistPort* port(
99 const std::string& portName,
100 bool partialMatch = true) const;
101
102 virtual size_t portGroupCount() const;
103 virtual const NetlistPortGroup& portGroup(size_t index) const;
104 virtual std::vector<const NetlistPortGroup*> portGroupsBy(
105 SignalGroupType type) const;
106
107 virtual const Netlist& netlist() const;
108
109 virtual bool hasParentBlock() const;
110 virtual const BaseNetlistBlock& parentBlock() const;
111
112 virtual bool isVirtual() const { return false; };
113
114 virtual void build() override;
115 virtual void connect() override;
116 virtual void finalize() override;
117 virtual void write(
118 const Path& targetBaseDir, HDL targetLang = VHDL) const override;
119 virtual void writeSelf(
120 const Path& targetBaseDir, HDL targetLang = VHDL) const;
121
122 virtual size_t packageCount() const;
123 virtual const std::string& package(size_t idx) const;
124
126
127 /**
128 * Returns true if the netlist block in the block hierarchy is a leaf
129 * block.
130 *
131 * Leaf block are not modifiable: No ports, sub blocks or ports may be
132 * added or removed.
133 */
134 virtual bool isLeaf() const { return true; }
135
136 BaseNetlistBlock* shallowCopy(const std::string& instanceName = "") const;
137
138protected:
139 Netlist& netlist();
140
141 virtual NetlistPort& port(size_t index);
142 virtual BaseNetlistBlock& subBlock(size_t index);
143 virtual BaseNetlistBlock& parentBlock();
144
145 void setModuleName(const std::string& name);
146 void addSubBlock(
148 const std::string& instanceName = "");
155 void setParameter(const Parameter& param);
156 void addParameter(const Parameter& param);
157 Parameter& parameter(const std::string& name);
159 const std::string& portName,
160 bool recursiveSearch = false,
161 bool partialMatch = true) const;
162 void addPackage(const std::string& packageName);
163
164 void connectClocks();
165 void connectResets();
166
167private:
170
171 virtual void setParent(BaseNetlistBlock* parent);
172
173 /// The reference to parent block of this block.
175 /// The sub blocks of this netlist block.
177 /// The parameters of the block.
179 /// The ports of the block.
181 /// The ports of the block.
183 /// The netlist of the block.
185 /// The instance name of the block.
186 std::string instanceName_;
187 /// The module name of the block.
188 std::string moduleName_;
189 /// The referenced packages by the module.
190 std::vector<std::string> packages_;
191};
192
193/**
194 * Compares 2 NetlistBlock's names lexicographically(dictionary order).
195 *
196 * Can be used to organize containers of type NetlistBlock to dictionary
197 * order according to their instanceNames + moduleNames.
198 * @param a the first NetlistBlock to compare.
199 * @param b the second NetlistBlock to compare.
200 * @return true, if a comes before b in dictionary order.
201 */
203public:
205 const BaseNetlistBlock* a,
206 const BaseNetlistBlock* b) const {
207 return (a->instanceName() + a->moduleName()) <
208 (b->instanceName() + b->moduleName());
209 }
210};
211
212} /* namespace ProGe */
213
214#endif /* BASENETLISTBLOCK_HH */
PortContainerType ports_
The ports of the block.
BaseNetlistBlock & operator=(const BaseNetlistBlock &)
virtual const BaseNetlistBlock & subBlock(size_t index) const
virtual bool isLeaf() const
virtual size_t parameterCount() const
std::string moduleName_
The module name of the block.
virtual bool hasParameter(const std::string &name) const
BlockContainerType subBlocks_
The sub blocks of this netlist block.
std::vector< NetlistPort * > PortContainerType
void setModuleName(const std::string &name)
virtual size_t subBlockCount() const
virtual size_t packageCount() const
void setInstanceName(const std::string &name)
virtual const Parameter & parameter(const std::string &name) const
void addSubBlock(BaseNetlistBlock *subBlock, const std::string &instanceName="")
NetlistPort * addPort(NetlistPort *port)
PortContainerType & ports()
virtual size_t portGroupCount() const
void deleteSubBlock(BaseNetlistBlock *subBlock)
virtual const std::string & package(size_t idx) const
virtual bool isVirtual() const
virtual bool hasSubBlock(const std::string &instanceName) const
BaseNetlistBlock(const BaseNetlistBlock &)
PortGroupContainerType portGroups_
The ports of the block.
virtual std::vector< const NetlistPort * > portsBy(SignalType type) const
std::string instanceName_
The instance name of the block.
BaseNetlistBlock * shallowCopy(const std::string &instanceName="") const
virtual const NetlistPortGroup & portGroup(size_t index) const
void addParameter(const Parameter &param)
BaseNetlistBlock * parent_
The reference to parent block of this block.
std::vector< Parameter > ParameterContainerType
virtual void build() override
virtual bool hasPortsBy(SignalType type) const
virtual bool isSubBlock(const BaseNetlistBlock &block) const
virtual const NetlistPort & portBy(SignalType type, size_t index=0) const
virtual const NetlistPort & port(size_t index) const
const std::string & instanceName() const
void removePortGroup(NetlistPortGroup *portGroup)
virtual bool hasParentBlock() const
virtual size_t portCount() const
virtual std::vector< const NetlistPortGroup * > portGroupsBy(SignalGroupType type) const
void removeSubBlock(BaseNetlistBlock *subBlock)
virtual void connect() override
Netlist * netlist_
The netlist of the block.
virtual const BaseNetlistBlock & parentBlock() const
ParameterContainerType parameters_
The parameters of the block.
const std::string & moduleName() const
std::vector< NetlistPortGroup * > PortGroupContainerType
void addPackage(const std::string &packageName)
const std::string name() const
virtual void writeSelf(const Path &targetBaseDir, HDL targetLang=VHDL) const
void addPortGroup(NetlistPortGroup *portGroup)
void setParameter(const Parameter &param)
virtual const Netlist & netlist() const
NetlistPort * findPort(const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const
void removePort(NetlistPort *port)
std::vector< BaseNetlistBlock * > BlockContainerType
virtual void finalize() override
virtual void setParent(BaseNetlistBlock *parent)
std::vector< std::string > packages_
The referenced packages by the module.
bool operator()(const BaseNetlistBlock *a, const BaseNetlistBlock *b) const
Definition FUGen.hh:54
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40
@ VHDL
VHDL.
Definition ProGeTypes.hh:41