OpenASIP 2.2
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SinglePortByteMaskSSRAMBlock.hh
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1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * @file SinglePortByteMaskSSRAMBlock.hh
26 *
27 * Declaration of SinglePortByteMaskSSRAMBlock class.
28 *
29 * Created on: 8.9.2015
30 * @author Henry Linjam�ki 2015 (henry.linjamaki-no.spam-tut.fi)
31 * @note rating: red
32 */
33
34#ifndef SinglePortByteMaskSSRAMBlock_HH
35#define SinglePortByteMaskSSRAMBlock_HH
36
37#include <string>
38
39#include "BaseNetlistBlock.hh"
40
41namespace ProGe {
42
43/*
44 * Netlist block of single port synchronous SRAM with byte mask.
45 */
47public:
50 const std::string& addressWidth,
51 const std::string& dataWidth,
52 const std::string& initFile,
53 bool isForSimulation = true);
55
56 void setAccessTraceFile(const std::string filename);
57 const NetlistPortGroup& memoryPort() const;
58
59 virtual void write(
60 const Path& targetBaseDir, HDL targetLang = VHDL) const override;
61
62private:
63
65
66 bool isForSimulation_ = true;
67};
68
69} /* namespace ProGe */
70
71#endif /* SinglePortByteMaskSSRAMBlock_HH */
void setAccessTraceFile(const std::string filename)
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const override
Definition FUGen.hh:54
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40
@ VHDL
VHDL.
Definition ProGeTypes.hh:41