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Public Member Functions | Private Attributes | List of all members
ProGe::SinglePortByteMaskSSRAMBlock Class Reference

#include <SinglePortByteMaskSSRAMBlock.hh>

Inheritance diagram for ProGe::SinglePortByteMaskSSRAMBlock:
Inheritance graph
Collaboration diagram for ProGe::SinglePortByteMaskSSRAMBlock:
Collaboration graph

Public Member Functions

 SinglePortByteMaskSSRAMBlock ()=delete
 
 SinglePortByteMaskSSRAMBlock (const std::string &addressWidth, const std::string &dataWidth, const std::string &initFile, bool isForSimulation=true)
 
virtual ~SinglePortByteMaskSSRAMBlock ()
 
void setAccessTraceFile (const std::string filename)
 
const NetlistPortGroupmemoryPort () const
 
virtual void write (const Path &targetBaseDir, HDL targetLang=VHDL) const override
 
- Public Member Functions inherited from ProGe::BaseNetlistBlock
 BaseNetlistBlock ()
 
 BaseNetlistBlock (BaseNetlistBlock *parent)
 
 BaseNetlistBlock (const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=nullptr)
 
virtual ~BaseNetlistBlock ()
 
const std::string & instanceName () const
 
void setInstanceName (const std::string &name)
 
const std::string & moduleName () const
 
const std::string name () const
 
virtual size_t subBlockCount () const
 
virtual const BaseNetlistBlocksubBlock (size_t index) const
 
virtual bool hasSubBlock (const std::string &instanceName) const
 
virtual bool isSubBlock (const BaseNetlistBlock &block) const
 
virtual bool hasParameter (const std::string &name) const
 
virtual const Parameterparameter (const std::string &name) const
 
virtual size_t parameterCount () const
 
virtual const Parameterparameter (size_t index) const
 
virtual size_t portCount () const
 
virtual const NetlistPortport (size_t index) const
 
virtual std::vector< const NetlistPort * > portsBy (SignalType type) const
 
virtual const NetlistPortportBy (SignalType type, size_t index=0) const
 
virtual bool hasPortsBy (SignalType type) const
 
virtual const NetlistPortport (const std::string &portName, bool partialMatch=true) const
 
virtual size_t portGroupCount () const
 
virtual const NetlistPortGroupportGroup (size_t index) const
 
virtual std::vector< const NetlistPortGroup * > portGroupsBy (SignalGroupType type) const
 
virtual const Netlistnetlist () const
 
virtual bool hasParentBlock () const
 
virtual const BaseNetlistBlockparentBlock () const
 
virtual bool isVirtual () const
 
virtual void build () override
 
virtual void connect () override
 
virtual void finalize () override
 
virtual void writeSelf (const Path &targetBaseDir, HDL targetLang=VHDL) const
 
virtual size_t packageCount () const
 
virtual const std::string & package (size_t idx) const
 
PortContainerTypeports ()
 
virtual bool isLeaf () const
 
BaseNetlistBlockshallowCopy (const std::string &instanceName="") const
 
- Public Member Functions inherited from ProGe::IGenerationPhases
virtual ~IGenerationPhases ()
 

Private Attributes

NetlistPortGroupmemoryPortGroup_ = nullptr
 
bool isForSimulation_ = true
 

Additional Inherited Members

- Public Types inherited from ProGe::BaseNetlistBlock
typedef std::vector< BaseNetlistBlock * > BlockContainerType
 
typedef std::vector< ParameterParameterContainerType
 
typedef std::vector< NetlistPort * > PortContainerType
 
typedef std::vector< NetlistPortGroup * > PortGroupContainerType
 
- Protected Member Functions inherited from ProGe::BaseNetlistBlock
Netlistnetlist ()
 
virtual NetlistPortport (size_t index)
 
virtual BaseNetlistBlocksubBlock (size_t index)
 
virtual BaseNetlistBlockparentBlock ()
 
void setModuleName (const std::string &name)
 
void addSubBlock (BaseNetlistBlock *subBlock, const std::string &instanceName="")
 
void deleteSubBlock (BaseNetlistBlock *subBlock)
 
void removeSubBlock (BaseNetlistBlock *subBlock)
 
NetlistPortaddPort (NetlistPort *port)
 
void removePort (NetlistPort *port)
 
void addPortGroup (NetlistPortGroup *portGroup)
 
void removePortGroup (NetlistPortGroup *portGroup)
 
void setParameter (const Parameter &param)
 
void addParameter (const Parameter &param)
 
Parameterparameter (const std::string &name)
 
NetlistPortfindPort (const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const
 
void addPackage (const std::string &packageName)
 
void connectClocks ()
 
void connectResets ()
 

Detailed Description

Definition at line 46 of file SinglePortByteMaskSSRAMBlock.hh.

Constructor & Destructor Documentation

◆ SinglePortByteMaskSSRAMBlock() [1/2]

ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock ( )
delete

References write().

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◆ SinglePortByteMaskSSRAMBlock() [2/2]

ProGe::SinglePortByteMaskSSRAMBlock::SinglePortByteMaskSSRAMBlock ( const std::string &  addressWidth,
const std::string &  dataWidth,
const std::string &  memInitFile,
bool  isForSimulation = true 
)

Constructs Single port synchronous SRAM block.

Parameters
addressWidthThe width of the address port.
dataWidthThe width of the data port.
memInitFileName of the memory initialization file loaded during RTL-simulation.
isForSimulationTells if the block is used in RTL simulation. Affects placement of the HDL source.

Definition at line 56 of file SinglePortByteMaskSSRAMBlock.cc.

59 : BaseNetlistBlock("synch_byte_mask_sram", ""),
60 isForSimulation_(isForSimulation) {
61 addParameter(Parameter("DATAW", "integer", dataWidth));
62 addParameter(Parameter("ADDRW", "integer", addressWidth));
63 addParameter(Parameter("INITFILENAME", "string", memInitFile));
64 addParameter(Parameter("access_trace", "boolean", "false"));
66 Parameter("ACCESSTRACEFILENAME", "string", "\"access_trace\""));
67
69
70 // todo add memory ports via PortFactory
74 new InBitPort(
75 "avalid", Signal(SignalType::AVALID, ActiveState::HIGH)),
76 new OutBitPort(
77 "aready", Signal(SignalType::AREADY, ActiveState::HIGH)),
78 new InPort("aaddr", "ADDRW", BIT_VECTOR, SignalType::AADDR),
79 new InBitPort(
80 "awren", Signal(SignalType::AWREN, ActiveState::HIGH)),
81 new InPort(
82 "astrb", dataWidth + "/8", BIT_VECTOR, SignalType::ASTRB),
83 new InBitPort(
84 "rready", Signal(SignalType::RREADY, ActiveState::HIGH)),
85 new OutPort("rdata", "DATAW", BIT_VECTOR, SignalType::RDATA),
86 new InPort("adata", "DATAW", BIT_VECTOR, SignalType::ADATA),
87 new OutBitPort(
88 "rvalid", Signal(SignalType::RVALID, ActiveState::HIGH))));
89}
NetlistPort * addPort(NetlistPort *port)
void addParameter(const Parameter &param)
void addPortGroup(NetlistPortGroup *portGroup)
static NetlistPort * clockPort(Direction direction=IN)
@ BIT_VECTOR
Several bits.
Definition ProGeTypes.hh:48
@ BYTEMASKED_SRAM_PORT
Signal group type for one port SRAM having read and write capability and bitmask for writing with sep...
@ AVALID
Signal types for memory interface with separate valid/ready in address/data.

References ProGe::AADDR, ProGe::ADATA, ProGe::BaseNetlistBlock::addParameter(), ProGe::BaseNetlistBlock::addPort(), ProGe::BaseNetlistBlock::addPortGroup(), ProGe::AREADY, ProGe::ASTRB, ProGe::AVALID, ProGe::AWREN, ProGe::BIT_VECTOR, ProGe::BYTEMASKED_SRAM_PORT, ProGe::PortFactory::clockPort(), ProGe::HIGH, memoryPortGroup_, ProGe::BaseNetlistBlock::NetlistPortGroup, ProGe::BaseNetlistBlock::Parameter, ProGe::RDATA, ProGe::RREADY, and ProGe::RVALID.

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◆ ~SinglePortByteMaskSSRAMBlock()

ProGe::SinglePortByteMaskSSRAMBlock::~SinglePortByteMaskSSRAMBlock ( )
virtual

Definition at line 91 of file SinglePortByteMaskSSRAMBlock.cc.

91{}

Member Function Documentation

◆ memoryPort()

const NetlistPortGroup & ProGe::SinglePortByteMaskSSRAMBlock::memoryPort ( ) const

Definition at line 103 of file SinglePortByteMaskSSRAMBlock.cc.

103 {
104 assert(memoryPortGroup_ != nullptr);
105 return *memoryPortGroup_;
106}
#define assert(condition)

References assert, and memoryPortGroup_.

Referenced by ProGe::ProcessorWrapperBlock::addDataMemory2().

◆ setAccessTraceFile()

void ProGe::SinglePortByteMaskSSRAMBlock::setAccessTraceFile ( const std::string  filename)

Sets a file name where memory access trace is dumped for this memory.

Definition at line 97 of file SinglePortByteMaskSSRAMBlock.cc.

97 {
98 this->setParameter(Parameter("access_trace", "boolean", "true"));
99 this->setParameter(Parameter("ACCESSTRACEFILENAME", "string", filename));
100}
void setParameter(const Parameter &param)

References ProGe::BaseNetlistBlock::Parameter, and ProGe::BaseNetlistBlock::setParameter().

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◆ write()

void ProGe::SinglePortByteMaskSSRAMBlock::write ( const Path targetBaseDir,
HDL  targetLang = VHDL 
) const
overridevirtual

Does nothing on self but calls write function on each sub block.

Reimplemented from ProGe::BaseNetlistBlock.

Definition at line 109 of file SinglePortByteMaskSSRAMBlock.cc.

110 {
111 Path progeDataDir(Environment::dataDirPath("ProGe"));
112
113 assert(targetLang == VHDL);
114
115 std::string tempFile = std::string("synch_byte_mask_sram.vhdl");
116 std::string targetDir =
117 (isForSimulation_) ? std::string("tb")
118 : ((targetLang == VHDL) ? std::string("vhdl")
119 : std::string("verilog"));
121 (progeDataDir / std::string("tb") / tempFile).string(),
122 (targetBaseDir / targetDir / tempFile).string());
123}
static std::string dataDirPath(const std::string &prog)
void instantiateTemplateFile(const std::string &templateFile, const std::string &dstFile)
@ VHDL
VHDL.
Definition ProGeTypes.hh:41

References assert, Environment::dataDirPath(), HDLTemplateInstantiator::instantiateTemplateFile(), isForSimulation_, and ProGe::VHDL.

Referenced by SinglePortByteMaskSSRAMBlock().

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Member Data Documentation

◆ isForSimulation_

bool ProGe::SinglePortByteMaskSSRAMBlock::isForSimulation_ = true
private

Definition at line 66 of file SinglePortByteMaskSSRAMBlock.hh.

Referenced by write().

◆ memoryPortGroup_

NetlistPortGroup* ProGe::SinglePortByteMaskSSRAMBlock::memoryPortGroup_ = nullptr
private

Definition at line 64 of file SinglePortByteMaskSSRAMBlock.hh.

Referenced by memoryPort(), and SinglePortByteMaskSSRAMBlock().


The documentation for this class was generated from the following files: