OpenASIP 2.2
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TestBenchBlock.hh
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1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * @file TestBenchBlock.hh
26 *
27 * Declaration of TestBenchBlock class.
28 *
29 * Created on: 7.9.2015
30 * @author Henry Linjamäki 2015 (henry.linjamaki-no.spam-tut.fi)
31 * @note rating: red
32 */
33
34#ifndef TESTBENCHBLOCK_HH
35#define TESTBENCHBLOCK_HH
36
37#include "BaseNetlistBlock.hh"
38
39#include "Exception.hh"
40
41namespace ProGe {
42
43class ProGeContext;
44class ProcessorWrapperBlock;
45
46/*
47 * Block that generates testbench template for TTA cores to run
48 * programs in RTL simulations.
49 */
51public:
52 TestBenchBlock() = delete;
54 const ProGeContext& context, const BaseNetlistBlock& coreBlock);
55 virtual ~TestBenchBlock();
56
57 virtual void write(
58 const Path& targetBaseDir, HDL targetLang = VHDL) const override;
59
60private:
61
62 /// The ProGe context for additional information.
64 /// The block that wraps the processor and instantiates memories for the
65 /// GCU and LSUs
67};
68
69} /* namespace ProGe */
70
71#endif /* TESTBENCHBLOCK_HH */
ProcessorWrapperBlock * proc_
The block that wraps the processor and instantiates memories for the GCU and LSUs.
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const override
const ProGeContext & context_
The ProGe context for additional information.
Definition FUGen.hh:54
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40
@ VHDL
VHDL.
Definition ProGeTypes.hh:41