#include <ProcessorWrapperBlock.hh>

Inheritance diagram for ProGe::ProcessorWrapperBlock:

Collaboration diagram for ProGe::ProcessorWrapperBlock:

Public Member Functions
	ProcessorWrapperBlock ()=delete

	ProcessorWrapperBlock (const ProGeContext &context, const BaseNetlistBlock &processorBlock)

virtual	~ProcessorWrapperBlock ()

virtual void	write (const Path &targetBaseDir, HDL targetLang=VHDL) const override

Public Member Functions inherited from ProGe::BaseNetlistBlock
	BaseNetlistBlock ()

	BaseNetlistBlock (BaseNetlistBlock *parent)

	BaseNetlistBlock (const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=nullptr)

virtual	~BaseNetlistBlock ()

const std::string &	instanceName () const

void	setInstanceName (const std::string &name)

const std::string &	moduleName () const

const std::string	name () const

virtual size_t	subBlockCount () const

virtual const BaseNetlistBlock &	subBlock (size_t index) const

virtual bool	hasSubBlock (const std::string &instanceName) const

virtual bool	isSubBlock (const BaseNetlistBlock &block) const

virtual bool	hasParameter (const std::string &name) const

virtual const Parameter &	parameter (const std::string &name) const

virtual size_t	parameterCount () const

virtual const Parameter &	parameter (size_t index) const

virtual size_t	portCount () const

virtual const NetlistPort &	port (size_t index) const

virtual std::vector< const NetlistPort * >	portsBy (SignalType type) const

virtual const NetlistPort &	portBy (SignalType type, size_t index=0) const

virtual bool	hasPortsBy (SignalType type) const

virtual const NetlistPort *	port (const std::string &portName, bool partialMatch=true) const

virtual size_t	portGroupCount () const

virtual const NetlistPortGroup &	portGroup (size_t index) const

virtual std::vector< const NetlistPortGroup * >	portGroupsBy (SignalGroupType type) const

virtual const Netlist &	netlist () const

virtual bool	hasParentBlock () const

virtual const BaseNetlistBlock &	parentBlock () const

virtual bool	isVirtual () const

virtual void	build () override

virtual void	connect () override

virtual void	finalize () override

virtual void	writeSelf (const Path &targetBaseDir, HDL targetLang=VHDL) const

virtual size_t	packageCount () const

virtual const std::string &	package (size_t idx) const

PortContainerType &	ports ()

virtual bool	isLeaf () const

BaseNetlistBlock *	shallowCopy (const std::string &instanceName="") const

Public Member Functions inherited from ProGe::IGenerationPhases
virtual	~IGenerationPhases ()

Private Member Functions
void	addInstructionMemory (const NetlistPortGroup &)

void	addDataMemory (const MemoryBusInterface &)

void	addDataMemory2 (const MemoryBusInterface &)

void	connectLockStatus (const NetlistPort &topPCInitPort)

void	connectPCInit (const NetlistPort &topPCInitPort)

void	handleUnconnectedPorts ()

Private Attributes
const ProGeContext &	context_

BaseNetlistBlock *	coreBlock_
	The target TTA processor.

unsigned	imemCount_ = 0

Additional Inherited Members
Public Types inherited from ProGe::BaseNetlistBlock
typedef std::vector< BaseNetlistBlock * >	BlockContainerType

typedef std::vector< Parameter >	ParameterContainerType

typedef std::vector< NetlistPort * >	PortContainerType

typedef std::vector< NetlistPortGroup * >	PortGroupContainerType

Protected Member Functions inherited from ProGe::BaseNetlistBlock
Netlist &	netlist ()

virtual NetlistPort &	port (size_t index)

virtual BaseNetlistBlock &	subBlock (size_t index)

virtual BaseNetlistBlock &	parentBlock ()

void	setModuleName (const std::string &name)

void	addSubBlock (BaseNetlistBlock *subBlock, const std::string &instanceName="")

void	deleteSubBlock (BaseNetlistBlock *subBlock)

void	removeSubBlock (BaseNetlistBlock *subBlock)

NetlistPort *	addPort (NetlistPort *port)

void	removePort (NetlistPort *port)

void	addPortGroup (NetlistPortGroup *portGroup)

void	removePortGroup (NetlistPortGroup *portGroup)

void	setParameter (const Parameter &param)

void	addParameter (const Parameter &param)

Parameter &	parameter (const std::string &name)

NetlistPort *	findPort (const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const

void	addPackage (const std::string &packageName)

void	connectClocks ()

void	connectResets ()

Detailed Description

Definition at line 51 of file ProcessorWrapperBlock.hh.

Constructor & Destructor Documentation

◆ ProcessorWrapperBlock() [1/2]

ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock ( )

delete

References write().

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◆ ProcessorWrapperBlock() [2/2]

ProGe::ProcessorWrapperBlock::ProcessorWrapperBlock	(	const ProGeContext &	context,
		const BaseNetlistBlock &	processorBlock
	)

Definition at line 53 of file ProcessorWrapperBlock.cc.

    : BaseNetlistBlock("proc", ""),
      context_(context),
      coreBlock_(processorBlock.shallowCopy()) {
    assert(processorBlock.portCount() > 0);
    assert(coreBlock_->portCount() > 0);
 
    // Wrapper interface //
    addPort(PortFactory::clockPort());
    addPort(PortFactory::resetPort());
    NetlistPort* coreLocked = new OutPort("locked", "1");
    addPort(coreLocked);
 
    // Instantiate core //
    addSubBlock(coreBlock_);
 
    // Memory instantiations and connections //
    for (size_t i = 0; i < coreBlock_->portGroupCount(); i++) {
        const NetlistPortGroup& portGrp = coreBlock_->portGroup(i);
        SignalGroupType type = portGrp.assignedSignalGroup().type();
        if (type == SignalGroupType::INSTRUCTION_LINE) {
            addInstructionMemory(portGrp);
        } else if (type == SignalGroupType::BITMASKED_SRAM_PORT) {
            auto dmemIf = dynamic_cast<const MemoryBusInterface*>(&portGrp);
            assert(dmemIf != nullptr);
            addDataMemory(*dmemIf);
        } else if (type == SignalGroupType::BYTEMASKED_SRAM_PORT) {
            auto dmemIf = dynamic_cast<const MemoryBusInterface*>(&portGrp);
            assert(dmemIf != nullptr);
            addDataMemory2(*dmemIf);
        }
    }
 
    connectClocks();
    connectResets();
    connectLockStatus(*coreLocked);
 
    // Package holding instruction bus constants
    std::set<std::string> procPackages{context.globalPackage().name()};
 
    // Other packages possibly holding constants used in core ports.
    for (size_t i = 0; i < processorBlock.packageCount(); i++) {
        procPackages.insert(processorBlock.package(i));
    }
 
    for (auto packageStr : procPackages) {
        addPackage(packageStr);
    }
 
    addPackage(context.coreEntityName() + "_params");
 
    // Handle unknown ports
    handleUnconnectedPorts();
}

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◆ ~ProcessorWrapperBlock()

ProGe::ProcessorWrapperBlock::~ProcessorWrapperBlock ( )

virtual

Definition at line 109 of file ProcessorWrapperBlock.cc.

109{}

Member Function Documentation

◆ addDataMemory()

void ProGe::ProcessorWrapperBlock::addDataMemory ( const MemoryBusInterface & coreDmemPort )

private

Definition at line 179 of file ProcessorWrapperBlock.cc.

                                                                           {
    using SigT = SignalType;
 
    const NetlistPort& addrPort = coreDmemPort.portBySignal(SigT::ADDRESS);
    const NetlistPort& dataPort = coreDmemPort.portBySignal(SigT::WRITE_DATA);
 
    SinglePortSSRAMBlock* dmemBlock = new SinglePortSSRAMBlock(
        addrPort.widthFormula(), dataPort.widthFormula(),
        TCEString("tb/dmem_") + coreDmemPort.addressSpace() + "_init.img",
        /* isForSmulation = */ true);
    addSubBlock(dmemBlock, TCEString("dmem_") + coreDmemPort.addressSpace());
 
    if (!netlist().connect(dmemBlock->memoryPort(), coreDmemPort)) {
        THROW_EXCEPTION(
            IllegalConnectivity,
            "Could not connect two port groups together.");
    }
}

References ProGe::MemoryBusInterface::addressSpace(), ProGe::SinglePortSSRAMBlock::memoryPort(), ProGe::NetlistPortGroup::portBySignal(), THROW_EXCEPTION, and ProGe::NetlistPort::widthFormula().

Referenced by ProcessorWrapperBlock().

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◆ addDataMemory2()

void ProGe::ProcessorWrapperBlock::addDataMemory2 ( const MemoryBusInterface & coreDmemPort )

private

Definition at line 199 of file ProcessorWrapperBlock.cc.

                                            {
    using SigT = SignalType;
 
    const NetlistPort& addrPort = coreDmemPort.portBySignal(SigT::AADDR);
    const NetlistPort& dataPort = coreDmemPort.portBySignal(SigT::RDATA);
 
    SinglePortByteMaskSSRAMBlock* dmemBlock =
        new SinglePortByteMaskSSRAMBlock(
            addrPort.widthFormula(), dataPort.widthFormula(),
            TCEString("tb/dmem_") + coreDmemPort.addressSpace() + "_init.img",
            /* isForSmulation = */ true);
    addSubBlock(dmemBlock, TCEString("dmem_") + coreDmemPort.addressSpace());
 
    if (!netlist().connect(dmemBlock->memoryPort(), coreDmemPort)) {
        THROW_EXCEPTION(
            IllegalConnectivity,
            "Could not connect two port groups together.");
    }
}

References ProGe::MemoryBusInterface::addressSpace(), ProGe::SinglePortByteMaskSSRAMBlock::memoryPort(), ProGe::NetlistPortGroup::portBySignal(), THROW_EXCEPTION, and ProGe::NetlistPort::widthFormula().

Referenced by ProcessorWrapperBlock().

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◆ addInstructionMemory()

void ProGe::ProcessorWrapperBlock::addInstructionMemory ( const NetlistPortGroup & coreImemPort )

private

Definition at line 120 of file ProcessorWrapperBlock.cc.

                                          {
    using SigT = SignalType;
    bool isRISCV = context_.adf().isRISCVMachine();
 
    const int imemWidthInMaus = (context_.adf().isRISCVMachine()) ? 4 : 1;
    const int unusedBits = std::ceil(std::log2(imemWidthInMaus));
 
    std::string addrWidth = context_.globalPackage().fetchBlockAddressWidth();
    if (isRISCV) {
        const int unusedBits = std::ceil(std::log2(imemWidthInMaus));
        addrWidth = context_.globalPackage().fetchBlockAddressWidth() + "-" +
                    std::to_string(unusedBits);
    }
 
    SinglePortSSRAMBlock* imemBlock = new SinglePortSSRAMBlock(
        addrWidth, context_.globalPackage().fetchBlockDataWidth(),
        "tb/imem_init.img", true);
    addSubBlock(imemBlock, "imem0");
    // todo: use core id instead of counter value.
    std::string accessTrace = std::string("core") +
                              Conversion::toString(imemCount_++) +
                              "_imem_access_trace.dump";
    imemBlock->setAccessTraceFile(accessTrace);
 
    if (isRISCV) {
        // With RISC-V the two lower bits are unused
        const int realAddrWidth = MathTools::requiredBits(
            context_.adf().controlUnit()->addressSpace()->end());
        netlist().connect(
            imemBlock->memoryPort(), coreImemPort,
            {{SigT::READ_DATA, SigT::FETCHBLOCK},
             {SigT::READ_WRITE_REQUEST, SigT::READ_REQUEST}});
        netlist().connect(
            imemBlock->memoryPort().portBySignal(SigT::ADDRESS),
            coreImemPort.portBySignal(SigT::ADDRESS), 0, unusedBits,
            realAddrWidth - unusedBits);
    } else {
        netlist().connect(
            imemBlock->memoryPort(), coreImemPort,
            {{SigT::ADDRESS, SigT::ADDRESS},
             {SigT::READ_DATA, SigT::FETCHBLOCK},
             {SigT::READ_WRITE_REQUEST, SigT::READ_REQUEST}});
    }
 
    imemBlock->memoryPort()
        .portBySignal(SigT::WRITE_BITMASK)
        .setToStatic(StaticSignal::VCC);
    imemBlock->memoryPort()
        .portBySignal(SigT::WRITEMODE)
        .setToStatic(StaticSignal::VCC);
    imemBlock->memoryPort()
        .portBySignal(SigT::WRITE_DATA)
        .setToStatic(StaticSignal::GND);
    coreImemPort.portBySignal(SigT::READ_REQUEST_READY)
        .setToStatic(StaticSignal::GND);  // Active low
}

References TTAMachine::FunctionUnit::addressSpace(), ProGe::BaseNetlistBlock::addSubBlock(), ProGe::ProGeContext::adf(), ProGe::Netlist::connect(), context_, TTAMachine::Machine::controlUnit(), TTAMachine::AddressSpace::end(), ProGe::GlobalPackage::fetchBlockAddressWidth(), ProGe::GlobalPackage::fetchBlockDataWidth(), ProGe::ProGeContext::globalPackage(), imemCount_, TTAMachine::Machine::isRISCVMachine(), ProGe::SinglePortSSRAMBlock::memoryPort(), ProGe::BaseNetlistBlock::netlist(), ProGe::NetlistPortGroup::portBySignal(), MathTools::requiredBits(), ProGe::SinglePortSSRAMBlock::setAccessTraceFile(), and Conversion::toString().

Referenced by ProcessorWrapperBlock().

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◆ connectLockStatus()

void ProGe::ProcessorWrapperBlock::connectLockStatus ( const NetlistPort & topPCInitPort )

private

Definition at line 221 of file ProcessorWrapperBlock.cc.

                                          {
    assert(
        coreBlock_->port("locked") != nullptr &&
        "Could not found lock status port.");
    if (!netlist().connect(*coreBlock_->port("locked"), topLockStatusPort)) {
        THROW_EXCEPTION(
            IllegalConnectivity,
            "Could not connect \"locked\" signal to the toplevel");
    }
}

References assert, and THROW_EXCEPTION.

Referenced by ProcessorWrapperBlock().

◆ connectPCInit()

void ProGe::ProcessorWrapperBlock::connectPCInit ( const NetlistPort & topPCInitPort )

private

◆ handleUnconnectedPorts()

void ProGe::ProcessorWrapperBlock::handleUnconnectedPorts ( )

private

Handles unconnected ports of the top-level TTA processor by connecting them to the toplevel

Definition at line 238 of file ProcessorWrapperBlock.cc.

                                              {
    for (size_t i = 0; i < coreBlock_->portCount(); i++) {
        const NetlistPort& port =
            ((const BaseNetlistBlock*)coreBlock_)->port(i);
        if (!netlist().isPortConnected(port) && !port.hasStaticValue()) {
            NetlistPort* topPort = port.clone();
            addPort(topPort);
            netlist().connect(*topPort, port);
        }
    }
}

References ProGe::NetlistPort::clone(), and ProGe::NetlistPort::hasStaticValue().

Referenced by ProcessorWrapperBlock().

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◆ write()

void ProGe::ProcessorWrapperBlock::write	(	const Path &	targetBaseDir,
		HDL	targetLang = `VHDL`
	)		const

overridevirtual

Does nothing on self but calls write function on each sub block.

Reimplemented from ProGe::BaseNetlistBlock.

Definition at line 112 of file ProcessorWrapperBlock.cc.

                                                     {
    BaseNetlistBlock::writeSelf(
        targetBaseDir / std::string("tb"), targetLang);
    BaseNetlistBlock::write(targetBaseDir, targetLang);
}

References ProGe::BaseNetlistBlock::write(), and ProGe::BaseNetlistBlock::writeSelf().

Referenced by ProcessorWrapperBlock(), and ProGe::TestBenchBlock::write().

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Member Data Documentation

◆ context_

const ProGeContext& ProGe::ProcessorWrapperBlock::context_

private

Definition at line 74 of file ProcessorWrapperBlock.hh.

Referenced by addInstructionMemory().

◆ coreBlock_

BaseNetlistBlock* ProGe::ProcessorWrapperBlock::coreBlock_

private

The target TTA processor.

Definition at line 76 of file ProcessorWrapperBlock.hh.

Referenced by ProcessorWrapperBlock().

◆ imemCount_

unsigned ProGe::ProcessorWrapperBlock::imemCount_ = 0

private

Definition at line 77 of file ProcessorWrapperBlock.hh.

Referenced by addInstructionMemory().

The documentation for this class was generated from the following files:

Public Member Functions

Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ ProcessorWrapperBlock() [1/2]

◆ ProcessorWrapperBlock() [2/2]

◆ ~ProcessorWrapperBlock()

Member Function Documentation

◆ addDataMemory()

◆ addDataMemory2()

◆ addInstructionMemory()

◆ connectLockStatus()

◆ connectPCInit()

◆ handleUnconnectedPorts()

◆ write()

Member Data Documentation

◆ context_

◆ coreBlock_

◆ imemCount_