34#ifndef PROCESSORWRAPPERBLOCK_HH
35#define PROCESSORWRAPPERBLOCK_HH
43class NetlistPortGroup;
45class MemoryBusInterface;
60 const Path& targetBaseDir,
HDL targetLang =
VHDL)
const override;
BaseNetlistBlock * coreBlock_
The target TTA processor.
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const override
void connectPCInit(const NetlistPort &topPCInitPort)
const ProGeContext & context_
virtual ~ProcessorWrapperBlock()
void addInstructionMemory(const NetlistPortGroup &)
void addDataMemory2(const MemoryBusInterface &)
void handleUnconnectedPorts()
void addDataMemory(const MemoryBusInterface &)
void connectLockStatus(const NetlistPort &topPCInitPort)
ProcessorWrapperBlock()=delete
HDL
HDLs supported by ProGe.