#include <VerilogNetlistWriter.hh>

Inheritance diagram for ProGe::VerilogNetlistWriter:

Collaboration diagram for ProGe::VerilogNetlistWriter:

Public Member Functions
	VerilogNetlistWriter (const BaseNetlistBlock &targetBlock)

virtual	~VerilogNetlistWriter ()

virtual void	write (const std::string &dstDirectory)

Public Member Functions inherited from ProGe::NetlistWriter
	NetlistWriter (const BaseNetlistBlock &targetBlock)

virtual	~NetlistWriter ()

Static Public Member Functions
static void	writeGenericDeclaration (const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)

static void	writePortDeclaration (const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)

Private Types
typedef boost::graph_traits< Netlist >::vertex_descriptor	vertex_descriptor

typedef boost::graph_traits< Netlist >::edge_descriptor	edge_descriptor

typedef boost::graph_traits< Netlist >::out_edge_iterator	out_edge_iterator

Private Member Functions
void	writeNetlistParameterPackage (const std::string &dstDirectory) const

std::string	netlistParameterPkgName () const

void	writeBlock (const BaseNetlistBlock &block, const std::string &dstDirectory)

void	writeSignalDeclarations (const BaseNetlistBlock &block, std::ofstream &stream)

void	writeSignalAssignments (const BaseNetlistBlock &block, std::ofstream &stream) const

void	writeComponentDeclarations (const BaseNetlistBlock &block, std::ofstream &stream) const

void	writePortMappings (const BaseNetlistBlock &block, std::ofstream &stream) const

std::string	indentation (unsigned int level) const

TCEString	genericMapStringValue (const TCEString &generic) const

Static Private Member Functions
static std::string	directionString (Direction direction)

static std::string	generateIndentation (unsigned int level, const std::string &indentation)

static bool	isNumber (const std::string &formula)

static std::string	portSignalName (const NetlistPort &port)

static std::string	portSignalType (const NetlistPort &port)

Private Attributes
int	groundWidth_
	Width of the ground signal.

Additional Inherited Members
Protected Member Functions inherited from ProGe::NetlistWriter
const BaseNetlistBlock &	targetNetlistBlock () const

Detailed Description

Writes Verilog files which implement the given netlist.

Definition at line 52 of file VerilogNetlistWriter.hh.

Member Typedef Documentation

◆ edge_descriptor

typedef boost::graph_traits<Netlist>::edge_descriptor ProGe::VerilogNetlistWriter::edge_descriptor

private

Definition at line 74 of file VerilogNetlistWriter.hh.

◆ out_edge_iterator

typedef boost::graph_traits<Netlist>::out_edge_iterator ProGe::VerilogNetlistWriter::out_edge_iterator

private

Definition at line 76 of file VerilogNetlistWriter.hh.

◆ vertex_descriptor

typedef boost::graph_traits<Netlist>::vertex_descriptor ProGe::VerilogNetlistWriter::vertex_descriptor

private

Definition at line 72 of file VerilogNetlistWriter.hh.

Constructor & Destructor Documentation

◆ VerilogNetlistWriter()

ProGe::VerilogNetlistWriter::VerilogNetlistWriter ( const BaseNetlistBlock & targetBlock )

Constructor. Records the input netlist for which it can generate Verilog.

Parameters

netlist The input netlist.

Definition at line 68 of file VerilogNetlistWriter.cc.

70 : NetlistWriter(targetBlock), groundWidth_(0) {}

ProGe::NetlistWriter::NetlistWriter

NetlistWriter(const BaseNetlistBlock &targetBlock)

Definition NetlistWriter.cc:46

ProGe::VerilogNetlistWriter::groundWidth_

int groundWidth_

Width of the ground signal.

Definition VerilogNetlistWriter.hh:117

◆ ~VerilogNetlistWriter()

ProGe::VerilogNetlistWriter::~VerilogNetlistWriter ( )

virtual

The destructor.

Definition at line 75 of file VerilogNetlistWriter.cc.

75 {

76}

Member Function Documentation

◆ directionString()

std::string ProGe::VerilogNetlistWriter::directionString ( Direction direction )

staticprivate

Returns the string that means the same direction as the given one in Verilog.

Returns: The direction string.

Definition at line 573 of file VerilogNetlistWriter.cc.

                                                         {
    switch (direction) {
        case IN:
            return "input";
        case OUT:
            return "output";
        case BIDIR:
            return "inout";
    }
    assert(false);
    // dummy return
    return "";
}

References assert, ProGe::BIDIR, ProGe::IN, and ProGe::OUT.

Referenced by writePortDeclaration().

◆ generateIndentation()

std::string ProGe::VerilogNetlistWriter::generateIndentation	(	unsigned int	indentationLevel,
		const std::string &	indentation
	)

staticprivate

Generates an indentation string with the given parameters.

Parameters

indentationLevel	The level of indentation.
indentation	The string used as indentation (one level).

Returns: The indentation of the given level.

Definition at line 623 of file VerilogNetlistWriter.cc.

                                  {
 
    string generatedInd("");
    for (unsigned int i = 0; i < indentationLevel; i++) {
        generatedInd += indentation;
    }
    return generatedInd;
}

References indentation().

Referenced by writeGenericDeclaration(), and writePortDeclaration().

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◆ genericMapStringValue()

TCEString ProGe::VerilogNetlistWriter::genericMapStringValue ( const TCEString & generic ) const

private

Tries to determine whether the string generic needs quot marks for generic mapping

If string literal contains '.', or "__" it cannot be a valid Verilog label (i.e. another generic), thus it needs quotation marks.

Parameters

generic String generic value

Returns: Generic mapping string

Definition at line 676 of file VerilogNetlistWriter.cc.

                                                                          {
 
    if (generic.startsWith("\"") && generic.endsWith("\"")) {
        return generic;
    }
    std::vector<TCEString> unallowed;
    unallowed.push_back(".");
    unallowed.push_back("__");
    for (unsigned int i = 0; i < unallowed.size(); i++) {
        if (generic.find(unallowed.at(i)) != TCEString::npos) {
            TCEString quoted;
            quoted << "\"" << generic << "\"";
            return quoted;
        }
    }
    return generic;
}

References TCEString::endsWith(), and TCEString::startsWith().

Referenced by writePortMappings().

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◆ indentation()

std::string ProGe::VerilogNetlistWriter::indentation ( unsigned int level ) const

private

Returns a string which makes indetation of the given level.

Parameters

level The indentation level.

Definition at line 611 of file VerilogNetlistWriter.cc.

                                                          {
    return StringTools::indent(level);
}

References StringTools::indent().

Referenced by generateIndentation(), writeBlock(), writeGenericDeclaration(), writePortDeclaration(), writePortMappings(), writeSignalAssignments(), and writeSignalDeclarations().

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◆ isNumber()

bool ProGe::VerilogNetlistWriter::isNumber ( const std::string & formula )

staticprivate

Tells whether the given string is a non-negative integer number.

Parameters

formula The string.

Returns: True if the given string is a non-negative integer number.

Definition at line 594 of file VerilogNetlistWriter.cc.

                                                       {
    int length = formula.length();
    for (int i = 0; i < length; i++) {
        if (!isdigit(formula[i])) {
            return false;
        }
    }
    return true;
}

Referenced by portSignalType(), and writePortDeclaration().

◆ netlistParameterPkgName()

std::string ProGe::VerilogNetlistWriter::netlistParameterPkgName ( ) const

private

Returns the name of the netlist parameter package(include file).

Returns: The name.

Definition at line 126 of file VerilogNetlistWriter.cc.

                                                    {
    return targetNetlistBlock().moduleName() + "_params";
}

References ProGe::BaseNetlistBlock::moduleName(), and ProGe::NetlistWriter::targetNetlistBlock().

Referenced by writeBlock(), and writeNetlistParameterPackage().

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◆ portSignalName()

std::string ProGe::VerilogNetlistWriter::portSignalName ( const NetlistPort & port )

staticprivate

Returns the name of the signal mapped to the given port.

Parameters

port The port.

Definition at line 641 of file VerilogNetlistWriter.cc.

                                                            {
    const BaseNetlistBlock* parentBlock = &port.parentBlock();
    if (port.hasStaticValue()) {
        return "{" + Conversion::toString(port.realWidth()) + "{" +
               ((port.staticValue().is(StaticSignal::VCC)) ? "1'b1"
                                                           : "1'b0") +
               "}}";
    }
    return parentBlock->instanceName() + "_" + port.name() +"_wire";
}

References ProGe::NetlistPort::hasStaticValue(), ProGe::BaseNetlistBlock::instanceName(), ProGe::StaticSignal::is(), ProGe::NetlistPort::name(), ProGe::NetlistPort::parentBlock(), ProGe::NetlistPort::realWidth(), ProGe::NetlistPort::staticValue(), Conversion::toString(), and ProGe::StaticSignal::VCC.

Referenced by writePortMappings(), writeSignalAssignments(), and writeSignalDeclarations().

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◆ portSignalType()

std::string ProGe::VerilogNetlistWriter::portSignalType ( const NetlistPort & port )

staticprivate

Returns the type of the signal mapped to the given port.

Parameters

port The port.

Definition at line 659 of file VerilogNetlistWriter.cc.

                                                            {
    if (port.dataType() == BIT) {
        return "";
    } else {
        if (port.realWidthAvailable()) {
            int width = port.realWidth();
            return "[" + Conversion::toString(width?width-1:0) + ":0]";
        } else if (isNumber(port.widthFormula()) && 
                   (Conversion::toInt(port.widthFormula()) == 0)) {
            return "[0:0]";
        } else {
            return "[" + port.widthFormula()+"-1: 0]";
        }
    }
}

References ProGe::BIT, ProGe::NetlistPort::dataType(), isNumber(), ProGe::NetlistPort::realWidth(), ProGe::NetlistPort::realWidthAvailable(), Conversion::toInt(), Conversion::toString(), and ProGe::NetlistPort::widthFormula().

Referenced by writeSignalDeclarations().

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◆ write()

void ProGe::VerilogNetlistWriter::write ( const std::string & dstDirectory )

virtual

Generates the Verilog files and writes them to the given directory.

Parameters

dstDirectory The destination directory.

Exceptions

IOException	If an IO error occurs.
InvalidData	If the netlist is invalid.

Implements ProGe::NetlistWriter.

Definition at line 86 of file VerilogNetlistWriter.cc.

                                                         {
    const BaseNetlistBlock& block = this->targetNetlistBlock();
    if (block.netlist().isEmpty()) {
        string errorMsg = "Empty input netlist block.";
        throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
    }
 
    writeNetlistParameterPackage(dstDirectory);
    writeBlock(block, dstDirectory);
}

References __func__, ProGe::Netlist::isEmpty(), ProGe::BaseNetlistBlock::netlist(), ProGe::NetlistWriter::targetNetlistBlock(), writeBlock(), and writeNetlistParameterPackage().

Referenced by ProGe::BaseNetlistBlock::writeSelf().

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◆ writeBlock()

void ProGe::VerilogNetlistWriter::writeBlock	(	const BaseNetlistBlock &	block,
		const std::string &	dstDirectory
	)

private

Writes the given block of the netlist to the given destination directory.

Parameters

block	The netlist block.
dstDirectory	The destination directory.

Exceptions

IOException If the file cannot be created.

Definition at line 139 of file VerilogNetlistWriter.cc.

                                                                  {
    string fileName = dstDirectory + FileSystem::DIRECTORY_SEPARATOR +
        block.moduleName() + ".v";
    if (!FileSystem::fileIsCreatable(fileName) && 
        !(FileSystem::fileExists(fileName) && 
          FileSystem::fileIsWritable(fileName))) {
 
        string errorMsg = "Unable to create file: " + fileName;
        throw IOException(__FILE__, __LINE__, __func__, errorMsg);
    }
 
    const string entityName = block.moduleName();
 
    ofstream outFile;
    outFile.open(fileName.c_str(), ofstream::out);
 
    // create module
    outFile << "module " + entityName << endl;
 
    //create include
    string separator;
    outFile << "#(" << endl;
    if (block.netlist().parameterCount() > 0) {
        outFile << "`include \"" << netlistParameterPkgName() << "_pkg.vh\""
                << endl;
        separator = ",";
    }
 
    for (size_t i = 0; i < block.packageCount(); i++) {
        outFile << separator << endl;
        outFile << "`include \"" << block.package(i) << "_pkg.vh\"" << endl;
        separator = ",";
    }
 
    outFile << ")" << endl;
    
    // create port declarations
    writePortDeclaration(block, 1, indentation(1), outFile);
    outFile << endl;
    
    // create generics
    writeGenericDeclaration(block, 1, indentation(1), outFile);
    // create architecture
    writeSignalDeclarations(block, outFile);
    outFile << endl;
    writeSignalAssignments(block, outFile);
    outFile << endl;
    writePortMappings(block, outFile);
    outFile << "endmodule" << endl;
    outFile << endl;
    outFile.close();
}

References __func__, FileSystem::DIRECTORY_SEPARATOR, FileSystem::fileExists(), FileSystem::fileIsCreatable(), FileSystem::fileIsWritable(), indentation(), ProGe::BaseNetlistBlock::moduleName(), ProGe::BaseNetlistBlock::netlist(), netlistParameterPkgName(), ProGe::BaseNetlistBlock::package(), ProGe::BaseNetlistBlock::packageCount(), ProGe::Netlist::parameterCount(), writeGenericDeclaration(), writePortDeclaration(), writePortMappings(), writeSignalAssignments(), and writeSignalDeclarations().

Referenced by write().

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◆ writeComponentDeclarations()

void ProGe::VerilogNetlistWriter::writeComponentDeclarations	(	const BaseNetlistBlock &	block,
		std::ofstream &	stream
	)		const

private

◆ writeGenericDeclaration()

void ProGe::VerilogNetlistWriter::writeGenericDeclaration	(	const BaseNetlistBlock &	block,
		unsigned int	indentationLevel,
		const std::string &	indentation,
		std::ostream &	stream
	)

static

Writes the generic(parameter) declarations of the given netlist block.

Parameters

block	The netlist block.
indentationLevel	The indentation level where the generic declaration is written.
indentation	The string used as indentation (one level).
stream	The stream to write.

Definition at line 203 of file VerilogNetlistWriter.cc.

                                                      {
    if (block.parameterCount() > 0) {
        stream << endl;
        for (size_t i = 0; i < block.parameterCount(); i++) {
            stream << generateIndentation(indentationLevel, indentation)
                   << "parameter ";
            Parameter param = block.parameter(i);
            stream << generateIndentation(indentationLevel + 1, indentation)
                   << param.name();
            if (param.defaultValue() != "") {
                stream << " = ";
                if (param.type().lower() == PARAM_STRING) {
                    // string literal needs quot. marks
                    if (!param.defaultValue().startsWith("\""))
                        stream << "\"";
                    stream << param.defaultValue();
                    if (!param.defaultValue().endsWith("\"")) stream << "\"";
                } else {
                    stream << param.defaultValue();
                }
            }
            stream << ";" << endl;
        }
    }
}

References ProGe::Parameter::defaultValue(), TCEString::endsWith(), generateIndentation(), indentation(), TCEString::lower(), ProGe::Parameter::name(), PARAM_STRING, ProGe::BaseNetlistBlock::parameter(), ProGe::BaseNetlistBlock::parameterCount(), TCEString::startsWith(), and ProGe::Parameter::type().

Referenced by writeBlock(), DefaultDecoderGenerator::writeInstructionDecoder(), and DefaultICGenerator::writeInterconnectionNetwork().

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◆ writeNetlistParameterPackage()

void ProGe::VerilogNetlistWriter::writeNetlistParameterPackage ( const std::string & dstDirectory ) const

private

Writes the package(include files for verilog) that defines parameters of the netlist.

Parameters

dstDirectory The destination directory.

Definition at line 104 of file VerilogNetlistWriter.cc.

                                         {
    string fileName = dstDirectory + FileSystem::DIRECTORY_SEPARATOR + 
        netlistParameterPkgName() + "_pkg.vh";
    ofstream outFile;
    outFile.open(fileName.c_str(), ofstream::out);
    for (size_t i = 0; i < targetNetlistBlock().netlist().parameterCount();
         i++) {
        Parameter param = targetNetlistBlock().netlist().parameter(i);
        outFile << "parameter " << param.name() << " = " << param.value();
        if (i != targetNetlistBlock().netlist().parameterCount() - 1)
            outFile << ",";
        outFile << endl;
    }
}

References FileSystem::DIRECTORY_SEPARATOR, ProGe::Parameter::name(), ProGe::BaseNetlistBlock::netlist(), netlistParameterPkgName(), ProGe::Netlist::parameter(), ProGe::Netlist::parameterCount(), ProGe::NetlistWriter::targetNetlistBlock(), and ProGe::Parameter::value().

Referenced by write().

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◆ writePortDeclaration()

void ProGe::VerilogNetlistWriter::writePortDeclaration	(	const BaseNetlistBlock &	block,
		unsigned int	indentationLevel,
		const std::string &	indentation,
		std::ostream &	stream
	)

static

Writes the port declaration of the given netlist block.

Parameters

block	The netlist block.
indentationLevel	The indentation level where the generic declaration is written.
indentation	The string used as indentation (one level).
stream	The stream to write.

Definition at line 241 of file VerilogNetlistWriter.cc.

                                                      {
    stream << generateIndentation(indentationLevel, indentation) << "("
           << endl;
 
    for (size_t i = 0; i < block.portCount(); i++) {
        const NetlistPort& port = block.port(i);
        string portName = port.name();
        string direction = directionString(port.direction());
        stream << generateIndentation(indentationLevel+1, indentation)
               << direction;
 
        if (port.dataType() == BIT) {
           //nothing to do
        } else {
            stream << "[";
            // zero width ports as (0: 0 
            if (isNumber(port.widthFormula()) && 
                    Conversion::toInt(port.widthFormula()) == 0) {
                stream << "0";
            } else if (isNumber(port.widthFormula())) {
                stream << Conversion::toInt(port.widthFormula()) - 1;
            } else {
                stream << port.widthFormula() << "-1";
            }
            stream << ":0]";
        }
        stream << " " << portName;
        if (i + 1 == block.portCount()) {
            stream << ");";
        } else {
            stream << ",";
        }
        stream << endl;
    }
}

References ProGe::BIT, ProGe::NetlistPort::dataType(), ProGe::NetlistPort::direction(), directionString(), generateIndentation(), indentation(), isNumber(), ProGe::NetlistPort::name(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), Conversion::toInt(), and ProGe::NetlistPort::widthFormula().

Referenced by writeBlock(), DefaultDecoderGenerator::writeInstructionDecoder(), and DefaultICGenerator::writeInterconnectionNetwork().

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◆ writePortMappings()

void ProGe::VerilogNetlistWriter::writePortMappings	(	const BaseNetlistBlock &	block,
		std::ofstream &	stream
	)		const

private

Writes the port mappings of the given block to the given stream.

Parameters

block	The netlist block.
stream	The stream to write.

Definition at line 488 of file VerilogNetlistWriter.cc.

                                                              {
    for (size_t i = 0; i < block.subBlockCount(); i++) {
        const BaseNetlistBlock& component = block.subBlock(i);
 
        // virtual NetlistBlocks are omitted
        if (component.isVirtual()) {
            continue;
        }
 
        stream << indentation(1) << component.moduleName()<< endl;
 
        // create generic map(parameters)
        if (component.parameterCount() > 0) {
            stream << indentation(1) << "#(" << endl;
            for (size_t i = 0; i < component.parameterCount(); i++) {
                Parameter param = component.parameter(i);
                stream << indentation(2) << "." << param.name() << "(";
 
                if (param.type().lower() == PARAM_STRING) {
                    stream << genericMapStringValue(param.value());
                } else {
                    stream << param.value();
                }
                if (i == component.parameterCount() - 1) {
                    stream << ")";
                } else {
                    stream << "),";
                }
                stream << endl;
            }
            stream << indentation(1) << ")" << endl;
        }
        // create port map on unique(!) instance
        stream << indentation(1) << component.instanceName()
               << "_" << i << endl
               << indentation(2) << "(" << endl;
        for (size_t i = 0; i < component.portCount(); i++) {
            const NetlistPort& port = component.port(i);
            size_t vertexDescriptor = block.netlist().descriptor(port);
            std::pair<out_edge_iterator, out_edge_iterator> edges =
                boost::out_edges(vertexDescriptor, block.netlist());
 
            string srcConn = port.name();
            string dstConn = "";
            if (edges.first != edges.second) {
                edge_descriptor edgeDescriptor = *edges.first;
                vertex_descriptor dstVertex =
                    boost::target(edgeDescriptor, block.netlist());
                NetlistPort* dstPort = block.netlist()[dstVertex];
 
                if (&dstPort->parentBlock() == &block) {
                    if (port.dataType() != dstPort->dataType()) {
                        if (port.dataType() == BIT) {
                            assert(dstPort->dataType() == BIT_VECTOR);
                            dstConn = dstPort->name() + "[0]";
                        } else {
                            assert(dstPort->dataType() == BIT);
                            srcConn += "[0]";
                            dstConn = dstPort->name();
                        }
                    } else {
                        dstConn = dstPort->name();
                    }
                } else {
                    dstConn = portSignalName(port);
                }
            } else {
                dstConn = portSignalName(port);
            }
            stream << indentation(3) << "." << srcConn << "(" << dstConn << ")";
            if (i+1 < component.portCount()) {
                stream << "," << endl;
            }
        }
        stream << ");" << endl << endl;
    }
}

References assert, ProGe::BIT, ProGe::BIT_VECTOR, ProGe::NetlistPort::dataType(), ProGe::Netlist::descriptor(), genericMapStringValue(), indentation(), ProGe::BaseNetlistBlock::instanceName(), ProGe::BaseNetlistBlock::isVirtual(), TCEString::lower(), ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistPort::name(), ProGe::Parameter::name(), ProGe::BaseNetlistBlock::netlist(), PARAM_STRING, ProGe::BaseNetlistBlock::parameter(), ProGe::BaseNetlistBlock::parameterCount(), ProGe::NetlistPort::parentBlock(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), portSignalName(), ProGe::BaseNetlistBlock::subBlock(), ProGe::BaseNetlistBlock::subBlockCount(), ProGe::Parameter::type(), and ProGe::Parameter::value().

Referenced by writeBlock().

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◆ writeSignalAssignments()

void ProGe::VerilogNetlistWriter::writeSignalAssignments	(	const BaseNetlistBlock &	block,
		std::ofstream &	stream
	)		const

private

Writes the signal assignments of the given block to the given stream.

Parameters

block	The netlist block.
stream	The stream.

Definition at line 350 of file VerilogNetlistWriter.cc.

                                                              {
    set<const BaseNetlistBlock*, NetlistBlockNameComparator> subBlocks;
    for (size_t i = 0; i < block.subBlockCount(); i++) {
        subBlocks.insert(&block.subBlock(i));
    }
 
    typedef std::vector<edge_descriptor> EdgeTable;
    EdgeTable handledEdges;
 
    for (size_t i = 0; i < block.subBlockCount(); i++) {
        const BaseNetlistBlock& subBlock = block.subBlock(i);
        for (size_t i = 0; i < subBlock.portCount(); i++) {
            const NetlistPort& port = subBlock.port(i);
            size_t vertexDescriptor = block.netlist().descriptor(port);
            std::pair<out_edge_iterator, out_edge_iterator> edges =
                boost::out_edges(vertexDescriptor, block.netlist());
 
            while (edges.first != edges.second) {
                edge_descriptor edgeDescriptor = *edges.first;
                edges.first++;
                if (!ContainerTools::containsValue(
                        handledEdges, edgeDescriptor)) {
                    vertex_descriptor srcVertex =
                        boost::source(edgeDescriptor, block.netlist());
                    vertex_descriptor dstVertex =
                        boost::target(edgeDescriptor, block.netlist());
                    NetlistPort* srcPort = block.netlist()[srcVertex];
                    NetlistPort* dstPort = block.netlist()[dstVertex];
 
                    if (&dstPort->parentBlock() == &block) {
                        continue;
                    }
 
                    assert(srcPort == &port);
                    if (AssocTools::containsKey(
                            subBlocks, &srcPort->parentBlock()) &&
                        AssocTools::containsKey(
                            subBlocks, &dstPort->parentBlock())) {
                        handledEdges.push_back(edgeDescriptor);
                        // add the opposite edge too
                        std::pair<edge_descriptor, bool> opposite =
                            boost::edge(
                                dstVertex, srcVertex, block.netlist());
                        assert(opposite.second);
                        assert(opposite.first != edgeDescriptor);
                        handledEdges.push_back(opposite.first);
 
                        PortConnectionProperty property =
                            block.netlist()[edgeDescriptor];
                        if (property.fullyConnected()) {
                            if (srcPort->direction() == OUT) {
                                stream << indentation(1) << "assign "
                                       << portSignalName(*dstPort) << " = "
                                       << portSignalName(*srcPort) << ";"
                                       << endl;
                            } else {
                                stream << indentation(1) << "assign "
                                       << portSignalName(*srcPort) << " = "
                                       << portSignalName(*dstPort) << ";"
                                       << endl;
                            }
                        } else {
                            string srcPortSignal;
                            if (srcPort->dataType() == BIT) {
                                srcPortSignal = portSignalName(*srcPort);
                            } else {
                                if (dstPort->dataType() == BIT) {
                                    srcPortSignal =
                                        portSignalName(*srcPort) + "[" +
                                        Conversion::toString(
                                            property.port1FirstBit()) +
                                        "]";
                                } else {
                                    srcPortSignal =
                                        portSignalName(*srcPort) + "[" +
                                        Conversion::toString(
                                            property.port1FirstBit() +
                                            property.width() - 1) +
                                        ":" +
                                        Conversion::toString(
                                            property.port1FirstBit()) +
                                        "]";
                                }
                            }
                            string dstPortSignal;
                            if (dstPort->dataType() == BIT) {
                                dstPortSignal = portSignalName(*dstPort);
                            } else {
                                if (srcPort->dataType() == BIT) {
                                    dstPortSignal =
                                        portSignalName(*dstPort) + "[" +
                                        Conversion::toString(
                                            property.port2FirstBit()) +
                                        "]";
                                } else {
                                    dstPortSignal =
                                        portSignalName(*dstPort) + "[" +
                                        Conversion::toString(
                                            property.port2FirstBit() +
                                            property.width() - 1) +
                                        ":" +
                                        Conversion::toString(
                                            property.port2FirstBit()) +
                                        "]";
                                }
                            }
 
                            if (srcPort->direction() == OUT) {
                                stream << indentation(1) << "assign "
                                       << dstPortSignal << " = "
                                       << srcPortSignal << ";" << endl;
                            } else {
                                stream << indentation(1) << "assign "
                                       << srcPortSignal << " = "
                                       << dstPortSignal << ";" << endl;
                            }
                        }
                    }
                }
            }
        }
    }
 
    if (groundWidth_ > 0) {
        stream << indentation(1) << "assign "
               << GROUND_SIGNAL << " = {" << groundWidth_ <<"{1'b0}};"
               << endl;
    }
}

References assert, ProGe::BIT, AssocTools::containsKey(), ContainerTools::containsValue(), ProGe::NetlistPort::dataType(), ProGe::Netlist::descriptor(), ProGe::NetlistPort::direction(), GROUND_SIGNAL, groundWidth_, indentation(), ProGe::BaseNetlistBlock::netlist(), ProGe::OUT, ProGe::NetlistPort::parentBlock(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), portSignalName(), ProGe::BaseNetlistBlock::subBlock(), ProGe::BaseNetlistBlock::subBlockCount(), and Conversion::toString().

Referenced by writeBlock().

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◆ writeSignalDeclarations()

void ProGe::VerilogNetlistWriter::writeSignalDeclarations	(	const BaseNetlistBlock &	block,
		std::ofstream &	stream
	)

private

Writes the Verilog signal declarations to the given stream.

Parameters

block	The block of which the signals are written.
stream	The stream to write.

Definition at line 286 of file VerilogNetlistWriter.cc.

                                                        {
    // collect all the sub blocks to a set
    typedef std::set<const BaseNetlistBlock*, NetlistBlockNameComparator>
        BlockSet;
    BlockSet subBlocks;
    for (size_t i = 0; i < block.subBlockCount(); i++) {
        // ports belonging to virtual blocks have static values, thus they are
        // excluded
        if (!block.subBlock(i).isVirtual()) {
            subBlocks.insert(&block.subBlock(i));
        }
    }
 
    // create a signal for each port in the sub-blocks
    for (BlockSet::const_iterator iter = subBlocks.begin();
         iter != subBlocks.end(); iter++) {
        const BaseNetlistBlock* subBlock = *iter;
 
        for (size_t i = 0; i < subBlock->portCount(); i++) {
            const NetlistPort& port = subBlock->port(i);
 
            size_t vertexDescriptor = block.netlist().descriptor(port);
            std::pair<out_edge_iterator, out_edge_iterator> edges =
                boost::out_edges(vertexDescriptor, block.netlist());
 
            if (edges.first != edges.second) {
                edge_descriptor edgeDescriptor = *edges.first;
                vertex_descriptor dstVertex =
                    boost::target(edgeDescriptor, block.netlist());
                NetlistPort* dstPort = block.netlist()[dstVertex];
                if (&dstPort->parentBlock() != &block) {
                    stream << indentation(1) << "wire"
                           << portSignalType(port) << " "
                           << portSignalName(port) << ";" << endl;
                }
            } else if (!port.hasStaticValue()) {
                // assume the port is connected to ground if is is
                // unconnected in the netlist
                if (port.realWidthAvailable()) {
                    groundWidth_ = 
                        std::max(port.realWidth(), groundWidth_);
                }
                stream << indentation(1) << "wire"
                       << portSignalType(port) << " "
                       << portSignalName(port) << ";" << endl;
            }
        }
    }
    
    // create a ground signal
    if (groundWidth_ > 0) {
        stream << indentation(1) << "wire[" << groundWidth_ - 1 << ":0]"
               << GROUND_SIGNAL << ";" << endl;
    }
}

References ProGe::Netlist::descriptor(), GROUND_SIGNAL, groundWidth_, ProGe::NetlistPort::hasStaticValue(), indentation(), ProGe::BaseNetlistBlock::isVirtual(), ProGe::BaseNetlistBlock::netlist(), ProGe::NetlistPort::parentBlock(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), portSignalName(), portSignalType(), ProGe::NetlistPort::realWidth(), ProGe::NetlistPort::realWidthAvailable(), ProGe::BaseNetlistBlock::subBlock(), and ProGe::BaseNetlistBlock::subBlockCount().

Referenced by writeBlock().

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Member Data Documentation

◆ groundWidth_

int ProGe::VerilogNetlistWriter::groundWidth_

private

Width of the ground signal.

Definition at line 117 of file VerilogNetlistWriter.hh.

Referenced by writeSignalAssignments(), and writeSignalDeclarations().

The documentation for this class was generated from the following files:

Public Member Functions

Static Public Member Functions

Private Types

Private Member Functions

Static Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ edge_descriptor

◆ out_edge_iterator

◆ vertex_descriptor

Constructor & Destructor Documentation

◆ VerilogNetlistWriter()

◆ ~VerilogNetlistWriter()

Member Function Documentation

◆ directionString()

◆ generateIndentation()

◆ genericMapStringValue()

◆ indentation()

◆ isNumber()

◆ netlistParameterPkgName()

◆ portSignalName()

◆ portSignalType()

◆ write()

◆ writeBlock()

◆ writeComponentDeclarations()

◆ writeGenericDeclaration()

◆ writeNetlistParameterPackage()

◆ writePortDeclaration()

◆ writePortMappings()

◆ writeSignalAssignments()

◆ writeSignalDeclarations()

Member Data Documentation

◆ groundWidth_