#include <VhdlRomGenerator.hh>

Inheritance diagram for VhdlRomGenerator:

Collaboration diagram for VhdlRomGenerator:

Public Member Functions
	VhdlRomGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)

virtual	~VhdlRomGenerator ()

virtual bool	generatesComponentHdlFile () const

virtual std::vector< TCEString >	generateComponentFile (TCEString outputPath)

Public Member Functions inherited from MemoryGenerator
	MemoryGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)

virtual	~MemoryGenerator ()

virtual bool	isCompatible (const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const

virtual void	addMemory (const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)

int	memoryTotalWidth () const

int	memoryMauSize () const

int	memoryWidthInMaus () const

int	memoryAddrWidth () const

TCEString	initializationFile () const

void	addLsu (TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)

Protected Member Functions
virtual TCEString	moduleName () const

virtual TCEString	instanceName (int coreId, int memIndex) const

Protected Member Functions inherited from MemoryGenerator
virtual bool	checkFuPort (const std::string fuPort, std::vector< TCEString > &reasons) const

virtual void	connectPorts (ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)

virtual MemoryGenerator::BlockPair	createMemoryNetlistBlock (ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)

const PlatformIntegrator *	platformIntegrator () const

std::ostream &	warningStream ()

std::ostream &	errorStream ()

int	portCount () const

const HDLPort *	port (int index) const

const HDLPort *	portByKeyName (TCEString name) const

TCEString	portKeyName (const HDLPort *port) const

void	addPort (const TCEString &name, HDLPort *port)

int	parameterCount () const

const ProGe::Parameter &	parameter (int index) const

void	addParameter (const ProGe::Parameter &add)

TCEString	ttaCoreName () const

TCEString	memoryIndexString (int coreId, int memIndex) const

TCEString	templatePath () const

void	instantiateTemplate (const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const

bool	hasLSUArchitecture () const

const TTAMachine::FunctionUnit &	lsuArchitecture () const

TCEString	corePortName (const TCEString &portBaseName, int coreId) const

Private Member Functions
TCEString	imagePackageName () const

Additional Inherited Members
Protected Types inherited from MemoryGenerator
typedef std::multimap< TCEString, HDLPort * >	PortMap

typedef std::pair< ProGe::NetlistBlock , ProGe::VirtualNetlistBlock >	BlockPair

Detailed Description

Definition at line 42 of file VhdlRomGenerator.hh.

Constructor & Destructor Documentation

◆ VhdlRomGenerator()

VhdlRomGenerator::VhdlRomGenerator	(	int	memMauWidth,
		int	widthInMaus,
		int	addrWidth,
		TCEString	initFile,
		const PlatformIntegrator *	integrator,
		std::ostream &	warningStream,
		std::ostream &	errorStream
	)

Definition at line 50 of file VhdlRomGenerator.cc.

                            : 
        MemoryGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
            integrator, warningStream, errorStream) {
 
    addPort("clk", new HDLPort("clock", "1", ProGe::BIT, ProGe::IN, false, 1));
    addPort("imem_addr", new HDLPort("addr", "addrw", ProGe::BIT_VECTOR,
        ProGe::IN, false, memoryAddrWidth()));
 
    addPort("imem_en_x", new HDLPort("en_x", "1", ProGe::BIT,
        ProGe::IN, false, 1));
 
    addPort("imem_data", new HDLPort("dataout", "instrw", ProGe::BIT_VECTOR,
        ProGe::OUT, false, memoryTotalWidth()));
 
    HDLPort* busyToGnd = new HDLPort("wait", "1", ProGe::BIT, ProGe::OUT,
        false, 1);
    busyToGnd->setToStatic(ProGe::StaticSignal::GND);
    addPort("busy", busyToGnd);
 
    ProGe::Parameter addr("addrw", "integer", "IMEMADDRWIDTH");
    ProGe::Parameter data("instrw", "integer", "IMEMMAUWIDTH*IMEMWIDTHINMAUS");
    
    addParameter(addr);
    addParameter(data);
}

References MemoryGenerator::addParameter(), MemoryGenerator::addPort(), ProGe::BIT, ProGe::BIT_VECTOR, ProGe::StaticSignal::GND, ProGe::IN, MemoryGenerator::memoryAddrWidth(), MemoryGenerator::memoryTotalWidth(), ProGe::OUT, and HDLPort::setToStatic().

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◆ ~VhdlRomGenerator()

VhdlRomGenerator::~VhdlRomGenerator ( )

virtual

Definition at line 83 of file VhdlRomGenerator.cc.

83 {

84}

Member Function Documentation

◆ generateComponentFile()

std::vector< TCEString > VhdlRomGenerator::generateComponentFile ( TCEString outputPath )

virtual

Implements MemoryGenerator.

Definition at line 94 of file VhdlRomGenerator.cc.

                                                            {
 
    TCEString outputFile =
        outputPath << FileSystem::DIRECTORY_SEPARATOR << moduleName() 
                   << ".vhd";
 
    std::ofstream file;
    file.open(outputFile.c_str());
    if (!file) {
        TCEString msg = "Couldn't open file " + outputFile + " for writing";
        IOException exc(__FILE__, __LINE__, "VhdlRomGenerator", msg);
        throw exc;
    }
    
    TCEString indentL1 = StringTools::indent(1);
    TCEString indentL2 = StringTools::indent(2);
    std::ostringstream stream;
    stream
        << "library ieee;" << endl
        << "use ieee.std_logic_1164.all;" << endl
        << "use ieee.std_logic_arith.all;" << endl
        << "use work." << imagePackageName() << ".all;" << endl << endl
        << "entity " << moduleName() << " is" << endl << endl
        << indentL1 << "generic (" << endl
        << indentL2 << "addrw  : integer := 10;" << endl
        << indentL2 << "instrw : integer := 100);" << endl
        << indentL1 << "port (" << endl
        << indentL2 << "clock   : in  std_logic;" << endl
        << indentL2 << "en_x    : in std_logic; -- not used" << endl
        << indentL2 << "addr    : in  std_logic_vector(addrw-1 downto 0);"
        << endl << indentL2
        << "dataout : out std_logic_vector(instrw-1 downto 0));" << endl
        << "end " << moduleName() << ";" << endl << endl;
 
    stream
        << "architecture rtl of " << moduleName() << " is" << endl << endl
        << indentL1
        << "subtype imem_index is integer range 0 to imem_array'length-1;"
        << endl 
        << indentL1 << "constant imem : std_logic_imem_matrix"
        << "(0 to imem_array'length-1) := imem_array;" << endl
        << indentL1 << "signal en_x_dummy : std_logic;" << endl << endl
        << "begin --rtl" << endl << endl
        << indentL1 << "process" << endl
        << indentL2 << "variable imem_line : imem_index;" << endl
        << indentL1 << "begin -- process" << endl
        << indentL2 << "wait until clock'event and clock='1';" << endl
        << indentL2 << "imem_line := conv_integer(unsigned(addr));" << endl
        << indentL2 << "dataout <= imem(imem_line);" << endl
        << indentL1 << "end process;" << endl << endl
        << indentL1 << "en_x_dummy <= en_x; -- dummy connection" << endl
        << endl << "end rtl;" << endl;
 
    file << stream.str();
    file.close();
 
    std::vector<TCEString> componentFiles;
    componentFiles.push_back(outputFile);
    componentFiles.push_back(initializationFile());
    return componentFiles;
} 

References FileSystem::DIRECTORY_SEPARATOR, imagePackageName(), StringTools::indent(), MemoryGenerator::initializationFile(), and moduleName().

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◆ generatesComponentHdlFile()

bool VhdlRomGenerator::generatesComponentHdlFile ( ) const

virtual

Implements MemoryGenerator.

Definition at line 88 of file VhdlRomGenerator.cc.

                                                  {
    return true;
}

◆ imagePackageName()

TCEString VhdlRomGenerator::imagePackageName ( ) const

private

Definition at line 172 of file VhdlRomGenerator.cc.

                                         {
 
    return ttaCoreName() + "_imem_image";
}

References MemoryGenerator::ttaCoreName().

Referenced by generateComponentFile().

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◆ instanceName()

TCEString VhdlRomGenerator::instanceName	(	int	coreId,
		int	memIndex
	)		const

protectedvirtual

Implements MemoryGenerator.

Definition at line 165 of file VhdlRomGenerator.cc.

                                                             {
 
    TCEString iname("imem_array_instance_");
    return iname << memoryIndexString(coreId, memIndex);
}

References MemoryGenerator::memoryIndexString().

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◆ moduleName()

TCEString VhdlRomGenerator::moduleName ( ) const

protectedvirtual

Implements MemoryGenerator.

Definition at line 158 of file VhdlRomGenerator.cc.

                                   {
 
    return ttaCoreName() + "_rom_array_comp";
}

References MemoryGenerator::ttaCoreName().

Referenced by generateComponentFile().

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The documentation for this class was generated from the following files:

Public Member Functions

Protected Member Functions

Private Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ VhdlRomGenerator()

◆ ~VhdlRomGenerator()

Member Function Documentation

◆ generateComponentFile()

◆ generatesComponentHdlFile()

◆ imagePackageName()

◆ instanceName()

◆ moduleName()