OpenASIP 2.2
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Public Member Functions | Protected Types | Protected Member Functions | Private Types | Private Attributes | Static Private Attributes | List of all members
MemoryGenerator Class Referenceabstract

#include <MemoryGenerator.hh>

Inheritance diagram for MemoryGenerator:
Inheritance graph
Collaboration diagram for MemoryGenerator:
Collaboration graph

Public Member Functions

 MemoryGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
 
virtual ~MemoryGenerator ()
 
virtual bool isCompatible (const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const
 
virtual void addMemory (const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
 
virtual bool generatesComponentHdlFile () const =0
 
virtual std::vector< TCEStringgenerateComponentFile (TCEString outputPath)=0
 
int memoryTotalWidth () const
 
int memoryMauSize () const
 
int memoryWidthInMaus () const
 
int memoryAddrWidth () const
 
TCEString initializationFile () const
 
void addLsu (TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
 

Protected Types

typedef std::multimap< TCEString, HDLPort * > PortMap
 
typedef std::pair< ProGe::NetlistBlock *, ProGe::VirtualNetlistBlock * > BlockPair
 

Protected Member Functions

virtual bool checkFuPort (const std::string fuPort, std::vector< TCEString > &reasons) const
 
virtual void connectPorts (ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)
 
virtual MemoryGenerator::BlockPair createMemoryNetlistBlock (ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
 
const PlatformIntegratorplatformIntegrator () const
 
std::ostream & warningStream ()
 
std::ostream & errorStream ()
 
int portCount () const
 
const HDLPortport (int index) const
 
const HDLPortportByKeyName (TCEString name) const
 
TCEString portKeyName (const HDLPort *port) const
 
void addPort (const TCEString &name, HDLPort *port)
 
int parameterCount () const
 
const ProGe::Parameterparameter (int index) const
 
void addParameter (const ProGe::Parameter &add)
 
TCEString ttaCoreName () const
 
virtual TCEString moduleName () const =0
 
virtual TCEString instanceName (int coreId, int memIndex) const =0
 
TCEString memoryIndexString (int coreId, int memIndex) const
 
TCEString templatePath () const
 
void instantiateTemplate (const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const
 
bool hasLSUArchitecture () const
 
const TTAMachine::FunctionUnitlsuArchitecture () const
 
TCEString corePortName (const TCEString &portBaseName, int coreId) const
 

Private Types

typedef std::vector< ProGe::ParameterParameterList
 

Private Attributes

int mauWidth_
 
int widthInMaus_
 
int addrWidth_
 
TCEString initFile_
 
const PlatformIntegratorintegrator_
 
std::ostream & warningStream_
 
std::ostream & errorStream_
 
PortMap memPorts_
 
ParameterList params_
 
TTAMachine::FunctionUnitlsuArch_
 
std::vector< std::string > lsuPorts_
 

Static Private Attributes

static const TCEString CLOCK_PORT = "clk"
 
static const TCEString RESET_PORT = "rstx"
 

Detailed Description

Definition at line 85 of file MemoryGenerator.hh.

Member Typedef Documentation

◆ BlockPair

Definition at line 148 of file MemoryGenerator.hh.

◆ ParameterList

typedef std::vector<ProGe::Parameter> MemoryGenerator::ParameterList
private

Definition at line 215 of file MemoryGenerator.hh.

◆ PortMap

typedef std::multimap<TCEString, HDLPort*> MemoryGenerator::PortMap
protected

Definition at line 145 of file MemoryGenerator.hh.

Constructor & Destructor Documentation

◆ MemoryGenerator()

MemoryGenerator::MemoryGenerator ( int  memMauWidth,
int  widthInMaus,
int  addrWidth,
TCEString  initFile,
const PlatformIntegrator integrator,
std::ostream &  warningStream,
std::ostream &  errorStream 
)

Definition at line 59 of file MemoryGenerator.cc.

63 : mauWidth_(mauWidth),
64 widthInMaus_(widthInMaus),
65 addrWidth_(addrWidth),
66 initFile_(initFile),
67 integrator_(integrator),
70 lsuArch_(NULL),
71 lsuPorts_() {}
TTAMachine::FunctionUnit * lsuArch_
std::ostream & warningStream()
std::ostream & errorStream_
std::vector< std::string > lsuPorts_
const PlatformIntegrator * integrator_
std::ostream & warningStream_
std::ostream & errorStream()

◆ ~MemoryGenerator()

MemoryGenerator::~MemoryGenerator ( )
virtual

Definition at line 73 of file MemoryGenerator.cc.

73 {
74
75 for (PortMap::iterator i = memPorts_.begin(); i != memPorts_.end(); i++) {
76 if (i->second != NULL)
77 delete i->second;
78 }
79}

References memPorts_.

Member Function Documentation

◆ addLsu()

void MemoryGenerator::addLsu ( TTAMachine::FunctionUnit lsuArch,
std::vector< std::string >  lsuPorts 
)

For data memories

Definition at line 376 of file MemoryGenerator.cc.

377 {
378 lsuArch_ = &lsuArch;
379 lsuPorts_ = lsuPorts;
380}

References lsuArch_, and lsuPorts_.

Referenced by AlmaIFIntegrator::dmemInstance(), AlteraIntegrator::dmemInstance(), KoskiIntegrator::dmemInstance(), and Stratix2DSPBoardIntegrator::dmemInstance().

◆ addMemory()

void MemoryGenerator::addMemory ( const ProGe::NetlistBlock ttaCore,
ProGe::NetlistBlock integratorBlock,
int  memIndex,
int  coreId 
)
virtual

Reimplemented in DummyMemGenerator, AlteraMemGenerator, AlteraOnchipRomGenerator, Stratix2SramGenerator, and XilinxBlockRamGenerator.

Definition at line 119 of file MemoryGenerator.cc.

121 {
122 BlockPair blocks =
123 createMemoryNetlistBlock(integratorBlock, memIndex, coreId);
124 NetlistBlock* mem = blocks.first;
125 VirtualNetlistBlock* virt = blocks.second;
126 assert(mem != NULL);
127 assert(virt != NULL);
128 if (virt->portCount() > 0) {
129 integratorBlock.addSubBlock(virt);
130 }
131
132 for (int i = 0; i < portCount(); i++) {
133 const HDLPort* hdlPort = port(i);
134 NetlistPort* memPort = mem->port(hdlPort->name());
135 if (memPort == NULL) {
136 memPort = virt->port(hdlPort->name());
137 if (memPort == NULL) {
138 TCEString msg = "Port ";
139 msg << hdlPort->name() << " not found from netlist block";
140 throw InvalidData(__FILE__, __LINE__, "MemoryGenerator", msg);
141 }
142 }
143
144 TCEString portName = corePortName(portKeyName(hdlPort), coreId);
145 const NetlistPort* corePort = NULL;
146 // clock and reset must be connected to new toplevel ports
147 if (portName == platformIntegrator()->clockPort()->name()) {
148 corePort = platformIntegrator()->clockPort();
149 } else if (portName == platformIntegrator()->resetPort()->name()) {
150 corePort = platformIntegrator()->resetPort();
151 } else {
152 corePort = ttaCore.port(portName);
153 }
154 assert(corePort != NULL);
155
157 integratorBlock, *memPort, *corePort, hdlPort->needsInversion(),
158 coreId);
159 }
160}
#define assert(condition)
TCEString name() const
Definition HDLPort.cc:87
bool needsInversion() const
Definition HDLPort.cc:122
TCEString portKeyName(const HDLPort *port) const
const PlatformIntegrator * platformIntegrator() const
const HDLPort * port(int index) const
std::pair< ProGe::NetlistBlock *, ProGe::VirtualNetlistBlock * > BlockPair
virtual void connectPorts(ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)
TCEString corePortName(const TCEString &portBaseName, int coreId) const
int portCount() const
virtual MemoryGenerator::BlockPair createMemoryNetlistBlock(ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
ProGe::NetlistPort * resetPort() const
ProGe::NetlistPort * clockPort() const
void addSubBlock(BaseNetlistBlock *subBlock, const std::string &instanceName="")
virtual NetlistPort * port(const std::string &portName, bool partialMatch=true)
virtual size_t portCount() const

References ProGe::NetlistBlock::addSubBlock(), assert, PlatformIntegrator::clockPort(), connectPorts(), corePortName(), createMemoryNetlistBlock(), HDLPort::name(), HDLPort::needsInversion(), platformIntegrator(), ProGe::NetlistBlock::port(), port(), portCount(), ProGe::NetlistBlock::portCount(), portKeyName(), and PlatformIntegrator::resetPort().

Referenced by AlteraMemGenerator::addMemory(), AlteraOnchipRomGenerator::addMemory(), and PlatformIntegrator::generateMemory().

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◆ addParameter()

void MemoryGenerator::addParameter ( const ProGe::Parameter add)
protected

Definition at line 313 of file MemoryGenerator.cc.

313 {
314 ProGe::Parameter toAdd(add.name(), add.type(), add.value());
315 params_.push_back(toAdd);
316}
ParameterList params_
const TCEString & value() const
Definition Parameter.cc:143
const TCEString & type() const
Definition Parameter.cc:138
const TCEString & name() const
Definition Parameter.cc:133

References ProGe::Parameter::name(), params_, ProGe::Parameter::type(), and ProGe::Parameter::value().

Referenced by AlteraMemGenerator::addGenerics(), Stratix2SramGenerator::Stratix2SramGenerator(), VhdlRomGenerator::VhdlRomGenerator(), and XilinxBlockRamGenerator::XilinxBlockRamGenerator().

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◆ addPort()

void MemoryGenerator::addPort ( const TCEString name,
HDLPort port 
)
protected

◆ checkFuPort()

bool MemoryGenerator::checkFuPort ( const std::string  fuPort,
std::vector< TCEString > &  reasons 
) const
protectedvirtual

Reimplemented in AlteraHibiDpRamGenerator, and DummyMemGenerator.

Definition at line 106 of file MemoryGenerator.cc.

107 {
108 PortMap::const_iterator iter = memPorts_.find(fuPort);
109 if (iter == memPorts_.end()) {
110 TCEString msg;
111 msg << "MemoryGenerator does not have port " << fuPort;
112 reasons.push_back(msg);
113 return false;
114 }
115 return true;
116}

References memPorts_.

Referenced by AlteraHibiDpRamGenerator::checkFuPort(), and isCompatible().

◆ connectPorts()

void MemoryGenerator::connectPorts ( ProGe::NetlistBlock netlistBlock,
const ProGe::NetlistPort memPort,
const ProGe::NetlistPort corePort,
bool  inverted,
int  coreId 
)
protectedvirtual

Reimplemented in AlteraHibiDpRamGenerator.

Definition at line 392 of file MemoryGenerator.cc.

394 {
395 if (inverted) {
396 ProGe::InverterBlock* InvertedBlock =
397 new ProGe::InverterBlock(corePort, memPort);
398 netlistBlock.addSubBlock(InvertedBlock);
399
400 netlistBlock.netlist().connect(
401 corePort, InvertedBlock->inputPort(), 0, 0, 1);
402 netlistBlock.netlist().connect(
403 InvertedBlock->outputPort(), memPort, 0, 0, 1);
404
405 } else {
406 if (memPort.dataType() == corePort.dataType()) {
407 netlistBlock.netlist().connect(memPort, corePort);
408 } else {
409 // bit to bit vector connection, connect lowest bits
410 netlistBlock.netlist().connect(memPort, corePort, 0, 0, 1);
411 }
412 }
413}
const NetlistPort & outputPort() const
const NetlistPort & inputPort() const
virtual const Netlist & netlist() const
DataType dataType() const
bool connect(const NetlistPort &port1, const NetlistPort &port2, int port1FirstBit, int port2FirstBit, int width=1)
Definition Netlist.cc:83

References ProGe::NetlistBlock::addSubBlock(), ProGe::Netlist::connect(), ProGe::NetlistPort::dataType(), ProGe::InverterBlock::inputPort(), ProGe::NetlistBlock::netlist(), and ProGe::InverterBlock::outputPort().

Referenced by addMemory(), Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), and AlteraHibiDpRamGenerator::connectPorts().

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◆ corePortName()

TCEString MemoryGenerator::corePortName ( const TCEString portBaseName,
int  coreId 
) const
protected

Definition at line 356 of file MemoryGenerator.cc.

357 {
358 // clock and reset port names are global
359 if (portBaseName == integrator_->clockPort()->name() ||
360 portBaseName == integrator_->resetPort()->name()) {
361 return portBaseName;
362 }
363
364 TCEString portName;
365 if (coreId >= 0) {
366 portName << "core" << coreId << "_";
367 }
368 if (lsuArch_ != NULL) {
369 portName << "fu_" << lsuArchitecture().name() << "_";
370 }
371 portName << portBaseName;
372 return portName;
373}
const TTAMachine::FunctionUnit & lsuArchitecture() const
std::string name() const
virtual TCEString name() const

References PlatformIntegrator::clockPort(), integrator_, lsuArch_, lsuArchitecture(), ProGe::NetlistPort::name(), TTAMachine::Component::name(), and PlatformIntegrator::resetPort().

Referenced by addMemory(), Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), and isCompatible().

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◆ createMemoryNetlistBlock()

MemoryGenerator::BlockPair MemoryGenerator::createMemoryNetlistBlock ( ProGe::NetlistBlock integratorBlock,
int  memIndex,
int  coreId 
)
protectedvirtual

Definition at line 163 of file MemoryGenerator.cc.

164 {
165 VirtualNetlistBlock* staticConnectionsBlock = new VirtualNetlistBlock(
166 moduleName() + "_virt", instanceName(coreId, memIndex) + "_virt");
167
168 NetlistBlock* mem =
169 new NetlistBlock(moduleName(), instanceName(coreId, memIndex));
170 integratorBlock.addSubBlock(mem);
171
172 for (int i = 0; i < parameterCount(); i++) {
173 mem->setParameter(parameter(i));
174 }
175 for (int i = 0; i < portCount(); i++) {
176 const HDLPort* hdlPort = port(i);
177 NetlistPort* memPort = NULL;
178 if (hdlPort->hasStaticValue()) {
179 memPort = hdlPort->convertToNetlistPort(*staticConnectionsBlock);
180 } else {
181 memPort = hdlPort->convertToNetlistPort(*mem);
182 }
183 assert(memPort != NULL);
184 }
185
186 BlockPair blocks;
187 blocks.first = mem;
188 blocks.second = staticConnectionsBlock;
189 return blocks;
190}
bool hasStaticValue() const
Definition HDLPort.cc:153
ProGe::NetlistPort * convertToNetlistPort(ProGe::NetlistBlock &block) const
Definition HDLPort.cc:127
const ProGe::Parameter & parameter(int index) const
virtual TCEString instanceName(int coreId, int memIndex) const =0
virtual TCEString moduleName() const =0
int parameterCount() const
void setParameter(const std::string &name, const std::string &type, const std::string &value)

References ProGe::NetlistBlock::addSubBlock(), assert, HDLPort::convertToNetlistPort(), HDLPort::hasStaticValue(), instanceName(), moduleName(), parameter(), parameterCount(), port(), portCount(), and ProGe::NetlistBlock::setParameter().

Referenced by addMemory(), and XilinxBlockRamGenerator::addMemory().

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◆ errorStream()

std::ostream & MemoryGenerator::errorStream ( )
protected

Definition at line 237 of file MemoryGenerator.cc.

237 {
238
239 return errorStream_;
240}

References errorStream_.

◆ generateComponentFile()

virtual std::vector< TCEString > MemoryGenerator::generateComponentFile ( TCEString  outputPath)
pure virtual

◆ generatesComponentHdlFile()

virtual bool MemoryGenerator::generatesComponentHdlFile ( ) const
pure virtual

◆ hasLSUArchitecture()

bool MemoryGenerator::hasLSUArchitecture ( ) const
protected

Definition at line 344 of file MemoryGenerator.cc.

344 {
345 return lsuArch_ != NULL;
346}

References lsuArch_.

◆ initializationFile()

TCEString MemoryGenerator::initializationFile ( ) const

Definition at line 219 of file MemoryGenerator.cc.

219 {
220
221 return initFile_;
222}

References initFile_.

Referenced by AlteraMemGenerator::addGenerics(), and VhdlRomGenerator::generateComponentFile().

◆ instanceName()

virtual TCEString MemoryGenerator::instanceName ( int  coreId,
int  memIndex 
) const
protectedpure virtual

◆ instantiateTemplate()

void MemoryGenerator::instantiateTemplate ( const TCEString inFile,
const TCEString outFile,
const TCEString entity 
) const
protected

Definition at line 333 of file MemoryGenerator.cc.

336 {
337
339 inst.setEntityString(entity);
340 inst.instantiateTemplateFile(inFile, outFile);
341}
void instantiateTemplateFile(const std::string &templateFile, const std::string &dstFile)
void setEntityString(const TCEString &entityStr)

References HDLTemplateInstantiator::instantiateTemplateFile(), and HDLTemplateInstantiator::setEntityString().

Referenced by AlteraMemGenerator::instantiateAlteraTemplate().

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◆ isCompatible()

bool MemoryGenerator::isCompatible ( const ProGe::NetlistBlock ttaCore,
int  coreId,
std::vector< TCEString > &  reasons 
) const
virtual

Tests that the memory generator is compatible with TTA core. If incompatible, reasons are appended to the reasons vector

Parameters
ttaCoreTTA toplevel
coreIdThe core ID number
reasonsReasons why incompatible
Returns
is memory generator compatible with the TTA core

Reimplemented in XilinxBlockRamGenerator.

Definition at line 82 of file MemoryGenerator.cc.

84 {
85 for (std::string port : lsuPorts_) {
86 if (!checkFuPort(port, reasons)) {
87 return false;
88 }
89 }
90 bool foundAll = true;
91 PortMap::const_iterator iter = memPorts_.begin();
92 while (iter != memPorts_.end()) {
93 TCEString corePort = corePortName(iter->first, coreId);
94 if (ttaCore.port(corePort) == NULL) {
95 TCEString message = "Couldn't find port " + corePort +
96 " from toplevel";
97 reasons.push_back(message);
98 foundAll = false;
99 }
100 iter++;
101 }
102 return foundAll;
103}
virtual bool checkFuPort(const std::string fuPort, std::vector< TCEString > &reasons) const

References checkFuPort(), corePortName(), lsuPorts_, memPorts_, ProGe::NetlistBlock::port(), and port().

Referenced by PlatformIntegrator::generateMemory(), and XilinxBlockRamGenerator::isCompatible().

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◆ lsuArchitecture()

const TTAMachine::FunctionUnit & MemoryGenerator::lsuArchitecture ( ) const
protected

Definition at line 349 of file MemoryGenerator.cc.

349 {
350
351 assert(lsuArch_ != NULL);
352 return *lsuArch_;
353}

References assert, and lsuArch_.

Referenced by corePortName().

◆ memoryAddrWidth()

int MemoryGenerator::memoryAddrWidth ( ) const

◆ memoryIndexString()

TCEString MemoryGenerator::memoryIndexString ( int  coreId,
int  memIndex 
) const
protected

Definition at line 383 of file MemoryGenerator.cc.

383 {
384 TCEString index;
385 if (coreId >= 0) {
386 index << coreId << "_";
387 }
388 return index << memIndex;
389}

Referenced by AlteraHibiDpRamGenerator::instanceName(), AlteraOnchipRamGenerator::instanceName(), AlteraOnchipRomGenerator::instanceName(), Stratix2SramGenerator::instanceName(), and VhdlRomGenerator::instanceName().

◆ memoryMauSize()

int MemoryGenerator::memoryMauSize ( ) const

Definition at line 199 of file MemoryGenerator.cc.

199 {
200
201 return mauWidth_;
202}

References mauWidth_.

◆ memoryTotalWidth()

int MemoryGenerator::memoryTotalWidth ( ) const

◆ memoryWidthInMaus()

int MemoryGenerator::memoryWidthInMaus ( ) const

◆ moduleName()

virtual TCEString MemoryGenerator::moduleName ( ) const
protectedpure virtual

◆ parameter()

const ProGe::Parameter & MemoryGenerator::parameter ( int  index) const
protected

Definition at line 308 of file MemoryGenerator.cc.

308 {
309 return params_.at(index);
310}

References params_.

Referenced by Stratix2SramGenerator::addMemory(), and createMemoryNetlistBlock().

◆ parameterCount()

int MemoryGenerator::parameterCount ( ) const
protected

Definition at line 302 of file MemoryGenerator.cc.

302 {
303
304 return params_.size();
305}

References params_.

Referenced by Stratix2SramGenerator::addMemory(), and createMemoryNetlistBlock().

◆ platformIntegrator()

const PlatformIntegrator * MemoryGenerator::platformIntegrator ( ) const
protected

◆ port()

const HDLPort * MemoryGenerator::port ( int  index) const
protected

Definition at line 249 of file MemoryGenerator.cc.

249 {
250
251 if (index > static_cast<int>(memPorts_.size())) {
252 TCEString message = "Index out of range";
253 throw OutOfRange(__FILE__, __LINE__, "MemoryGenerator", message);
254 }
255 PortMap::const_iterator iter = memPorts_.begin();
256 for (int i = 0; i < index; i++) {
257 iter++;
258 }
259 return iter->second;
260}

References memPorts_.

Referenced by addMemory(), Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), addPort(), createMemoryNetlistBlock(), isCompatible(), and portKeyName().

◆ portByKeyName()

const HDLPort * MemoryGenerator::portByKeyName ( TCEString  name) const
protected

Definition at line 264 of file MemoryGenerator.cc.

264 {
265
266 if (memPorts_.find(name) == memPorts_.end()) {
267 TCEString message = "Port " + name + " not found";
268 throw KeyNotFound(__FILE__, __LINE__, "MemoryGenerator", message);
269 }
270 return memPorts_.find(name)->second;
271}

References memPorts_.

◆ portCount()

int MemoryGenerator::portCount ( ) const
protected

Definition at line 243 of file MemoryGenerator.cc.

243 {
244
245 return memPorts_.size();
246}

References memPorts_.

Referenced by addMemory(), Stratix2SramGenerator::addMemory(), XilinxBlockRamGenerator::addMemory(), and createMemoryNetlistBlock().

◆ portKeyName()

TCEString MemoryGenerator::portKeyName ( const HDLPort port) const
protected

Definition at line 275 of file MemoryGenerator.cc.

275 {
276
277 TCEString name = "";
278 PortMap::const_iterator iter = memPorts_.begin();
279 while (iter != memPorts_.end()) {
280 if (iter->second == port) {
281 name = iter->first;
282 break;
283 }
284 iter++;
285 }
286 if (name.empty()) {
287 TCEString message = "Key for port " + port->name() + " not found";
288 throw KeyNotFound(__FILE__, __LINE__, "MemoryGenerator", message);
289 }
290 return name;
291}

References memPorts_, HDLPort::name(), and port().

Referenced by addMemory(), Stratix2SramGenerator::addMemory(), and XilinxBlockRamGenerator::addMemory().

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◆ templatePath()

TCEString MemoryGenerator::templatePath ( ) const
protected

Returns base path to template files.

Definition at line 325 of file MemoryGenerator.cc.

325 {
326
327 TCEString path = Environment::dataDirPath("ProGe");
328 path << FileSystem::DIRECTORY_SEPARATOR << "platform";
329 return path;
330}
static std::string dataDirPath(const std::string &prog)
static const std::string DIRECTORY_SEPARATOR

References Environment::dataDirPath(), and FileSystem::DIRECTORY_SEPARATOR.

Referenced by XilinxBlockRamGenerator::generateComponentFile(), and AlteraMemGenerator::instantiateAlteraTemplate().

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◆ ttaCoreName()

TCEString MemoryGenerator::ttaCoreName ( ) const
protected

◆ warningStream()

std::ostream & MemoryGenerator::warningStream ( )
protected

Definition at line 231 of file MemoryGenerator.cc.

231 {
232
233 return warningStream_;
234}

References warningStream_.

Member Data Documentation

◆ addrWidth_

int MemoryGenerator::addrWidth_
private

Definition at line 219 of file MemoryGenerator.hh.

Referenced by memoryAddrWidth().

◆ CLOCK_PORT

const TCEString MemoryGenerator::CLOCK_PORT = "clk"
staticprivate

Definition at line 234 of file MemoryGenerator.hh.

◆ errorStream_

std::ostream& MemoryGenerator::errorStream_
private

Definition at line 226 of file MemoryGenerator.hh.

Referenced by errorStream().

◆ initFile_

TCEString MemoryGenerator::initFile_
private

Definition at line 221 of file MemoryGenerator.hh.

Referenced by initializationFile().

◆ integrator_

const PlatformIntegrator* MemoryGenerator::integrator_
private

Definition at line 223 of file MemoryGenerator.hh.

Referenced by corePortName(), and platformIntegrator().

◆ lsuArch_

TTAMachine::FunctionUnit* MemoryGenerator::lsuArch_
private

Definition at line 231 of file MemoryGenerator.hh.

Referenced by addLsu(), corePortName(), hasLSUArchitecture(), and lsuArchitecture().

◆ lsuPorts_

std::vector<std::string> MemoryGenerator::lsuPorts_
private

Definition at line 232 of file MemoryGenerator.hh.

Referenced by addLsu(), and isCompatible().

◆ mauWidth_

int MemoryGenerator::mauWidth_
private

Definition at line 217 of file MemoryGenerator.hh.

Referenced by memoryMauSize(), and memoryTotalWidth().

◆ memPorts_

PortMap MemoryGenerator::memPorts_
private

◆ params_

ParameterList MemoryGenerator::params_
private

Definition at line 229 of file MemoryGenerator.hh.

Referenced by addParameter(), parameter(), and parameterCount().

◆ RESET_PORT

const TCEString MemoryGenerator::RESET_PORT = "rstx"
staticprivate

Definition at line 235 of file MemoryGenerator.hh.

◆ warningStream_

std::ostream& MemoryGenerator::warningStream_
private

Definition at line 225 of file MemoryGenerator.hh.

Referenced by warningStream().

◆ widthInMaus_

int MemoryGenerator::widthInMaus_
private

Definition at line 218 of file MemoryGenerator.hh.

Referenced by memoryTotalWidth(), and memoryWidthInMaus().


The documentation for this class was generated from the following files: