AlteraOnchipRamGenerator.cc

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/*
    Copyright (c) 2002-2010 Tampere University.
 
    This file is part of TTA-Based Codesign Environment (TCE).
 
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/**
 * @file AlteraOnchipRamGenerator.cc
 *
 * Implementation of AlteraOnchipRamGenerator class.
 *
 * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
 * @note rating: red
 */
 
#include <iostream>
#include <vector>
#include "AlteraOnchipRamGenerator.hh"
#include "Netlist.hh"
#include "HDLPort.hh"
using std::endl;
 
const TCEString AlteraOnchipRamGenerator::COMPONENT_FILE = 
    "altera_onchip_ram_comp.vhd";
 
AlteraOnchipRamGenerator::AlteraOnchipRamGenerator(
    int memMauWidth,
    int widthInMaus,
    int addrWidth,
    TCEString initFile,
    const PlatformIntegrator* integrator,
    std::ostream& warningStream,
    std::ostream& errorStream): 
    AlteraMemGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
                       integrator, warningStream, errorStream) {
    
    bool inverted = true;
    bool noInvert = false;
    TCEString byteEnableWidth;
    byteEnableWidth << DATAW_G << "/8";
    addPort("dmem_data_in", 
        new HDLPort("q", DATAW_G,
            ProGe::BIT_VECTOR, ProGe::OUT, noInvert,
            memoryTotalWidth()));
    addPort("dmem_data_out",
        new HDLPort("data", DATAW_G,
            ProGe::BIT_VECTOR, ProGe::IN, noInvert,
            memoryTotalWidth()));
    addPort("dmem_addr",
        new HDLPort("address", ADDRW_G,
            ProGe::BIT_VECTOR, ProGe::IN, noInvert,
            memoryAddrWidth()));
    addPort("dmem_mem_en_x",
        new HDLPort("clken", "1", ProGe::BIT, ProGe::IN, inverted, 1));
    addPort("dmem_wr_en_x",
        new HDLPort("wren", "1", ProGe::BIT, ProGe::IN, inverted, 1));
    addPort("dmem_bytemask",
        new HDLPort("byteena", byteEnableWidth, ProGe::BIT_VECTOR,
            ProGe::IN, noInvert, memoryWidthInMaus()));
    addPort("clk",
        new HDLPort("clock", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
}
 
AlteraOnchipRamGenerator::~AlteraOnchipRamGenerator() {
}
 
bool
AlteraOnchipRamGenerator::generatesComponentHdlFile() const {
    return true;
}
 
 
std::vector<TCEString>
AlteraOnchipRamGenerator::generateComponentFile(TCEString outputPath) {
 
    return instantiateAlteraTemplate(COMPONENT_FILE, outputPath);
}
 
 
TCEString
AlteraOnchipRamGenerator::moduleName() const {
 
    return ttaCoreName() + "_altera_onchip_ram_comp";
}
    
 
TCEString
AlteraOnchipRamGenerator::instanceName(int coreId, int memIndex) const {
    
    TCEString iname("onchip_dmem_");
    return iname << memoryIndexString(coreId, memIndex);
}