OpenASIP
2.0
src
applibs
ProGe
SinglePortSSRAMBlock.hh
Go to the documentation of this file.
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/*
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Copyright (c) 2002-2015 Tampere University.
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This file is part of TTA-Based Codesign Environment (TCE).
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*/
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/*
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* @file SinglePortSSRAMBlock.hh
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*
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* Declaration of SinglePortSSRAMBlock class.
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*
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* Created on: 8.9.2015
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* @author Henry Linjamäki 2015 (henry.linjamaki-no.spam-tut.fi)
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* @note rating: red
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*/
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#ifndef SINGLEPORTSSRAMBLOCK_HH
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#define SINGLEPORTSSRAMBLOCK_HH
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#include <string>
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#include "
BaseNetlistBlock.hh
"
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namespace
ProGe
{
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/*
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* Netlist block of single port synchronous SRAM.
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*/
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class
SinglePortSSRAMBlock
:
public
BaseNetlistBlock
{
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public
:
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SinglePortSSRAMBlock
() =
delete
;
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SinglePortSSRAMBlock
(
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const
std::string& addressWidth,
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const
std::string& dataWidth,
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const
std::string& initFile,
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bool
isForSimulation =
true
);
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virtual
~SinglePortSSRAMBlock
();
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void
setAccessTraceFile
(
const
std::string filename);
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const
NetlistPortGroup
&
memoryPort
()
const
;
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virtual
void
write
(
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const
Path
& targetBaseDir,
HDL
targetLang =
VHDL
)
const override
;
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private
:
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NetlistPortGroup
*
memoryPortGroup_
=
nullptr
;
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bool
isForSimulation_
=
true
;
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};
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}
/* namespace ProGe */
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#endif
/* SINGLEPORTSSRAMBLOCK_HH */
ProGe::SinglePortSSRAMBlock::write
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const override
Definition:
SinglePortSSRAMBlock.cc:103
ProGe::BaseNetlistBlock
Definition:
BaseNetlistBlock.hh:59
Path
Definition:
FileSystem.hh:197
ProGe::SinglePortSSRAMBlock
Definition:
SinglePortSSRAMBlock.hh:46
ProGe::SinglePortSSRAMBlock::memoryPortGroup_
NetlistPortGroup * memoryPortGroup_
Definition:
SinglePortSSRAMBlock.hh:64
ProGe::SinglePortSSRAMBlock::~SinglePortSSRAMBlock
virtual ~SinglePortSSRAMBlock()
Definition:
SinglePortSSRAMBlock.cc:85
ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock
SinglePortSSRAMBlock()=delete
ProGe::SinglePortSSRAMBlock::memoryPort
const NetlistPortGroup & memoryPort() const
Definition:
SinglePortSSRAMBlock.cc:97
ProGe::NetlistPortGroup
Definition:
NetlistPortGroup.hh:53
ProGe::VHDL
@ VHDL
VHDL.
Definition:
ProGeTypes.hh:41
ProGe::SinglePortSSRAMBlock::isForSimulation_
bool isForSimulation_
Definition:
SinglePortSSRAMBlock.hh:66
ProGe
Definition:
FUGen.hh:54
BaseNetlistBlock.hh
ProGe::HDL
HDL
HDLs supported by ProGe.
Definition:
ProGeTypes.hh:40
ProGe::SinglePortSSRAMBlock::setAccessTraceFile
void setAccessTraceFile(const std::string filename)
Definition:
SinglePortSSRAMBlock.cc:91
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