#include <SinglePortSSRAMBlock.hh>

Inheritance diagram for ProGe::SinglePortSSRAMBlock:

Collaboration diagram for ProGe::SinglePortSSRAMBlock:

Public Member Functions
	SinglePortSSRAMBlock ()=delete

	SinglePortSSRAMBlock (const std::string &addressWidth, const std::string &dataWidth, const std::string &initFile, bool isForSimulation=true)

virtual	~SinglePortSSRAMBlock ()

void	setAccessTraceFile (const std::string filename)

const NetlistPortGroup &	memoryPort () const

virtual void	write (const Path &targetBaseDir, HDL targetLang=VHDL) const override

Public Member Functions inherited from ProGe::BaseNetlistBlock
	BaseNetlistBlock ()

	BaseNetlistBlock (BaseNetlistBlock *parent)

	BaseNetlistBlock (const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=nullptr)

virtual	~BaseNetlistBlock ()

const std::string &	instanceName () const

void	setInstanceName (const std::string &name)

const std::string &	moduleName () const

const std::string	name () const

virtual size_t	subBlockCount () const

virtual const BaseNetlistBlock &	subBlock (size_t index) const

virtual bool	hasSubBlock (const std::string &instanceName) const

virtual bool	isSubBlock (const BaseNetlistBlock &block) const

virtual bool	hasParameter (const std::string &name) const

virtual const Parameter &	parameter (const std::string &name) const

virtual size_t	parameterCount () const

virtual const Parameter &	parameter (size_t index) const

virtual size_t	portCount () const

virtual const NetlistPort &	port (size_t index) const

virtual std::vector< const NetlistPort * >	portsBy (SignalType type) const

virtual const NetlistPort &	portBy (SignalType type, size_t index=0) const

virtual bool	hasPortsBy (SignalType type) const

virtual const NetlistPort *	port (const std::string &portName, bool partialMatch=true) const

virtual size_t	portGroupCount () const

virtual const NetlistPortGroup &	portGroup (size_t index) const

virtual std::vector< const NetlistPortGroup * >	portGroupsBy (SignalGroupType type) const

virtual const Netlist &	netlist () const

virtual bool	hasParentBlock () const

virtual const BaseNetlistBlock &	parentBlock () const

virtual bool	isVirtual () const

virtual void	build () override

virtual void	connect () override

virtual void	finalize () override

virtual void	writeSelf (const Path &targetBaseDir, HDL targetLang=VHDL) const

virtual size_t	packageCount () const

virtual const std::string &	package (size_t idx) const

PortContainerType &	ports ()

virtual bool	isLeaf () const

BaseNetlistBlock *	shallowCopy (const std::string &instanceName="") const

Public Member Functions inherited from ProGe::IGenerationPhases
virtual	~IGenerationPhases ()

Private Attributes
NetlistPortGroup *	memoryPortGroup_ = nullptr

bool	isForSimulation_ = true

Additional Inherited Members
Public Types inherited from ProGe::BaseNetlistBlock
typedef std::vector< BaseNetlistBlock * >	BlockContainerType

typedef std::vector< Parameter >	ParameterContainerType

typedef std::vector< NetlistPort * >	PortContainerType

typedef std::vector< NetlistPortGroup * >	PortGroupContainerType

Protected Member Functions inherited from ProGe::BaseNetlistBlock
Netlist &	netlist ()

virtual NetlistPort &	port (size_t index)

virtual BaseNetlistBlock &	subBlock (size_t index)

virtual BaseNetlistBlock &	parentBlock ()

void	setModuleName (const std::string &name)

void	addSubBlock (BaseNetlistBlock *subBlock, const std::string &instanceName="")

void	deleteSubBlock (BaseNetlistBlock *subBlock)

void	removeSubBlock (BaseNetlistBlock *subBlock)

NetlistPort *	addPort (NetlistPort *port)

void	removePort (NetlistPort *port)

void	addPortGroup (NetlistPortGroup *portGroup)

void	removePortGroup (NetlistPortGroup *portGroup)

void	setParameter (const Parameter &param)

void	addParameter (const Parameter &param)

Parameter &	parameter (const std::string &name)

NetlistPort *	findPort (const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const

void	addPackage (const std::string &packageName)

void	connectClocks ()

void	connectResets ()

Detailed Description

Definition at line 46 of file SinglePortSSRAMBlock.hh.

Constructor & Destructor Documentation

◆ SinglePortSSRAMBlock() [1/2]

ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock ( )

delete

◆ SinglePortSSRAMBlock() [2/2]

ProGe::SinglePortSSRAMBlock::SinglePortSSRAMBlock	(	const std::string &	addressWidth,
		const std::string &	dataWidth,
		const std::string &	memInitFile,
		bool	isForSimulation = `true`
	)

Constructs Single port synchronous SRAM block.

Parameters

addressWidth	The width of the address port.
dataWidth	The width of the data port.
memInitFile	Name of the memory initialization file loaded during RTL-simulation.
isForSimulation	Tells if the block is used in RTL simulation. Affects placement of the HDL source.

Definition at line 56 of file SinglePortSSRAMBlock.cc.

     : BaseNetlistBlock("synch_sram", ""), isForSimulation_(isForSimulation) {
     addParameter(Parameter("DATAW", "integer", dataWidth));
     addParameter(Parameter("ADDRW", "integer", addressWidth));
     addParameter(Parameter("INITFILENAME", "string", memInitFile));
     addParameter(Parameter("access_trace", "boolean", "false"));
     addParameter(
         Parameter("ACCESSTRACEFILENAME", "string", "\"access_trace\""));
  
     addPort(PortFactory::clockPort());
  
     // todo add memory ports via PortFactory
     addPortGroup(
         memoryPortGroup_ = new NetlistPortGroup(
             SignalGroupType::BITMASKED_SRAM_PORT,
             new InPort("d", "DATAW", BIT_VECTOR, SignalType::WRITE_DATA),
             new InPort("addr", "ADDRW", BIT_VECTOR, SignalType::ADDRESS),
             new InBitPort(
                 "en_x",
                 Signal(SignalType::READ_WRITE_REQUEST, ActiveState::LOW)),
             new InBitPort(
                 "wr_x", Signal(SignalType::WRITEMODE, ActiveState::LOW)),
             new InPort(
                 "bit_wr_x", "DATAW", BIT_VECTOR, SignalType::WRITE_BITMASK),
             new OutPort("q", "DATAW", BIT_VECTOR, SignalType::READ_DATA)));
 }

References ProGe::BaseNetlistBlock::addParameter(), ProGe::BaseNetlistBlock::addPort(), ProGe::BaseNetlistBlock::addPortGroup(), ProGe::ADDRESS, ProGe::BIT_VECTOR, ProGe::BITMASKED_SRAM_PORT, ProGe::PortFactory::clockPort(), ProGe::LOW, memoryPortGroup_, ProGe::BaseNetlistBlock::NetlistPortGroup, ProGe::BaseNetlistBlock::Parameter, ProGe::READ_DATA, ProGe::READ_WRITE_REQUEST, ProGe::WRITE_BITMASK, ProGe::WRITE_DATA, and ProGe::WRITEMODE.

Here is the call graph for this function:

◆ ~SinglePortSSRAMBlock()

ProGe::SinglePortSSRAMBlock::~SinglePortSSRAMBlock ( )

virtual

Definition at line 85 of file SinglePortSSRAMBlock.cc.

85 {}

Member Function Documentation

◆ memoryPort()

const NetlistPortGroup & ProGe::SinglePortSSRAMBlock::memoryPort ( ) const

Definition at line 97 of file SinglePortSSRAMBlock.cc.

                                        {
     assert(memoryPortGroup_ != nullptr);
     return *memoryPortGroup_;
 }

References assert, and memoryPortGroup_.

Referenced by ProGe::ProcessorWrapperBlock::addDataMemory(), and ProGe::ProcessorWrapperBlock::addInstructionMemory().

◆ setAccessTraceFile()

void ProGe::SinglePortSSRAMBlock::setAccessTraceFile ( const std::string filename )

Sets a file name where memory access trace is dumped for this memory.

Definition at line 91 of file SinglePortSSRAMBlock.cc.

                                                                  {
     this->setParameter(Parameter("access_trace", "boolean", "true"));
     this->setParameter(Parameter("ACCESSTRACEFILENAME", "string", filename));
 }

References ProGe::BaseNetlistBlock::Parameter, and ProGe::BaseNetlistBlock::setParameter().

Referenced by ProGe::ProcessorWrapperBlock::addInstructionMemory().

Here is the call graph for this function:

◆ write()

void ProGe::SinglePortSSRAMBlock::write	(	const Path &	targetBaseDir,
		HDL	targetLang = `VHDL`
	)		const

overridevirtual

Does nothing on self but calls write function on each sub block.

Reimplemented from ProGe::BaseNetlistBlock.

Definition at line 103 of file SinglePortSSRAMBlock.cc.

                                                                            {
     Path progeDataDir(Environment::dataDirPath("ProGe"));
  
     std::string tempFile = (targetLang == VHDL)
                                ? std::string("synch_sram.vhdl")
                                : std::string("synch_sram.v");
     std::string targetDir =
         (isForSimulation_) ? std::string("tb")
                            : ((targetLang == VHDL) ? std::string("vhdl")
                                                    : std::string("verilog"));
     HDLTemplateInstantiator().instantiateTemplateFile(
         (progeDataDir / "tb" / tempFile).string(),
         (targetBaseDir / targetDir / tempFile).string());
 }

References Environment::dataDirPath(), HDLTemplateInstantiator::instantiateTemplateFile(), isForSimulation_, and ProGe::VHDL.

Here is the call graph for this function:

Member Data Documentation

◆ isForSimulation_

bool ProGe::SinglePortSSRAMBlock::isForSimulation_ = true

private

Definition at line 66 of file SinglePortSSRAMBlock.hh.

Referenced by write().

◆ memoryPortGroup_

NetlistPortGroup* ProGe::SinglePortSSRAMBlock::memoryPortGroup_ = nullptr

private

Definition at line 64 of file SinglePortSSRAMBlock.hh.

Referenced by memoryPort(), and SinglePortSSRAMBlock().

The documentation for this class was generated from the following files:

Public Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ SinglePortSSRAMBlock() [1/2]

◆ SinglePortSSRAMBlock() [2/2]

◆ ~SinglePortSSRAMBlock()

Member Function Documentation

◆ memoryPort()

◆ setAccessTraceFile()

◆ write()

Member Data Documentation

◆ isForSimulation_

◆ memoryPortGroup_