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34 #ifndef BASENETLISTBLOCK_HH
35 #define BASENETLISTBLOCK_HH
50 class NetlistPortGroup;
81 const std::string
name()
const;
99 const std::string& portName,
100 bool partialMatch =
true)
const;
104 virtual std::vector<const NetlistPortGroup*>
portGroupsBy(
114 virtual void build()
override;
115 virtual void connect()
override;
118 const Path& targetBaseDir,
HDL targetLang =
VHDL)
const override;
120 const Path& targetBaseDir,
HDL targetLang =
VHDL)
const;
123 virtual const std::string&
package(
size_t idx)
const;
134 virtual bool isLeaf()
const {
return true; }
159 const std::string& portName,
160 bool recursiveSearch =
false,
161 bool partialMatch =
true)
const;
162 void addPackage(
const std::string& packageName);
void setModuleName(const std::string &name)
NetlistPort * addPort(NetlistPort *port)
const std::string name() const
void addSubBlock(BaseNetlistBlock *subBlock, const std::string &instanceName="")
virtual bool hasPortsBy(SignalType type) const
virtual void writeSelf(const Path &targetBaseDir, HDL targetLang=VHDL) const
bool operator()(const BaseNetlistBlock *a, const BaseNetlistBlock *b) const
virtual bool hasSubBlock(const std::string &instanceName) const
virtual bool isSubBlock(const BaseNetlistBlock &block) const
virtual size_t parameterCount() const
void setParameter(const Parameter ¶m)
void removePort(NetlistPort *port)
std::vector< BaseNetlistBlock * > BlockContainerType
virtual bool isLeaf() const
void addParameter(const Parameter ¶m)
const std::string & instanceName() const
virtual std::vector< const NetlistPort * > portsBy(SignalType type) const
virtual const std::string & package(size_t idx) const
std::vector< NetlistPortGroup * > PortGroupContainerType
BlockContainerType subBlocks_
The sub blocks of this netlist block.
virtual void connect() override
virtual const Netlist & netlist() const
virtual const BaseNetlistBlock & parentBlock() const
void deleteSubBlock(BaseNetlistBlock *subBlock)
Netlist * netlist_
The netlist of the block.
virtual size_t portGroupCount() const
virtual bool hasParentBlock() const
BaseNetlistBlock * parent_
The reference to parent block of this block.
void addPortGroup(NetlistPortGroup *portGroup)
std::vector< NetlistPort * > PortContainerType
virtual void setParent(BaseNetlistBlock *parent)
virtual bool hasParameter(const std::string &name) const
virtual const Parameter & parameter(const std::string &name) const
virtual std::vector< const NetlistPortGroup * > portGroupsBy(SignalGroupType type) const
PortContainerType ports_
The ports of the block.
std::vector< Parameter > ParameterContainerType
virtual size_t portCount() const
virtual size_t packageCount() const
void addPackage(const std::string &packageName)
NetlistPort * findPort(const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const
std::string moduleName_
The module name of the block.
virtual const NetlistPortGroup & portGroup(size_t index) const
PortGroupContainerType portGroups_
The ports of the block.
std::string instanceName_
The instance name of the block.
virtual const NetlistPort & portBy(SignalType type, size_t index=0) const
BaseNetlistBlock & operator=(const BaseNetlistBlock &)
virtual ~BaseNetlistBlock()
virtual void finalize() override
PortContainerType & ports()
void removeSubBlock(BaseNetlistBlock *subBlock)
ParameterContainerType parameters_
The parameters of the block.
HDL
HDLs supported by ProGe.
const std::string & moduleName() const
std::vector< std::string > packages_
The referenced packages by the module.
virtual const BaseNetlistBlock & subBlock(size_t index) const
void setInstanceName(const std::string &name)
BaseNetlistBlock * shallowCopy(const std::string &instanceName="") const
virtual bool isVirtual() const
virtual void build() override
void removePortGroup(NetlistPortGroup *portGroup)
virtual size_t subBlockCount() const
virtual const NetlistPort & port(size_t index) const
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const override