#include <Stratix2SramGenerator.hh>

Inheritance diagram for Stratix2SramGenerator:

Collaboration diagram for Stratix2SramGenerator:

Public Member Functions
	Stratix2SramGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)

virtual	~Stratix2SramGenerator ()

virtual void	addMemory (const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)

virtual bool	generatesComponentHdlFile () const

virtual std::vector< TCEString >	generateComponentFile (TCEString outputPath)

Public Member Functions inherited from MemoryGenerator
	MemoryGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)

virtual	~MemoryGenerator ()

virtual bool	isCompatible (const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const

int	memoryTotalWidth () const

int	memoryMauSize () const

int	memoryWidthInMaus () const

int	memoryAddrWidth () const

TCEString	initializationFile () const

void	addLsu (TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)

Protected Member Functions
virtual TCEString	moduleName () const

virtual TCEString	instanceName (int coreId, int memIndex) const

Protected Member Functions inherited from MemoryGenerator
virtual bool	checkFuPort (const std::string fuPort, std::vector< TCEString > &reasons) const

virtual void	connectPorts (ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)

virtual MemoryGenerator::BlockPair	createMemoryNetlistBlock (ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)

const PlatformIntegrator *	platformIntegrator () const

std::ostream &	warningStream ()

std::ostream &	errorStream ()

int	portCount () const

const HDLPort *	port (int index) const

const HDLPort *	portByKeyName (TCEString name) const

TCEString	portKeyName (const HDLPort *port) const

void	addPort (const TCEString &name, HDLPort *port)

int	parameterCount () const

const ProGe::Parameter &	parameter (int index) const

void	addParameter (const ProGe::Parameter &add)

TCEString	ttaCoreName () const

TCEString	memoryIndexString (int coreId, int memIndex) const

TCEString	templatePath () const

void	instantiateTemplate (const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const

bool	hasLSUArchitecture () const

const TTAMachine::FunctionUnit &	lsuArchitecture () const

TCEString	corePortName (const TCEString &portBaseName, int coreId) const

Additional Inherited Members
Protected Types inherited from MemoryGenerator
typedef std::multimap< TCEString, HDLPort * >	PortMap

typedef std::pair< ProGe::NetlistBlock , ProGe::VirtualNetlistBlock >	BlockPair

Detailed Description

Definition at line 42 of file Stratix2SramGenerator.hh.

Constructor & Destructor Documentation

◆ Stratix2SramGenerator()

Stratix2SramGenerator::Stratix2SramGenerator	(	int	memMauWidth,
		int	widthInMaus,
		int	addrWidth,
		TCEString	initFile,
		const PlatformIntegrator *	integrator,
		std::ostream &	warningStream,
		std::ostream &	errorStream
	)

Definition at line 48 of file Stratix2SramGenerator.cc.

                              :
     MemoryGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
                     integrator, warningStream, errorStream) {
  
     ProGe::Parameter dataw("sram_dataw", "integer", "32");
     ProGe::Parameter addrw("sram_addrw", "integer", "18");
     addParameter(dataw);
     addParameter(addrw);
     addPort("STRATIXII_SRAM_DQ",
         new HDLPort("STRATIXII_SRAM_DQ", "sram_dataw", ProGe::BIT_VECTOR,
             ProGe::BIDIR, false, 32));
     addPort("STRATIXII_SRAM_ADDR",
         new HDLPort("STRATIXII_SRAM_ADDR", "sram_addrw",
             ProGe::BIT_VECTOR, ProGe::OUT, false, 18));
     addPort("STRATIXII_SRAM_WE_N",
         new HDLPort("STRATIXII_SRAM_WE_N", "1", ProGe::BIT_VECTOR,
             ProGe::OUT, false, 1));
     addPort("STRATIXII_SRAM_OE_N",
         new HDLPort("STRATIXII_SRAM_OE_N", "1", ProGe::BIT_VECTOR,
             ProGe::OUT, false, 1));
     addPort("STRATIXII_SRAM_CS_N",
         new HDLPort("STRATIXII_SRAM_CS_N", "1", ProGe::BIT_VECTOR,
             ProGe::OUT, false, 1));
     addPort("STRATIXII_SRAM_BE_N0",
         new HDLPort("STRATIXII_SRAM_BE_N0", "1", ProGe::BIT_VECTOR,
             ProGe::OUT, false, 1));
     addPort("STRATIXII_SRAM_BE_N1",
         new HDLPort("STRATIXII_SRAM_BE_N1", "1", ProGe::BIT_VECTOR,
             ProGe::OUT, false, 1));
     addPort("STRATIXII_SRAM_BE_N2",
         new HDLPort("STRATIXII_SRAM_BE_N2", "1", ProGe::BIT_VECTOR,
             ProGe::OUT, false, 1));
     addPort("STRATIXII_SRAM_BE_N3",
         new HDLPort("STRATIXII_SRAM_BE_N3", "1", ProGe::BIT_VECTOR,
             ProGe::OUT, false, 1));
 }

References MemoryGenerator::addParameter(), MemoryGenerator::addPort(), ProGe::BIDIR, ProGe::BIT_VECTOR, and ProGe::OUT.

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◆ ~Stratix2SramGenerator()

Stratix2SramGenerator::~Stratix2SramGenerator ( )

virtual

Definition at line 93 of file Stratix2SramGenerator.cc.

93 {

94 }

Member Function Documentation

◆ addMemory()

void Stratix2SramGenerator::addMemory	(	const ProGe::NetlistBlock &	ttaCore,
		ProGe::NetlistBlock &	integratorBlock,
		int	memIndex,
		int	coreId
	)

virtual

Reimplemented from MemoryGenerator.

Definition at line 98 of file Stratix2SramGenerator.cc.

                 {
     
     for (int i = 0; i < parameterCount(); i++) {
         integratorBlock.setParameter(
             parameter(i).name(),
             parameter(i).type(),
             parameter(i).value());
     }
  
     for (int i = 0; i < portCount(); i++) {
         const HDLPort* hdlPort = port(i);
         NetlistPort* memPort = hdlPort->convertToNetlistPort(integratorBlock);
  
         TCEString corePortName = portKeyName(hdlPort);
         const NetlistPort* corePort = ttaCore.port(corePortName);
         assert(corePort != NULL);
  
         MemoryGenerator::connectPorts(
             integratorBlock, *memPort, *corePort,
             hdlPort->needsInversion(), coreId);
     }
  
 }

References assert, MemoryGenerator::connectPorts(), HDLPort::convertToNetlistPort(), MemoryGenerator::corePortName(), ProGe::Parameter::name(), HDLPort::needsInversion(), MemoryGenerator::parameter(), MemoryGenerator::parameterCount(), ProGe::NetlistBlock::port(), MemoryGenerator::port(), MemoryGenerator::portCount(), MemoryGenerator::portKeyName(), ProGe::NetlistBlock::setParameter(), ProGe::Parameter::type(), and ProGe::Parameter::value().

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◆ generateComponentFile()

std::vector< TCEString > Stratix2SramGenerator::generateComponentFile ( TCEString outputPath )

virtual

Implements MemoryGenerator.

Definition at line 135 of file Stratix2SramGenerator.cc.

                                                       {
  
     vector<TCEString> noFileToGenerate;
     return noFileToGenerate;
 }

◆ generatesComponentHdlFile()

bool Stratix2SramGenerator::generatesComponentHdlFile ( ) const

virtual

Implements MemoryGenerator.

Definition at line 127 of file Stratix2SramGenerator.cc.

                                                        {
  
     // Sram controller is integrated into the lsu itself
     // No need to generate separate file
     return false;
 }

◆ instanceName()

TCEString Stratix2SramGenerator::instanceName	(	int	coreId,
		int	memIndex
	)		const

protectedvirtual

Implements MemoryGenerator.

Definition at line 150 of file Stratix2SramGenerator.cc.

                                                                   {
     
     TCEString iname("stratixII_sram_");
     return iname << memoryIndexString(coreId, memIndex);
 }

References MemoryGenerator::memoryIndexString().

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◆ moduleName()

TCEString Stratix2SramGenerator::moduleName ( ) const

protectedvirtual

Implements MemoryGenerator.

Definition at line 143 of file Stratix2SramGenerator.cc.

                                         {
  
     return "stratixII_sram_comp";
 }

The documentation for this class was generated from the following files:

Public Member Functions

Protected Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ Stratix2SramGenerator()

◆ ~Stratix2SramGenerator()

Member Function Documentation

◆ addMemory()

◆ generateComponentFile()

◆ generatesComponentHdlFile()

◆ instanceName()

◆ moduleName()