VLIWConnectIC Class Reference

Inheritance diagram for VLIWConnectIC:

Collaboration diagram for VLIWConnectIC:

Protected Member Functions
void	readParameters ()
TTAMachine::Segment *	createBus (TTAMachine::Machine *mach, int width)
int	widthIndex (int width)
Protected Member Functions inherited from DesignSpaceExplorerPlugin
	DesignSpaceExplorerPlugin ()
void	checkParameters () const
Protected Member Functions inherited from DesignSpaceExplorer
TTAProgram::Program *	schedule (const std::string applicationFile, TTAMachine::Machine &machine, TCEString paramOptions="-O3")
const ExecutionTrace *	simulate (const TTAProgram::Program &program, const TTAMachine::Machine &machine, const TestApplication &testApplication, const ClockCycleCount &maxCycles, ClockCycleCount &runnedCycles, const bool tracing, const bool useCompiledSimulation=false, std::vector< ClockCycleCount > *executionCounts=NULL)

Protected Attributes
bool	wipeRegisterFile_
int	shortImmediateWidth_
int	longImmediateBusCount_
std::vector< int >	distinctBusWidths_
Protected Attributes inherited from DesignSpaceExplorerPlugin
std::string	pluginName_
	the name of the explorer plugin More...
ParameterMap	parameters_
	Parameters for the plugin. More...

Static Protected Attributes
static const TCEString	wipeRegisterFilePN_
static const TCEString	shortImmediateWidthPN_
static const TCEString	longImmediateBusCountPN_

Private Member Functions
	PLUGIN_DESCRIPTION ("Arranges architecture FUs into a VLIW-like " "interconnection by adding separate RF for each distinct bus width.")
	VLIWConnectIC ()
virtual bool	requiresStartingPointArchitecture () const
virtual bool	producesArchitecture () const
virtual bool	requiresHDB () const
virtual bool	requiresSimulationData () const
virtual bool	requiresApplication () const
virtual std::vector< RowID >	explore (const RowID &configurationID, const unsigned int &)

Additional Inherited Members
Public Types inherited from DesignSpaceExplorerPlugin
typedef std::pair< std::string, ExplorerPluginParameter >	Parameter
typedef std::map< std::string, ExplorerPluginParameter >	ParameterMap
typedef std::map< std::string, ExplorerPluginParameter >::iterator	PMIt
typedef std::map< std::string, ExplorerPluginParameter >::const_iterator	PMCIt
Public Member Functions inherited from DesignSpaceExplorerPlugin
virtual std::string	description () const
void	addParameter (TCEString name, ExplorerPluginParameterType type, bool compulsory=true, TCEString defaultValue="", TCEString description="")
template<typename T >
void	readCompulsoryParameter (const std::string paramName, T &param) const
template<typename T >
void	readOptionalParameter (const std::string paramName, T &param) const
template<typename RT >
RT	parameterValue (const std::string &paramName) const
virtual	~DesignSpaceExplorerPlugin ()
virtual void	giveParameter (const std::string &name, const std::string &value)
virtual std::string	name () const
virtual void	setPluginName (const std::string &pluginName)
virtual bool	hasParameter (const std::string &paramName) const
ParameterMap	parameters () const
virtual bool	booleanValue (const std::string &parameter) const
Public Member Functions inherited from DesignSpaceExplorer
	DesignSpaceExplorer ()
virtual	~DesignSpaceExplorer ()
virtual void	setDSDB (DSDBManager &dsdb)
virtual bool	evaluate (const DSDBManager::MachineConfiguration &configuration, CostEstimates &results=dummyEstimate_, bool estimate=false)
virtual DSDBManager &	db ()
std::vector< DesignSpaceExplorerPlugin * >	getPlugins ()
RowID	createImplementationAndStore (const DSDBManager::MachineConfiguration &conf, const double &frequency=0.0, const double &maxArea=0.0, const bool &createEstimates=true, const std::string &icDec="DefaultICDecoder", const std::string &icDecHDB="asic_130nm_1.5V.hdb")
bool	createImplementation (const DSDBManager::MachineConfiguration &conf, DSDBManager::MachineConfiguration &newConf, const double &frequency=0.0, const double &maxArea=0.0, const bool &createEstimates=true, const std::string &icDec="DefaultICDecoder", const std::string &icDecHDB="asic_130nm_1.5V.hdb")
IDF::MachineImplementation *	selectComponents (const TTAMachine::Machine &mach, const double &frequency=0.0, const double &maxArea=0.0, const std::string &icDec="DefaultICDecoder", const std::string &icDecHDB="asic_130nm_1.5V.hdb") const
void	createEstimateData (const TTAMachine::Machine &mach, const IDF::MachineImplementation &idf, CostEstimator::AreaInGates &area, CostEstimator::DelayInNanoSeconds &longestPathDelay)
RowID	addConfToDSDB (const DSDBManager::MachineConfiguration &conf)
Static Public Member Functions inherited from DesignSpaceExplorer
static DesignSpaceExplorerPlugin *	loadExplorerPlugin (const std::string &pluginName, DSDBManager *dsdb=NULL)

Detailed Description

Definition at line 53 of file VLIWConnectIC.cc.

Constructor & Destructor Documentation

VLIWConnectIC()

VLIWConnectIC::VLIWConnectIC ( )

inlineprivate

Definition at line 58 of file VLIWConnectIC.cc.

                   : DesignSpaceExplorerPlugin(),
        wipeRegisterFile_(false),
        shortImmediateWidth_(6),
        longImmediateBusCount_(1) {
        addParameter(shortImmediateWidthPN_, INT, false, "6",
                     "Short immediate width for each bus.");
        addParameter(longImmediateBusCountPN_, INT, false, "1",
                     "Number of dummy buses for long immediates. (power-of-2)");
        addParameter(wipeRegisterFilePN_, BOOL, false, "true",
                     "Generate a VLIW-style register file.");
    }

References BOOL, and INT.

Member Function Documentation

createBus()

TTAMachine::Segment* VLIWConnectIC::createBus ( TTAMachine::Machine *  mach, int  width  )

inlineprotected

Creates a bus with specified bit width.

Parameters

mach	Machine for that bus.
width	Bit width of a bus.

Returns

Bus segment.

Definition at line 384 of file VLIWConnectIC.cc.

                                                                     {
        int idx = mach->busNavigator().count();
        TCEString busName = "B" + Conversion::toString(idx);
        Bus* newBus = new Bus(busName, width, 0, Machine::SIGN);
        TTAMachine::Segment* newSegment = 
            new TTAMachine::Segment(busName, *newBus);
        mach->addBus(*newBus);
        return newSegment;
    }

References TTAMachine::Machine::addBus(), TTAMachine::Machine::busNavigator(), TTAMachine::Machine::Navigator< ComponentType >::count(), TTAMachine::Machine::SIGN, and Conversion::toString().

Here is the call graph for this function:

explore()

virtual std::vector<RowID> VLIWConnectIC::explore ( const RowID &  configurationID, const unsigned int &    )

inlineprivatevirtual

Arranges architecture FUs into a VLIW-like interconnection. This is typically as baseline for running the BusMergeMinimizer and RFPortMergeMinimizer plugins.

Reimplemented from DesignSpaceExplorerPlugin.

Definition at line 83 of file VLIWConnectIC.cc.

                                                               {
        readParameters();
 
        std::vector<RowID> result;
 
        DSDBManager& dsdb = db();
        DSDBManager::MachineConfiguration conf;
        conf.hasImplementation = false;
        TTAMachine::Machine* mach = NULL;
 
        // load the adf from file or from dsdb
        try {
            conf = dsdb.configuration(configurationID);
            mach = dsdb.architecture(conf.architectureID);
        } catch (const Exception& e) {
            std::ostringstream msg(std::ostringstream::out);
            Application::errorStream()
                << "Error loading the adf." << std::endl;
            return result;
        }
        assert(mach != NULL);
 
        //Find BOOL
        TTAMachine::Machine::RegisterFileNavigator rfNavi 
            = mach->registerFileNavigator();
            
        RegisterFile* boolrf = NULL;
        for (int i = 0; i < rfNavi.count(); i++) {
            RegisterFile* rf = rfNavi.item(i);
            if (rf->width() == 1) {
                boolrf = rf;
            }
        }
        assert(boolrf != NULL);
 
        // Remove register files, except for BOOL
        if (wipeRegisterFile_) {
            for (int i = 0; i < rfNavi.count(); i++) {
                RegisterFile* rf = rfNavi.item(i);
                if (rf->width() != 1) {
                    mach->removeRegisterFile(*rfNavi.item(i));
                    i--;
                }
            }
        }
 
        // Remove unconnected sockets
        TTAMachine::Machine::SocketNavigator socketNavi 
            = mach->socketNavigator();
        for (int i = 0; i < socketNavi.count(); i++) {
            if (socketNavi.item(i)->portCount() == 0 ) {
                mach->removeSocket(*socketNavi.item(i));
                i--;
            }
        }
 
        // Wiping buses also destroys socket directions (input/output)
        // and there seems to be no other way to find out whether a port 
        // is input or output.
        // -> Save the directions before wiping the buses
 
        // get number of all distinct bus widths in the machine first
        std::vector<int>::iterator iter;
 
        for (int i = 0; i < socketNavi.count(); i++) {
            Socket* sock = socketNavi.item(i);
 
            assert(sock->portCount() == 1);
            int width = sock->port(0)->width();
 
            // combine <=32 bit widths into one cluster
            if (width < 32) {
                width = 32;
            }
 
            // add non-existing width to distinctBusWidths
            iter = std::find(distinctBusWidths_.begin(),
                distinctBusWidths_.end(), width);
            if (iter == distinctBusWidths_.end()) {
                distinctBusWidths_.push_back(width);
            }
        }
 
        sort(distinctBusWidths_.begin(), distinctBusWidths_.end());
        int numDistinctBusWidths = distinctBusWidths_.size();
 
        // save directions and sockets
        std::vector<Socket::Direction> directions;
        std::vector< std::vector<int> > readSockets(numDistinctBusWidths),
            writeSockets(numDistinctBusWidths),
            controlSockets(numDistinctBusWidths);
 
        for (int i = 0; i < socketNavi.count(); i++) {
            Socket* sock = socketNavi.item(i);
            Socket::Direction dir = sock->direction();
            directions.push_back(dir);
 
            assert(sock->portCount() == 1);
            Unit* parentUnit = sock->port(0)->parentUnit();
            int width = sock->port(0)->width();
            int widx = widthIndex(width);
 
            if (dynamic_cast<BaseRegisterFile*>(parentUnit) == NULL
                && dynamic_cast<ControlUnit*>(parentUnit) == NULL) {
                if (dir == Socket::INPUT) {
                    readSockets[widx].push_back(i);
                }
                else {
                    writeSockets[widx].push_back(i);
                }
            }
            else {
                controlSockets[widx].push_back(i);
            }
            
        }
 
        // Wipe all existing buses
 
        TTAMachine::Machine::BusNavigator busNavi = mach->busNavigator();
        for (int i = 0; i < busNavi.count(); i++) {
            mach->removeBus(*busNavi.item(i));
            i--;
        }
 
        // Add new bus for each fu/gcu socket
        std::vector< std::vector<int> > readBuses(numDistinctBusWidths),
            writeBuses(numDistinctBusWidths);
        int busCount = 0;
        
        for (int widx = 0; widx < numDistinctBusWidths; ++widx) {
            int width = distinctBusWidths_[widx];
            
            if (widx == 0) {
                TTAMachine::Segment* newSegment = createBus(mach, 32);
                
                for (unsigned int i = 0; i < controlSockets[widx].size(); i++) {
                    int idx = controlSockets[widx][i];
                    newSegment->attachSocket(*socketNavi.item(idx));
                    socketNavi.item(idx)->setDirection(directions[idx]);
                }
                readBuses[widx].push_back(busCount);
                writeBuses[widx].push_back(busCount++);
            }
 
            for (unsigned int i = 0; i < readSockets[widx].size(); i++) {
                int idx = readSockets[widx][i];
                TTAMachine::Segment* newSegment = createBus(mach, width);
                newSegment->attachSocket(*socketNavi.item(idx));
                socketNavi.item(idx)->setDirection(directions[idx]);
                readBuses[widx].push_back(busCount++);
            }
 
            for (unsigned int i = 0; i < writeSockets[widx].size(); i++) {
                int idx = writeSockets[widx][i];
                TTAMachine::Segment* newSegment = createBus(mach, width);
                newSegment->attachSocket(*socketNavi.item(idx));
                socketNavi.item(idx)->setDirection(directions[idx]);
                writeBuses[widx].push_back(busCount++);
            }
        }
 
        // Add register file
        for (int widx = 0; widx < numDistinctBusWidths; ++widx) {
            if (readBuses[widx].size() == 0 && writeBuses[widx].size() == 0) {
                continue;
            }
 
            if (wipeRegisterFile_) {
                int width = distinctBusWidths_[widx];
              
                RegisterFile* rf = new RegisterFile(
                    "RF_" + Conversion::toString(width),
                    512, // high enough to avoid register spills
                    width,
                    readBuses[widx].size(),
                    writeBuses[widx].size(),
                    0,
                    RegisterFile::NORMAL);
                mach->addRegisterFile(*rf);
 
                // Add RF read ports
                for (unsigned int i = 0; i < readBuses[widx].size(); i++) {
                    TCEString socketName = "R" + Conversion::toString(i) + 
                                           "_" + Conversion::toString(width);
                    Socket* newSocket = new Socket(socketName);
                    mach->addSocket(*newSocket);
                    
                    RFPort* newPort = new RFPort(socketName, *rf);
                    newPort->attachSocket(*newSocket);
                    busNavi.item(readBuses[widx][i])->segment(0)->
                        attachSocket(*newSocket);
                    newSocket->setDirection(Socket::OUTPUT);
                }
 
                // Add RF write ports
                for (unsigned int i = 0; i < writeBuses[widx].size(); i++) {
                    TCEString socketName = "W" + Conversion::toString(i) + 
                                           "_" + Conversion::toString(width);
                    Socket* newSocket = new Socket(socketName);
                    mach->addSocket(*newSocket);
                    
                    RFPort* newPort = new RFPort(socketName, *rf);
                    newPort->attachSocket(*newSocket);
                    busNavi.item(writeBuses[widx][i])->segment(0)->
                        attachSocket(*newSocket);
                    newSocket->setDirection(Socket::INPUT);
                }
            }
        }
 
        // Add bypasses
        for (int widx = 0; widx < numDistinctBusWidths; ++widx) {
            for (unsigned int i = 0; i < writeSockets[widx].size(); i++) {
                Socket* output = socketNavi.item(writeSockets[widx][i]);
                for (unsigned int j = 0; j < readBuses[widx].size(); j++) {
                    Bus* readBus = busNavi.item(readBuses[widx][j]);
                    readBus->segment(0)->attachSocket(*output);
                }
            }
        }
 
        for (int i = 0; i < busNavi.count(); i++) {
            Bus* bus = busNavi.item(i);
            
            new UnconditionalGuard(false, *bus);
            new RegisterGuard(false, *boolrf, 0, bus);
            new RegisterGuard(true, *boolrf, 0, bus);
            new RegisterGuard(false, *boolrf, 1, bus);
            new RegisterGuard(true, *boolrf, 1, bus);
        }
 
        for (int i = 0; i < busNavi.count(); i++) {
            Bus* bus = busNavi.item(i);
            bus->setImmediateWidth(shortImmediateWidth_);
 
            // connect each bus to immediate unit to avoid register files access
            ImmediateUnit* immu = mach->immediateUnitNavigator().item(0);
            if (!immu->port(0)->outputSocket()->isConnectedTo(*bus)) {
                immu->port(0)->outputSocket()->attachBus(*bus->segment(0));
            }
        }
 
        // add unconnected long immediate buses
        if (mach->immediateUnitNavigator().count() != 0) {
            ImmediateUnit* immu = mach->immediateUnitNavigator().item(0);
            
            while (mach->instructionTemplateNavigator().count() > 0) {
                mach->deleteInstructionTemplate(
                    *mach->instructionTemplateNavigator().item(0));
            }
 
            new InstructionTemplate("no_limm", *mach);
 
            InstructionTemplate* limm
                = new InstructionTemplate("limm", *mach);
            for (int i = 0; i < longImmediateBusCount_; i++) {
                TTAMachine::Segment* newSegment = createBus(mach, 32);
                Bus* newBus = newSegment->parentBus();
 
                limm->addSlot(newBus->name(), 32/longImmediateBusCount_, *immu);
            }
        }
 
        // add machine to configuration
        conf.architectureID = dsdb.addArchitecture(*mach);
 
        // add new configuration to dsdb
        RowID confID = dsdb.addConfiguration(conf);
        result.push_back(confID);
        return result;
    }

References DSDBManager::addArchitecture(), DSDBManager::addConfiguration(), TTAMachine::Machine::addRegisterFile(), TTAMachine::InstructionTemplate::addSlot(), TTAMachine::Machine::addSocket(), DSDBManager::architecture(), DSDBManager::MachineConfiguration::architectureID, assert, TTAMachine::Socket::attachBus(), TTAMachine::Segment::attachSocket(), TTAMachine::Port::attachSocket(), TTAMachine::Machine::busNavigator(), DSDBManager::configuration(), TTAMachine::Machine::Navigator< ComponentType >::count(), TTAMachine::Machine::deleteInstructionTemplate(), TTAMachine::Socket::direction(), Application::errorStream(), DSDBManager::MachineConfiguration::hasImplementation, TTAMachine::Machine::immediateUnitNavigator(), TTAMachine::Socket::INPUT, TTAMachine::Machine::instructionTemplateNavigator(), TTAMachine::Socket::isConnectedTo(), TTAMachine::Machine::Navigator< ComponentType >::item(), TTAMachine::Component::name(), TTAMachine::RegisterFile::NORMAL, TTAMachine::Socket::OUTPUT, TTAMachine::Port::outputSocket(), TTAMachine::Segment::parentBus(), TTAMachine::Port::parentUnit(), TTAMachine::BaseRegisterFile::port(), TTAMachine::Socket::port(), TTAMachine::Socket::portCount(), TTAMachine::Machine::registerFileNavigator(), TTAMachine::Machine::removeBus(), TTAMachine::Machine::removeRegisterFile(), TTAMachine::Machine::removeSocket(), TTAMachine::Bus::segment(), TTAMachine::Socket::setDirection(), TTAMachine::Bus::setImmediateWidth(), TTAMachine::Machine::socketNavigator(), Conversion::toString(), TTAMachine::BaseRegisterFile::width(), and TTAMachine::Port::width().

Here is the call graph for this function:

PLUGIN_DESCRIPTION()

VLIWConnectIC::PLUGIN_DESCRIPTION ( "Arranges architecture FUs into a VLIW-like " "interconnection by adding separate RF for each distinct bus width."  )

private

producesArchitecture()

virtual bool VLIWConnectIC::producesArchitecture ( ) const

inlineprivatevirtual

Implements DesignSpaceExplorerPlugin.

Definition at line 71 of file VLIWConnectIC.cc.

{ return true; }

readParameters()

void VLIWConnectIC::readParameters ( )

inlineprotected

Reads the parameters given to the plugin.

Definition at line 371 of file VLIWConnectIC.cc.

                          {
        readOptionalParameter(wipeRegisterFilePN_, wipeRegisterFile_);
        readOptionalParameter(shortImmediateWidthPN_, shortImmediateWidth_);
        readOptionalParameter(longImmediateBusCountPN_, longImmediateBusCount_);
    }

requiresApplication()

virtual bool VLIWConnectIC::requiresApplication ( ) const

inlineprivatevirtual

Reimplemented from DesignSpaceExplorerPlugin.

Definition at line 74 of file VLIWConnectIC.cc.

{ return false; }

requiresHDB()

virtual bool VLIWConnectIC::requiresHDB ( ) const

inlineprivatevirtual

Implements DesignSpaceExplorerPlugin.

Definition at line 72 of file VLIWConnectIC.cc.

{ return false; }

requiresSimulationData()

virtual bool VLIWConnectIC::requiresSimulationData ( ) const

inlineprivatevirtual

Implements DesignSpaceExplorerPlugin.

Definition at line 73 of file VLIWConnectIC.cc.

{ return false; }

requiresStartingPointArchitecture()

virtual bool VLIWConnectIC::requiresStartingPointArchitecture ( ) const

inlineprivatevirtual

Implements DesignSpaceExplorerPlugin.

Definition at line 70 of file VLIWConnectIC.cc.

{ return true; }

widthIndex()

int VLIWConnectIC::widthIndex ( int  width )

inlineprotected

Returns corresponding cluster index in distinct buses vector list.

Parameters

width	Bus width to get index.
buses	Vector list of distinct buses in current machine.

Returns

Bus width cluster index.

Definition at line 401 of file VLIWConnectIC.cc.

                              {
        if (width < 32) {
            width = 32;
        }
 
        int i = 0;
        for (auto const& busW : distinctBusWidths_) {
            if (width == busW) {
                break;
            }
            i++;
        }
        return i;
    }

Member Data Documentation

distinctBusWidths_

std::vector<int> VLIWConnectIC::distinctBusWidths_

protected

Definition at line 362 of file VLIWConnectIC.cc.

longImmediateBusCount_

int VLIWConnectIC::longImmediateBusCount_

protected

Definition at line 360 of file VLIWConnectIC.cc.

longImmediateBusCountPN_

const TCEString VLIWConnectIC::longImmediateBusCountPN_

staticprotected

Definition at line 365 of file VLIWConnectIC.cc.

shortImmediateWidth_

int VLIWConnectIC::shortImmediateWidth_

protected

Definition at line 359 of file VLIWConnectIC.cc.

shortImmediateWidthPN_

const TCEString VLIWConnectIC::shortImmediateWidthPN_

staticprotected

Definition at line 364 of file VLIWConnectIC.cc.

wipeRegisterFile_

bool VLIWConnectIC::wipeRegisterFile_

protected

Definition at line 358 of file VLIWConnectIC.cc.

wipeRegisterFilePN_

const TCEString VLIWConnectIC::wipeRegisterFilePN_

staticprotected

Definition at line 363 of file VLIWConnectIC.cc.

---

The documentation for this class was generated from the following file:

• VLIWConnectIC.cc