OpenASIP 2.2
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ICDecoderGeneratorPlugin.hh
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1/*
2 Copyright (c) 2002-2009 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file ICDecoderGeneratorPlugin.hh
26 *
27 * Declaration of ICDecoderGeneratorPlugin class.
28 *
29 * @author Lasse Laasonen 2005 (lasse.laasonen-no.spam-tut.fi)
30 * @author Vinogradov Viacheslav(added Verilog generating) 2012
31 * @note rating: red
32 */
33
34#ifndef TTA_ICDECODER_GENERATOR_PLUGIN_HH
35#define TTA_ICDECODER_GENERATOR_PLUGIN_HH
36
37#include <map>
38#include <string>
39#include <iostream>
40#include <set>
41
42#include "Socket.hh"
43#include "HDBTypes.hh"
44#include "ProGeTypes.hh"
46
47namespace TTAMachine {
48 class Machine;
49 class ImmediateUnit;
50}
51
52namespace IDF {
53 class MachineImplementation;
54}
55
56class BinaryEncoding;
57
58namespace ProGe {
59
60class NetlistBlock;
61class NetlistGenerator;
62
63/**
64 * Base class for plugins that are able to generate and IC and decoder.
65 *
66 * @todo Add rest of the methods.
67 */
69public:
72 const BinaryEncoding& bem,
73 const std::string& description);
75
76 /**
77 * Completes the given netlist block by adding IC block and completing the
78 * decoder block by adding the ports connected to IC. Connects also IC
79 * to all the units in the machine.
80 *
81 * @param coreBlock The netlist block to complete.
82 * @param generator The netlist generator which generated the netlist.
83 */
84 virtual void completeNetlist(
85 NetlistBlock& netlistBlock,
86 const NetlistGenerator& generator) = 0;
87
88 /**
89 * Generates the interconnection network and instruction decoder to the
90 * given destination directory.
91 *
92 * @param destinationDirectory The destination directory.
93 * @param generator The netlist generator that generated the netlist block.
94 */
95 virtual void generate(
96 HDL language,
97 const std::string& destinationDirectory,
98 const NetlistGenerator& generator,
100 const std::string& entityString) = 0;
101
102 /**
103 * Returns the set of acceptable latencies of the hardware implementation
104 * of the given immediate unit.
105 *
106 * @param iu The immediate unit.
107 */
108 virtual std::set<int> requiredRFLatencies(
109 const TTAMachine::ImmediateUnit& iu) const = 0;
110
111 /**
112 * Verifies that the plugin is compatible with the machine.
113 *
114 * @exception InvalidData If the plugin is not compatible with the
115 * machine.
116 */
117 virtual void verifyCompatibility() const = 0;
118
119 /**
120 * Returns global package definitions in the form of a stream specifically
121 * for the variable length instruction architecture.
122 *
123 * @param language The HDL to use.
124 * @param pkgStream The destination stream
125 */
127 HDL language, std::ostream& pkgStream)
128 const = 0;
129
130 std::string pluginDescription() const;
131 int recognizedParameterCount() const;
132 std::string recognizedParameter(int index) const;
133 std::string parameterDescription(const std::string& paramName) const;
134 void setParameter(const std::string& name, const std::string& value);
135
136 const TTAMachine::Machine& machine() const;
137 const BinaryEncoding& bem() const;
138 virtual void readParameters() = 0;
139
140protected:
142 HDB::Direction direction);
143 void addParameter(
144 const std::string& name,
145 const std::string& description);
146 bool hasParameterSet(const std::string& name) const;
147 std::string parameterValue(const std::string& name) const;
148
149private:
150 /// Map type for strings.
151 typedef std::map<std::string, std::string> StringMap;
152
153 /// The machine to generate.
155 /// The binary encoding map.
157 /// Parameters set.
159 /// Parameter descriptions.
161 /// Description of the plugin.
162 std::string description_;
163};
164
165/**
166 * Exports the given class as an IC&decoder generator.
167 *
168 * @note The class name of the generator MUST be [PLUGIN_NAME__]Generator,
169 * thus a generator exported with EXPORT_ICDEC_GENERATOR(Example)
170 * exports a class called ExampleGenerator.
171 */
172#define EXPORT_ICDEC_GENERATOR(PLUGIN_NAME__) \
173extern "C" { \
174 ICDecoderGeneratorPlugin*\
175 create_generator_plugin_##PLUGIN_NAME__(\
176 const TTAMachine::Machine& machine,\
177 const BinaryEncoding& bem) {\
178 PLUGIN_NAME__##Generator* instance = \
179 new PLUGIN_NAME__##Generator(machine, bem); \
180 return instance;\
181 }\
182 void delete_generator_plugin_##PLUGIN_NAME__(\
183 ICDecoderGeneratorPlugin* target) {\
184 delete target;\
185 }\
186}
187}
188
189#endif
IDF::MachineImplementation * implementation
the implementation definition of the estimated processor
void addParameter(const std::string &name, const std::string &description)
virtual std::set< int > requiredRFLatencies(const TTAMachine::ImmediateUnit &iu) const =0
const BinaryEncoding & bem() const
virtual void writeGlobalDefinitions(HDL language, std::ostream &pkgStream) const =0
const BinaryEncoding & bem_
The binary encoding map.
std::map< std::string, std::string > StringMap
Map type for strings.
std::string parameterValue(const std::string &name) const
virtual void generate(HDL language, const std::string &destinationDirectory, const NetlistGenerator &generator, const IDF::MachineImplementation &implementation, const std::string &entityString)=0
std::string recognizedParameter(int index) const
bool hasParameterSet(const std::string &name) const
virtual void verifyCompatibility() const =0
std::string description_
Description of the plugin.
static TTAMachine::Socket::Direction convertDirection(HDB::Direction direction)
StringMap parameterDescriptions_
Parameter descriptions.
const TTAMachine::Machine & machine() const
std::string parameterDescription(const std::string &paramName) const
virtual void completeNetlist(NetlistBlock &netlistBlock, const NetlistGenerator &generator)=0
const TTAMachine::Machine & machine_
The machine to generate.
void setParameter(const std::string &name, const std::string &value)
Direction
Direction of port.
Definition HDBTypes.hh:40
Definition FUGen.hh:54
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40