ProGe::NetlistGenerator Class Reference

#include <NetlistGenerator.hh>

Collaboration diagram for ProGe::NetlistGenerator:

Public Member Functions
	NetlistGenerator (const ProGeContext &context, ICDecoderGeneratorPlugin &plugin)
virtual	~NetlistGenerator ()
NetlistBlock *	generate (const ProGeOptions &options, int imemWidthInMAUs, TCEString entityNameStr, std::ostream &warningStream)
NetlistPort &	netlistPort (const TTAMachine::Port &port, Direction dir=IN) const
NetlistBlock &	netlistBlock (const TTAMachine::Unit &unit) const
NetlistPort &	loadPort (const NetlistPort &port) const
bool	hasOpcodePort (const NetlistPort &port) const
NetlistPort &	rfOpcodePort (const NetlistPort &port) const
NetlistPort &	rfGuardPort (const NetlistBlock &rfBlock) const
NetlistPort &	fuOpcodePort (const NetlistBlock &fuBlock) const
NetlistPort &	fuGuardPort (const NetlistPort &fuPort) const
NetlistPort &	clkPort (const NetlistBlock &block) const
NetlistPort &	rstPort (const NetlistBlock &block) const
bool	hasGlockPort (const NetlistBlock &block) const
NetlistPort &	glockPort (const NetlistBlock &block) const
bool	hasGlockReqPort (const NetlistBlock &block) const
NetlistPort &	glockReqPort (const NetlistBlock &block) const
NetlistPort &	immediateUnitWritePort (const TTAMachine::ImmediateUnit &iu) const
NetlistPort &	gcuReturnAddressInPort () const
NetlistPort &	gcuReturnAddressOutPort () const
NetlistBlock &	ttaCore () const
NetlistBlock &	instructionDecoder () const
NetlistBlock &	instructionDecompressor () const
NetlistBlock &	instructionFetch () const
HDB::FUEntry &	fuEntry (const std::string &fuName) const
HDB::RFEntry &	rfEntry (const std::string &rfName) const
const ProGeContext &	context () const
void	mapGlobalLockRequestPort (const NetlistBlock &block, NetlistPort &glockReqPort)

Static Public Attributes
static const std::string	DECODER_INSTR_WORD_PORT
	Instruction word port name in instruction decoder.
static const std::string	DECODER_RESET_PORT = RESET_PORT_NAME
	Reset port name in instruction decoder.
static const std::string	DECODER_CLOCK_PORT = CLOCK_PORT_NAME
	Clock port name in instruction decoder.
static const std::string	DECODER_RA_LOAD_PORT
	RA load port name in instruction decoder.
static const std::string	DECODER_PC_LOAD_PORT
	PC load port name in instruction decoder.
static const std::string	DECODER_PC_OPCODE_PORT
	PC opcode port name in instruction decoder.
static const std::string	DECODER_LOCK_REQ_OUT_PORT
	Lock request out port name in instruction decoder.
static const std::string	DECODER_LOCK_REQ_IN_PORT
	Lock request in port name in instruction decoder.
static const std::string	DECODER_LOCK_STATUS_PORT
static const std::string	DECOMP_LOCK_REQ_IN_PORT
	Lock request in port name in decompressor.
static const std::string	DECOMP_GLOCK_PORT
	Global lock out port name in decompressor.
static const std::string	DECOMP_INSTR_WORD_PORT
	Instruction word port name in decompressor.
static const std::string	ADDR_WIDTH
static const std::string	FETCHBLOCK_PORT_NAME = "fetchblock"

Private Types
typedef std::multimap< const TTAMachine::Port *, NetlistPort * >	PortCorrespondenceMap
	Multimap type to map ADF ports to NetlistPorts.
typedef std::map< const TTAMachine::Unit *, NetlistBlock * >	UnitCorrespondenceMap
	Map type to map ADF Units to NetlistBlocks.
typedef std::map< const NetlistPort *, NetlistPort * >	PortRelationMap
	Map type for NetlistPorts.
typedef std::map< const NetlistBlock *, NetlistPort * >	PortPurposeMap
	Map type for NetlistPorts.
typedef std::map< const TTAMachine::ImmediateUnit *, NetlistPort * >	IUPortMap
	Map type for port of immediate units.
typedef std::map< std::string, HDB::FUEntry * >	FUEntryMap
	Map type for FUImplementation.
typedef std::map< std::string, HDB::RFEntry * >	RFEntryMap
	Map type for RFImplementation.

Private Member Functions
void	addGCUToNetlist (NetlistBlock &toplevelBlock, int imemWidthInMAUs)
void	addFUToNetlist (const IDF::FUImplementationLocation &location, NetlistBlock &netlistBlock, std::ostream &warningStream)
GeneratableFUNetlistBlock *	addGeneratableFUsToNetlist (const IDF::FUGenerated &fug, NetlistBlock &netlistBlock)
void	addFUExternalPortsToNetlist (const HDB::FUImplementation &fuImplementation, NetlistBlock &coreBlock, NetlistBlock &fuBlock, const TTAMachine::FunctionUnit &adfFU)
void	addRFToNetlist (const ProGeOptions &options, const IDF::RFImplementationLocation &location, NetlistBlock &netlistBlock)
void	addIUToNetlist (const ProGeOptions &options, const IDF::RFImplementationLocation &location, NetlistBlock &netlistBlock)
void	addBaseRFToNetlist (const ProGeOptions &options, const TTAMachine::BaseRegisterFile &regFile, const IDF::RFImplementationLocation &location, NetlistBlock &netlistBlock, const std::string &blockNamePrefix)
void	mapNetlistPort (const TTAMachine::Port &adfPort, NetlistPort &netlistPort)
void	mapNetlistBlock (const TTAMachine::Unit &unit, NetlistBlock &netlistBlock)
bool	netlistPortIsMapped (const TTAMachine::Port &adfPort)
void	mapLoadPort (const NetlistPort &port, NetlistPort &loadPort)
void	mapRFOpcodePort (const NetlistPort &port, NetlistPort &opcodePort)
void	mapClockPort (const NetlistBlock &block, NetlistPort &clkPort)
void	mapResetPort (const NetlistBlock &block, NetlistPort &resetPort)
void	mapGlobalLockPort (const NetlistBlock &block, NetlistPort &glockPort)
void	mapRFGuardPort (const NetlistBlock &block, NetlistPort &guardPort)
void	mapFUGuardPort (const NetlistPort &dataPort, NetlistPort &guardPort)
void	mapFUOpcodePort (const NetlistBlock &block, NetlistPort &opcodePort)
void	mapImmediateUnitWritePort (const TTAMachine::ImmediateUnit &iu, NetlistPort &port)
bool	isParameterizable (const std::string &paramName, const HDB::FUEntry *fuEntry) const
unsigned int	calculateAddressWidth (TTAMachine::FunctionUnit const *fu) const
TCEString	checkInstanceName (const TCEString &baseInstanceName, const TCEString &moduleName) const
bool	isLSU (const TTAMachine::FunctionUnit &fu) const

Static Private Member Functions
static bool	isLSUDataPort (const TTAMachine::FunctionUnit &adfFU, const std::string &portName)
static Signal	inferLSUSignal (const std::string &portName)
static int	opcodePortWidth (const HDB::FUEntry &fu, std::ostream &warningStream)
static int	opcodePortWidth (const TTAMachine::ControlUnit &gcu)
static TTAMachine::FUPort &	findCorrespondingPort (const TTAMachine::FunctionUnit &fuToSearch, const TTAMachine::FunctionUnit &origFU, const std::string &portName)
static int	instructionMemoryAddressWidth (const TTAMachine::Machine &machine)
static int	instructionMemoryWidth (const TTAMachine::Machine &machine)
static TTAMachine::AddressSpace &	instructionMemory (const TTAMachine::Machine &machine)
static Direction	translateDirection (HDB::Direction direction)

Private Attributes
const ProGeContext &	context_
ICDecoderGeneratorPlugin &	plugin_
	The generator plugin.
PortCorrespondenceMap	portCorrespondenceMap_
	Maps the ADF ports to the netlist ports.
UnitCorrespondenceMap	unitCorrespondenceMap_
	Maps the ADF units to the netlist blocks.
PortRelationMap	loadPortMap_
	Maps loads ports.
PortRelationMap	rfOpcodePortMap_
	Maps opcode ports.
PortPurposeMap	clkPorts_
	Maps clock ports.
PortPurposeMap	rstPorts_
	Maps reset ports.
PortPurposeMap	rfGuardPorts_
	Maps RF guard ports.
PortPurposeMap	glockPorts_
	Maps global lock ports.
PortPurposeMap	glockReqPorts_
	Maps global lock request ports.
PortRelationMap	fuGuardPortMap_
	Maps FU guard ports.
PortPurposeMap	fuOpcodePorts_
	Maps FU opcode ports.
IUPortMap	iuPortMap_
	Maps the created netlist ports to immediate units.
NetlistBlock *	coreBlock_
	The TTA core block.
NetlistBlock *	instructionDecoder_
	The instruction decoder block.
NetlistBlock *	instructionDecompressor_
	The instruction decompressor block.
NetlistBlock *	instructionFetch_
	The instruction fetch block.
FUEntryMap	fuEntryMap_
	Maps FU implementations for different FU's.
RFEntryMap	rfEntryMap_
	Maps RF implementations for different RF's.
NetlistPort *	raInPort_
	Return address in port in GCU (ifetch).
NetlistPort *	raOutPort_
	Returns address out port in GCU (ifetch).

Friends
class	GeneratableFUNetlistBlock

Detailed Description

Generates a netlist of processor building blocks. [DEPRECATED]

Definition at line 84 of file NetlistGenerator.hh.

Member Typedef Documentation

FUEntryMap

typedef std::map<std::string, HDB::FUEntry*> ProGe::NetlistGenerator::FUEntryMap

private

Map type for FUImplementation.

Definition at line 174 of file NetlistGenerator.hh.

IUPortMap

typedef std::map<const TTAMachine::ImmediateUnit*, NetlistPort*> ProGe::NetlistGenerator::IUPortMap

private

Map type for port of immediate units.

Definition at line 172 of file NetlistGenerator.hh.

PortCorrespondenceMap

typedef std::multimap<const TTAMachine::Port*, NetlistPort*> ProGe::NetlistGenerator::PortCorrespondenceMap

private

Multimap type to map ADF ports to NetlistPorts.

Definition at line 162 of file NetlistGenerator.hh.

PortPurposeMap

typedef std::map<const NetlistBlock*, NetlistPort*> ProGe::NetlistGenerator::PortPurposeMap

private

Map type for NetlistPorts.

Definition at line 169 of file NetlistGenerator.hh.

PortRelationMap

typedef std::map<const NetlistPort*, NetlistPort*> ProGe::NetlistGenerator::PortRelationMap

private

Map type for NetlistPorts.

Definition at line 167 of file NetlistGenerator.hh.

RFEntryMap

typedef std::map<std::string, HDB::RFEntry*> ProGe::NetlistGenerator::RFEntryMap

private

Map type for RFImplementation.

Definition at line 176 of file NetlistGenerator.hh.

UnitCorrespondenceMap

typedef std::map<const TTAMachine::Unit*, NetlistBlock*> ProGe::NetlistGenerator::UnitCorrespondenceMap

private

Map type to map ADF Units to NetlistBlocks.

Definition at line 165 of file NetlistGenerator.hh.

Constructor & Destructor Documentation

NetlistGenerator()

ProGe::NetlistGenerator::NetlistGenerator	(	const ProGeContext &	context,
		ICDecoderGeneratorPlugin &	plugin
	)

Definition at line 159 of file NetlistGenerator.cc.

        : context_(context), plugin_(plugin), coreBlock_(NULL),
          instructionDecoder_(NULL), instructionDecompressor_(NULL),
          instructionFetch_(NULL), raInPort_(NULL), raOutPort_(NULL) {}

~NetlistGenerator()

ProGe::NetlistGenerator::~NetlistGenerator ( )

virtual

The destructor.

Definition at line 168 of file NetlistGenerator.cc.

                                        {
        MapTools::deleteAllValues(fuEntryMap_);
        MapTools::deleteAllValues(rfEntryMap_);
    }

References MapTools::deleteAllValues(), fuEntryMap_, and rfEntryMap_.

Here is the call graph for this function:

Member Function Documentation

addBaseRFToNetlist()

void ProGe::NetlistGenerator::addBaseRFToNetlist ( const ProGeOptions &  options, const TTAMachine::BaseRegisterFile &  regFile, const IDF::RFImplementationLocation &  location, NetlistBlock &  targetBlock, const std::string &  blockNamePrefix  )

private

Adds the RF or IU identified by the given RFImplementationLocation instance to the netlist.

Parameters

regFile	The corresponding RF (or IU) in ADF.
location	The RFImplementationLocation instance.
netlist	The netlist.
blockNamePrefix	Prefix to be added to the block name.

Exceptions

IOException	If the HDB that contains the implementation cannot be accessed.
InvalidData	If the RF entry in HDB does not have an implementation or architecture or if the HDB does not have the entry defined in the RFImplementationLocation instance at all.

Definition at line 1351 of file NetlistGenerator.cc.

                                          {
        RFEntry* entry = NULL;
        try {
            HDBManager& manager =
                HDBRegistry::instance().hdb(location.hdbFile());
            entry = manager.rfByEntryID(location.id());
        } catch (const KeyNotFound& e) {
            throw InvalidData(__FILE__, __LINE__, __func__, e.errorMessage());
        }
 
        if (!entry->hasImplementation() || !entry->hasArchitecture()) {
            format text("RF entry %1% does not have an implementation or "
                        "architecture "
                        "defined in HDB %2%.");
            text % location.id() % location.hdbFile();
            throw InvalidData(__FILE__, __LINE__, __func__, text.str());
        }
 
        rfEntryMap_.insert(std::make_pair(location.unitName(), entry));
        RFImplementation& implementation = entry->implementation();
        RFArchitecture& architecture = entry->architecture();
        TCEString instanceName = blockNamePrefix + location.unitName();
        TCEString moduleName = implementation.moduleName();
        instanceName = checkInstanceName(instanceName, moduleName);
        NetlistBlock* block = new NetlistBlock(moduleName, instanceName);
        targetBlock.addSubBlock(block);
        mapNetlistBlock(regFile, *block);
 
        // Add parameters (generics) to the block.
        for (int i = 0; i < implementation.parameterCount(); i++) {
            RFImplementation::Parameter param = implementation.parameter(i);
 
            // Check if parameter matches size or width parameter reference
            // and set/override its parameter value according to
            // architecture.
            if (param.name == implementation.sizeParameter()) {
                block->setParameter(implementation.sizeParameter(), "integer",
                    Conversion::toString(regFile.numberOfRegisters()));
            } else if (param.name == implementation.widthParameter()) {
                block->setParameter(implementation.widthParameter(), "integer",
                    Conversion::toString(regFile.width()));
            } else if (param.value == "") {
                format errorMsg(
                    "Unable to resolve the value of parameter %1% of RF "
                    "entry %2%.");
                errorMsg % param.name % location.id();
                throw InvalidData(__FILE__, __LINE__, __func__, errorMsg.str());
            } else {
                block->setParameter(param.name, param.type, param.value);
            }
        }
 
        // add ports
        for (int i = 0; i < implementation.portCount(); i++) {
            RFPortImplementation& port = implementation.port(i);
            NetlistPort* newInputPort = NULL;
            NetlistPort* newOutputPort = NULL;
            if (!implementation.widthParameter().empty()) {
                switch (port.direction()) {
                    case HDB::BIDIR:
                        newInputPort = new NetlistPort(port.name()+"_in",
                            implementation.widthParameter(), regFile.width(),
                            BIT_VECTOR, IN, *block);
                        newOutputPort = new NetlistPort(port.name()+"_out",
                            implementation.widthParameter(), regFile.width(),
                            BIT_VECTOR, OUT, *block);
                        break;
                    case HDB::IN:
                        newInputPort = new NetlistPort(port.name(),
                            implementation.widthParameter(), regFile.width(),
                            BIT_VECTOR, IN,
                            *block);
                        break;
                    case HDB::OUT:
                        newOutputPort = new NetlistPort(port.name(),
                            implementation.widthParameter(), regFile.width(),
                            BIT_VECTOR, OUT, *block);
                        break;
                }
            } else {
                switch (port.direction()) {
                    case HDB::BIDIR:
                        newInputPort = new NetlistPort(port.name(),
                            Conversion::toString(architecture.width()),
                            BIT_VECTOR, IN, *block);
                        newOutputPort = new NetlistPort(port.name(),
                            Conversion::toString(architecture.width()),
                            BIT_VECTOR, OUT, *block);
                        break;
                    case HDB::IN:
                        newInputPort = new NetlistPort(port.name(),
                            Conversion::toString(architecture.width()),
                            BIT_VECTOR, IN, *block);
                        break;
                    case HDB::OUT:
                        newOutputPort = new NetlistPort(port.name(),
                            Conversion::toString(architecture.width()),
                            BIT_VECTOR, OUT, *block);
                        break;
                }
            }
            assert(newInputPort || newOutputPort);
 
            RFPort* rfPort = NULL;
            // map the port if it is not input port of IU (not visible in
            // ADF)
            if (dynamic_cast<const ImmediateUnit*>(&regFile) == NULL ||
                port.direction() != HDB::IN) {
 
                bool mapped = false;
                for (int i = 0; i < regFile.portCount(); i++) {
                    rfPort = regFile.port(i);
                    if (portCorrespondenceMap_.count(rfPort) == 0) {
                        if ((port.direction() == HDB::IN &&
                                rfPort->inputSocket() != NULL &&
                                rfPort->outputSocket() == NULL) ||
                            (port.direction() == HDB::OUT &&
                                rfPort->outputSocket() != NULL &&
                                rfPort->inputSocket() == NULL) ||
                            (port.direction() == HDB::BIDIR &&
                                rfPort->outputSocket() != NULL &&
                                rfPort->inputSocket() != NULL)) {
                            mapped = true;
                            break;
                        }
                    }
                }
 
                if (!mapped) {
                    format text("Unable to map port '%1%' of RF entry '%2%' in "
                                "HDB '%3%' "
                                "to any port in %4% '%5%'.");
                    text % port.name() % location.id() % location.hdbFile();
                    if (dynamic_cast<const ImmediateUnit*>(&regFile) != NULL) {
                        text % "immediate unit";
                    } else {
                        text % "register file";
                    }
                    text % regFile.name();
                    throw InvalidData(__FILE__, __LINE__, __func__, text.str());
                }
            }
 
            // if the given BaseRegisterFile is ImmediateUnit, keep track of
            // the
            // data ports that does not appear in ADF
            const ImmediateUnit* iu =
                dynamic_cast<const ImmediateUnit*>(&regFile);
            if (iu != NULL && newInputPort) {
                mapImmediateUnitWritePort(*iu, *newInputPort);
            }
 
            // add load port
            NetlistPort* loadPort =
                new NetlistPort(port.loadPort(), "1", BIT, IN, *block);
 
 
            // Map data (unless it is IU's write port) and load port
            if (rfPort != NULL) {
                if (newInputPort)
                    mapNetlistPort(*rfPort, *newInputPort);
                if (newOutputPort)
                    mapNetlistPort(*rfPort, *newOutputPort);
            }
            if (newInputPort)
                mapLoadPort(*newInputPort, *loadPort);
            if (newOutputPort)
                mapLoadPort(*newOutputPort, *loadPort);
 
            // add opcode port
            NetlistPort* opcodePort = NULL;
            if (!port.opcodePort().empty()) {
                opcodePort = new NetlistPort(port.opcodePort(),
                    port.opcodePortWidthFormula(),
                    MathTools::requiredBits(regFile.numberOfRegisters() - 1),
                    BIT_VECTOR, IN, *block);
                if (newInputPort)
                    mapRFOpcodePort(*newInputPort, *opcodePort);
                if (newOutputPort)
                    mapRFOpcodePort(*newOutputPort, *opcodePort);
            } else if (regFile.numberOfRegisters() == 1) {
                // Special case for single register RFs which do not need
                // opcode
                // port. For legacy support the opcode port is left out if
                // opcode
                // port field is empty in HDB.
                // Do nothing.
            } else {
                format text("RF entry '%1%' in HDB '%2%' does not have "
                            "opcode port required for RFs of size > 1.");
                text % location.id() % location.hdbFile();
                throw InvalidData(__FILE__, __LINE__, __func__, text.str());
            }
        }
 
        // add guard port
        if (architecture.hasGuardSupport()) {
            string guardPortName = implementation.guardPort();
            string size;
            if (!implementation.sizeParameter().empty()) {
                size = implementation.sizeParameter();
            } else {
                size = Conversion::toString(architecture.size());
            }
            NetlistPort* guardPort = new NetlistPort(guardPortName, size,
                regFile.numberOfRegisters(), BIT_VECTOR, OUT, *block);
            mapRFGuardPort(*block, *guardPort);
        }
 
        // Add external ports
        string component_type("");
        if (dynamic_cast<const ImmediateUnit*>(&regFile) != NULL) {
            component_type = IU_NAME_PREFIX;
        } else {
            component_type = RF_NAME_PREFIX;
        }
        for (int i = 0; i < implementation.externalPortCount(); i++) {
            RFExternalPort& externalPort = implementation.externalPort(i);
            // if external port uses parameter, it must be added as netlist
            // parameter too and create new width formula for the top-level
            // port
            // by replacing parameter names with the corresponding names in
            // netlist.
            string tlPortWidth = externalPort.widthFormula();
            for (int i = 0; i < externalPort.parameterDependencyCount(); i++) {
                string hdbParamName = externalPort.parameterDependency(i);
                Parameter param = block->parameter(hdbParamName);
                string nlParamName =
                    component_type + location.unitName() + "_" + hdbParamName;
                if (!targetBlock.netlist().hasParameter(nlParamName)) {
                    targetBlock.netlist().setParameter(
                        nlParamName, param.type(), param.value());
                }
                block->setParameter(param.name(), param.type(), nlParamName);
                size_t replaceStart = tlPortWidth.find(param.name(), 0);
                if (replaceStart == std::string::npos) {
                    throw InvalidData(__FILE__, __LINE__, __func__,
                        (boost::format("RF external port parameter "
                                       "dependencies do not "
                                       "seem "
                                       "to be right: Tried to find "
                                       "parameter named '%s'"
                                       " from external port width formula "
                                       "'%s' in unit "
                                       "'%s'") %
                            param.name() % tlPortWidth % nlParamName)
                            .str());
                }
                size_t replaceLength = param.name().length();
                tlPortWidth = tlPortWidth.replace(
                    replaceStart, replaceLength, nlParamName);
            }
 
            NetlistPort* extPort = new NetlistPort(externalPort.name(),
                externalPort.widthFormula(), BIT_VECTOR,
                translateDirection(externalPort.direction()), *block);
            // connect the external port to top level
            string tlPortName = component_type + location.unitName() + "_" +
                                externalPort.name();
            NetlistPort* tlPort =
                new NetlistPort(tlPortName, tlPortWidth, BIT_VECTOR,
                    translateDirection(externalPort.direction()), targetBlock);
            targetBlock.netlist().connect(*tlPort, *extPort);
        }
 
        // add clock port
        NetlistPort* clockPort =
            new NetlistPort(implementation.clkPort(), "1", BIT, IN, *block);
        mapClockPort(*block, *clockPort);
        // connect clock port
        NetlistPort& tlClockPort = clkPort(targetBlock);
        targetBlock.netlist().connect(tlClockPort, *clockPort);
 
        // add reset port
        NetlistPort* resetPort =
            new NetlistPort(implementation.rstPort(), "1", BIT, IN, *block);
        mapResetPort(*block, *resetPort);
        // connect reset port
        NetlistPort& tlResetPort = rstPort(targetBlock);
        targetBlock.netlist().connect(tlResetPort, *resetPort);
 
        // add glock port
        if (implementation.glockPort() != "") {
            NetlistPort* glockPort = new NetlistPort(
                implementation.glockPort(), "1", BIT, IN, *block);
            mapGlobalLockPort(*block, *glockPort);
        }
    }

References __func__, ProGe::NetlistBlock::addSubBlock(), HDB::RFEntry::architecture(), assert, HDB::BIDIR, ProGe::BIT, ProGe::BIT_VECTOR, checkInstanceName(), clkPort(), ProGe::Netlist::connect(), HDB::ExternalPort::direction(), HDB::RFPortImplementation::direction(), Exception::errorMessage(), glockPort(), HDB::RFEntry::hasArchitecture(), HDB::RFArchitecture::hasGuardSupport(), HDB::RFEntry::hasImplementation(), ProGe::Netlist::hasParameter(), HDB::HDBRegistry::hdb(), IDF::UnitImplementationLocation::hdbFile(), IDF::UnitImplementationLocation::id(), HDB::RFEntry::implementation(), implementation, HDB::IN, ProGe::IN, TTAMachine::Port::inputSocket(), HDB::HDBRegistry::instance(), IU_NAME_PREFIX, HDB::PortImplementation::loadPort(), loadPort(), mapClockPort(), mapGlobalLockPort(), mapImmediateUnitWritePort(), mapLoadPort(), mapNetlistBlock(), mapNetlistPort(), mapResetPort(), mapRFGuardPort(), mapRFOpcodePort(), HDB::ExternalPort::name(), HDB::Parameter::name, HDB::PortImplementation::name(), ProGe::Parameter::name(), TTAMachine::Component::name(), ProGe::NetlistBlock::netlist(), TTAMachine::BaseRegisterFile::numberOfRegisters(), HDB::RFPortImplementation::opcodePort(), HDB::RFPortImplementation::opcodePortWidthFormula(), HDB::OUT, ProGe::OUT, TTAMachine::Port::outputSocket(), ProGe::NetlistBlock::parameter(), HDB::ExternalPort::parameterDependency(), HDB::ExternalPort::parameterDependencyCount(), TTAMachine::BaseRegisterFile::port(), portCorrespondenceMap_, TTAMachine::Unit::portCount(), TCEString::replace(), MathTools::requiredBits(), RF_NAME_PREFIX, HDB::HDBManager::rfByEntryID(), rfEntryMap_, rstPort(), ProGe::Netlist::setParameter(), ProGe::NetlistBlock::setParameter(), HDB::RFArchitecture::size(), Conversion::toString(), translateDirection(), HDB::Parameter::type, ProGe::Parameter::type(), IDF::UnitImplementationLocation::unitName(), HDB::Parameter::value, ProGe::Parameter::value(), HDB::RFArchitecture::width(), TTAMachine::BaseRegisterFile::width(), and HDB::ExternalPort::widthFormula().

Referenced by addIUToNetlist(), and addRFToNetlist().

addFUExternalPortsToNetlist()

void ProGe::NetlistGenerator::addFUExternalPortsToNetlist ( const HDB::FUImplementation &  fuImplementation, NetlistBlock &  coreBlock, NetlistBlock &  fuBlock, const TTAMachine::FunctionUnit &  adfFU  )

private

Adds external ports defined in HDB into netlist.

Also attempts to recognize LSU memory bus ports and assign them into corresponding NetlistGroup. Recognition is now done by seeking external ports having specific patterns (see inferLSUSignal()).

Definition at line 1189 of file NetlistGenerator.cc.

                                                          {
 
        // external ports recognized as LSU' data memory ports.
        set<std::pair<NetlistPort*, NetlistPort*>> lsuPorts;
        // Other unrecognized ports.
        set<std::pair<NetlistPort*, NetlistPort*>> otherPorts;
 
        // for each external port, a port is added to top-level block too
        for (int i = 0; i < fuImplementation.externalPortCount(); i++) {
            FUExternalPort& externalPort = fuImplementation.externalPort(i);
            // if external port uses parameter, it must be added as netlist
            // parameter too and create new width formula for the top-level
            // port
            // by replacing parameter names with the corresponding names in
            // netlist.
            string tlPortWidth = externalPort.widthFormula();
            for (int i = 0; i < externalPort.parameterDependencyCount(); i++) {
                string paramName = externalPort.parameterDependency(i);
                Parameter param = fuBlock.parameter(paramName);
                string nlParamName = fuBlock.instanceName() + "_" + paramName;
                if (!coreBlock.netlist().hasParameter(nlParamName)) {
                    coreBlock.netlist().setParameter(
                        nlParamName, param.type(), param.value());
                }
                fuBlock.setParameter(param.name(), param.type(), nlParamName);
                size_t replaceStart = tlPortWidth.find(param.name(), 0);
                if (replaceStart == std::string::npos) {
                    throw InvalidData(__FILE__, __LINE__, __func__,
                        (boost::format("FU external port parameter "
                                       "dependencies do not "
                                       "seem "
                                       "to be right: Tried to find "
                                       "parameter named '%s'"
                                       " from external port width formula "
                                       "'%s' in unit "
                                       "'%s'") %
                            param.name() % tlPortWidth % nlParamName)
                            .str());
                }
                size_t replaceLength = param.name().length();
                tlPortWidth = tlPortWidth.replace(
                    replaceStart, replaceLength, nlParamName);
            }
 
            NetlistPort* extPort = new NetlistPort(externalPort.name(),
                externalPort.widthFormula(), BIT_VECTOR,
                translateDirection(externalPort.direction()), fuBlock);
            string tlPortName =
                fuBlock.instanceName() + "_" + externalPort.name();
            if (isLSUDataPort(adfFU, externalPort.name())) {
                NetlistPort* tlPort = new NetlistPort(tlPortName, tlPortWidth,
                    BIT_VECTOR, translateDirection(externalPort.direction()),
                    coreBlock, inferLSUSignal(externalPort.name()));
                lsuPorts.insert(std::make_pair(extPort, tlPort));
            } else {
                NetlistPort* tlPort = new NetlistPort(tlPortName, tlPortWidth,
                    BIT_VECTOR, translateDirection(externalPort.direction()),
                    coreBlock);
                coreBlock.netlist().connect(*extPort, *tlPort);
            }
        }
 
        // Handle LSU data ports.
        TCEString asName("");
        if (adfFU.hasAddressSpace()) {
            asName = adfFU.addressSpace()->name();
        }
 
        NetlistPortGroup* dmemPortGroup = nullptr;
        for (auto portPair : lsuPorts) {
            dmemPortGroup =
                dmemPortGroup
                    ? dmemPortGroup
                    : (new MemoryBusInterface(
                          SignalGroupType::BITMASKED_SRAM_PORT, asName));
            dmemPortGroup->addPort(*portPair.second);
            coreBlock.netlist().connect(*portPair.first, *portPair.second);
        }
        if (dmemPortGroup != nullptr) {
            coreBlock.addPortGroup(dmemPortGroup);
            dmemPortGroup = nullptr;
        }
    }

References __func__, ProGe::NetlistPortGroup::addPort(), ProGe::NetlistBlock::addPortGroup(), TTAMachine::FunctionUnit::addressSpace(), ProGe::BIT_VECTOR, ProGe::BITMASKED_SRAM_PORT, ProGe::Netlist::connect(), HDB::ExternalPort::direction(), HDB::FUImplementation::externalPort(), HDB::FUImplementation::externalPortCount(), TTAMachine::FunctionUnit::hasAddressSpace(), ProGe::Netlist::hasParameter(), inferLSUSignal(), ProGe::BaseNetlistBlock::instanceName(), isLSUDataPort(), HDB::ExternalPort::name(), ProGe::Parameter::name(), TTAMachine::Component::name(), ProGe::NetlistBlock::netlist(), ProGe::NetlistBlock::parameter(), HDB::ExternalPort::parameterDependency(), HDB::ExternalPort::parameterDependencyCount(), TCEString::replace(), ProGe::Netlist::setParameter(), ProGe::NetlistBlock::setParameter(), translateDirection(), ProGe::Parameter::type(), ProGe::Parameter::value(), and HDB::ExternalPort::widthFormula().

Referenced by addFUToNetlist().

Here is the call graph for this function:

addFUToNetlist()

void ProGe::NetlistGenerator::addFUToNetlist ( const IDF::FUImplementationLocation &  location, NetlistBlock &  coreBlock, std::ostream &  warningStream  )

private

Adds the FU identified by the given FUImplementationLocation instance to the netlist.

Parameters

location	The FUImplementationLocation instance.
netlist	The netlist block under where FU is added.

Exceptions

IOException	If the HDB that contains the implementation cannot be accessed.
InvalidData	If the MachineImplementation instance is erroneous or if HDB erroneous.

Definition at line 974 of file NetlistGenerator.cc.

                                   {
        string hdbFile = location.hdbFile();
        int id = location.id();
        FUEntry* entry = NULL;
 
        try {
            HDBManager& manager = HDBRegistry::instance().hdb(hdbFile);
            entry = manager.fuByEntryID(id);
        } catch (const KeyNotFound& e) {
            throw InvalidData(__FILE__, __LINE__, __func__, e.errorMessage());
        }
 
        if (!entry->hasImplementation() || !entry->hasArchitecture()) {
            string errorMsg;
            if (!entry->hasImplementation()) {
                errorMsg = "FU entry " + Conversion::toString(id) +
                           " does not "
                           "have an implementation in HDB " +
                           hdbFile + ".";
            } else {
                errorMsg = "FU entry " + Conversion::toString(id) +
                           " does not "
                           "have architecture definition in HDB " +
                           hdbFile + ".";
            }
            throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
        }
 
        if (!context_.adf().functionUnitNavigator().hasItem(
                location.unitName())) {
            string errorMsg = "ADF does not have FU '" + location.unitName() +
                              "' which is referred to in the IDF.";
            throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
        }
 
        fuEntryMap_.insert(std::make_pair(location.unitName(), entry));
        FUImplementation& fuImplementation = entry->implementation();
        FUArchitecture& architecture = entry->architecture();
        const FunctionUnit* adfFU =
            context_.adf().functionUnitNavigator().item(location.unitName());
        TCEString instanceName = FU_NAME_PREFIX + location.unitName();
        TCEString moduleName = fuImplementation.moduleName();
        instanceName = checkInstanceName(instanceName, moduleName);
        NetlistBlock* block = new NetlistBlock(moduleName, instanceName);
        coreBlock.addSubBlock(block);
        mapNetlistBlock(*adfFU, *block);
 
        format architecturesDontMatch("Architectures of FU entry %1% in "
                                      "%2% and FU '%3%' don't match.");
 
        // add parameters
        for (int i = 0; i < fuImplementation.parameterCount(); i++) {
            FUImplementation::Parameter parameter =
                fuImplementation.parameter(i);
            string paramName = parameter.name;
            string paramType = parameter.type;
            string paramValue = parameter.value;
            if (paramValue == "" || isParameterizable(paramName, entry)) {
                bool parameterResolved = false;
                // find the port which uses this parameter
                for (int j = 0; j < fuImplementation.architecturePortCount();
                     j++) {
                    FUPortImplementation& port =
                        fuImplementation.architecturePort(j);
 
                    // Special case if the FU is an LSU and it has
                    // parametrizable
                    // address width. This sets the ADF port width according
                    // to
                    // address space width in ADF
                    if (adfFU->hasAddressSpace() && isLSU(*adfFU)) {
                        FUPort& adfPort = findCorrespondingPort(*adfFU,
                            architecture.architecture(),
                            port.architecturePort());
                        // Assume address port is the triggering port
                        if (adfPort.isTriggering() &&
                            port.widthFormula() == paramName) {
                            int ASWidth = calculateAddressWidth(adfFU);
                            block->setParameter(paramName, paramType,
                                Conversion::toString(ASWidth));
                            // Fix the FU port width
                            adfPort.setWidth(ASWidth);
                            parameterResolved = true;
                            break;
                        }
                    }
                    if (port.widthFormula() == paramName) {
                        try {
                            FUPort& adfPort = findCorrespondingPort(*adfFU,
                                architecture.architecture(),
                                port.architecturePort());
                            block->setParameter(paramName, paramType,
                                Conversion::toString(adfPort.width()));
                            parameterResolved = true;
                            break;
                        } catch (const InstanceNotFound&) {
                            architecturesDontMatch % id % hdbFile %
                                adfFU->name();
                            throw InvalidData(__FILE__, __LINE__, __func__,
                                architecturesDontMatch.str());
                        }
                    }
                }
 
                if (!parameterResolved) {
                    format errorMsg("Unable to resolve the value of "
                                    "parameter %1% of FU "
                                    "entry %2%.");
                    errorMsg % paramName % id;
                    throw InvalidData(
                        __FILE__, __LINE__, __func__, errorMsg.str());
                }
 
            } else {
                block->setParameter(paramName, paramType, paramValue);
            }
        }
 
        // add ports to the netlist block
        for (int i = 0; i < fuImplementation.architecturePortCount(); i++) {
 
            FUPortImplementation& port = fuImplementation.architecturePort(i);
 
            // add architectural port
            string architecturePort = port.architecturePort();
 
            FUPort* adfPort;
            try {
                adfPort = &findCorrespondingPort(
                    *adfFU, architecture.architecture(), architecturePort);
            } catch (const InstanceNotFound&) {
                architecturesDontMatch % id % hdbFile % adfFU->name();
                throw InvalidData(
                    __FILE__, __LINE__, __func__, architecturesDontMatch.str());
            }
            NetlistPort* newPort = new NetlistPort(port.name(),
                port.widthFormula(), adfPort->width(), BIT_VECTOR,
                translateDirection(
                    architecture.portDirection(architecturePort)),
                *block);
            mapNetlistPort(*adfPort, *newPort);
 
            // add load port
            if (port.loadPort() != "") {
                NetlistPort* loadPort =
                    new NetlistPort(port.loadPort(), "1", 1, BIT, IN, *block);
                mapLoadPort(*newPort, *loadPort);
            }
 
            // add guard port
            if (port.guardPort() != "") {
                NetlistPort* guardPort =
                    new NetlistPort(port.guardPort(), "1", 1, BIT, OUT, *block);
                mapFUGuardPort(*newPort, *guardPort);
            }
        }
 
        // add opcode port
        if (fuImplementation.opcodePort() != "") {
            NetlistPort* opcodePort = new NetlistPort(
                fuImplementation.opcodePort(),
                Conversion::toString(opcodePortWidth(*entry, warningStream)),
                opcodePortWidth(*entry, warningStream), BIT_VECTOR, IN, *block);
            mapFUOpcodePort(*block, *opcodePort);
        }
 
        // add external ports
        addFUExternalPortsToNetlist(
            fuImplementation, coreBlock, *block, *adfFU);
 
        // add clock port
        if (fuImplementation.clkPort() != "") {
            NetlistPort* clkPort = new NetlistPort(
                fuImplementation.clkPort(), "1", 1, BIT, IN, *block);
            mapClockPort(*block, *clkPort);
            // connect clock port
            NetlistPort& tlClkPort = this->clkPort(coreBlock);
            coreBlock.netlist().connect(*clkPort, tlClkPort);
        }
 
        // add reset port
        if (fuImplementation.rstPort() != "") {
            NetlistPort* rstPort = new NetlistPort(
                fuImplementation.rstPort(), "1", 1, BIT, IN, *block);
            mapResetPort(*block, *rstPort);
            // connect reset port
            NetlistPort& tlRstPort = this->rstPort(coreBlock);
            coreBlock.netlist().connect(*rstPort, tlRstPort);
        }
 
        // add global lock port
        if (fuImplementation.glockPort() != "") {
            NetlistPort* glockPort = new NetlistPort(
                fuImplementation.glockPort(), "1", 1, BIT, IN, *block);
            mapGlobalLockPort(*block, *glockPort);
        }
 
        // add global lock request port
        if (fuImplementation.glockReqPort() != "") {
            NetlistPort* glockReqPort = new NetlistPort(
                fuImplementation.glockReqPort(), "1", 1, BIT, OUT, *block);
            mapGlobalLockRequestPort(*block, *glockReqPort);
        }
    }

References __func__, addFUExternalPortsToNetlist(), ProGe::NetlistBlock::addSubBlock(), ProGe::ProGeContext::adf(), HDB::FUArchitecture::architecture(), HDB::FUEntry::architecture(), HDB::FUPortImplementation::architecturePort(), HDB::FUImplementation::architecturePort(), HDB::FUImplementation::architecturePortCount(), ProGe::BIT, ProGe::BIT_VECTOR, calculateAddressWidth(), checkInstanceName(), HDB::HWBlockImplementation::clkPort(), clkPort(), ProGe::Netlist::connect(), context_, Exception::errorMessage(), findCorrespondingPort(), FU_NAME_PREFIX, HDB::HDBManager::fuByEntryID(), fuEntryMap_, TTAMachine::Machine::functionUnitNavigator(), HDB::HWBlockImplementation::glockPort(), glockPort(), HDB::FUImplementation::glockReqPort(), glockReqPort(), HDB::FUPortImplementation::guardPort(), TTAMachine::FunctionUnit::hasAddressSpace(), HDB::FUEntry::hasArchitecture(), HDB::FUEntry::hasImplementation(), TTAMachine::Machine::Navigator< ComponentType >::hasItem(), HDB::HDBRegistry::hdb(), IDF::UnitImplementationLocation::hdbFile(), IDF::UnitImplementationLocation::id(), HDB::FUEntry::implementation(), ProGe::IN, HDB::HDBRegistry::instance(), isLSU(), isParameterizable(), TTAMachine::FUPort::isTriggering(), TTAMachine::Machine::Navigator< ComponentType >::item(), HDB::PortImplementation::loadPort(), loadPort(), mapClockPort(), mapFUGuardPort(), mapFUOpcodePort(), mapGlobalLockPort(), mapGlobalLockRequestPort(), mapLoadPort(), mapNetlistBlock(), mapNetlistPort(), mapResetPort(), HDB::HWBlockImplementation::moduleName(), HDB::Parameter::name, HDB::PortImplementation::name(), TTAMachine::Component::name(), ProGe::NetlistBlock::netlist(), HDB::FUImplementation::opcodePort(), opcodePortWidth(), ProGe::OUT, HDB::FUImplementation::parameter(), HDB::FUImplementation::parameterCount(), HDB::FUArchitecture::portDirection(), HDB::HWBlockImplementation::rstPort(), rstPort(), ProGe::NetlistBlock::setParameter(), TTAMachine::BaseFUPort::setWidth(), Conversion::toString(), translateDirection(), HDB::Parameter::type, IDF::UnitImplementationLocation::unitName(), HDB::Parameter::value, TTAMachine::BaseFUPort::width(), and HDB::FUPortImplementation::widthFormula().

Referenced by generate().

addGCUToNetlist()

void ProGe::NetlistGenerator::addGCUToNetlist ( NetlistBlock &  toplevelBlock, int  imemWidthInMAUs  )

private

Adds the global control unit to the netlist as sub-block of the given top-level block.

Parameters

toplevelBlock	The top-level block of the netlist.
imemWidthInMAUs	Width of the instruction memory in MAUs.

Definition at line 692 of file NetlistGenerator.cc.

                                                          {
        if (imemWidthInMAUs != 4 && context_.adf().isRISCVMachine()) {
            throw InvalidData(__FILE__, __LINE__, __func__,
                "Imem width fixed to 4 MAUs for RISC-V machines");
        } else if (imemWidthInMAUs != 1 && !context_.adf().isRISCVMachine()) {
            throw InvalidData(__FILE__, __LINE__, __func__,
                "Imem width is currently fixed to 1 MAU");
        }
        Netlist& netlist = toplevelBlock.netlist();
 
        Parameter coreIdParam("core_id", "integer", "0", "0");
        toplevelBlock.addParameter(coreIdParam);
 
        NetlistPort* tlClkPort =
            new InBitPort(CLOCK_PORT_NAME, toplevelBlock, SignalType::CLOCK);
        NetlistPort* tlRstPort = new InBitPort(RESET_PORT_NAME, toplevelBlock,
            Signal(SignalType::RESET, ActiveState::LOW));
 
        // Instruction fetch bus //
        NetlistPort* tlBusyPort = new InBitPort(BUSY_PORT_NAME,
            Signal(SignalType::READ_REQUEST_READY, ActiveState::LOW));
        NetlistPort* tlReadEnablePort = new OutBitPort(READ_ENABLE_PORT_NAME,
            Signal(SignalType::READ_REQUEST, ActiveState::LOW));
        NetlistPort* tlAddressPort = new OutPort(ADDRESS_PORT_NAME,
            IMEMADDRWIDTH, BIT_VECTOR, Signal(SignalType::ADDRESS));
        NetlistPort* tlDataPort = new InPort(DATA_PORT_NAME, IMEMWIDTHFORMULA,
            BIT_VECTOR, Signal(SignalType::FETCHBLOCK));
        NetlistPortGroup* toplevelInstructionLine =
            new NetlistPortGroup(SignalGroupType::INSTRUCTION_LINE, tlBusyPort,
                tlReadEnablePort, tlAddressPort, tlDataPort);
        toplevelBlock.addPortGroup(toplevelInstructionLine);
 
        NetlistPort* tlLockStatusPort = new NetlistPort(LOCK_STATUS_PORT_NAME,
            "1", BIT, OUT, toplevelBlock, SignalType::CORE_HALT_STATUS);
 
        mapClockPort(toplevelBlock, *tlClkPort);
        mapResetPort(toplevelBlock, *tlRstPort);
 
        // add ifetch block
        ControlUnit* gcu = context_.adf().controlUnit();
        instructionFetch_ = new NetlistBlock(
            context_.coreEntityName() + "_" + IFETCH_BLOCK_NAME, "inst_fetch");
        toplevelBlock.addSubBlock(instructionFetch_);
        NetlistPort* ifetchClkPort =
            new NetlistPort(CLOCK_PORT_NAME, "1", BIT, IN, *instructionFetch_);
        NetlistPort* ifetchRstPort =
            new NetlistPort(RESET_PORT_NAME, "1", BIT, IN, *instructionFetch_);
        NetlistPort* ifetchRAOutPort = new NetlistPort(RA_OUT_PORT_NAME,
            IMEMADDRWIDTH, BIT_VECTOR, OUT, *instructionFetch_);
        raOutPort_ = ifetchRAOutPort;
        NetlistPort* ifetchRAInPort = new NetlistPort(
            RA_IN_PORT_NAME, IMEMADDRWIDTH, BIT_VECTOR, IN, *instructionFetch_);
        raInPort_ = ifetchRAInPort;
 
        NetlistPort* ifetchBusyPort = new InBitPort(BUSY_PORT_NAME,
            Signal(SignalType::READ_REQUEST_READY, ActiveState::LOW));
        NetlistPort* ifetchReadEnablePort =
            new OutBitPort(READ_ENABLE_PORT_NAME,
                Signal(SignalType::READ_REQUEST, ActiveState::LOW));
        NetlistPort* ifetchAddressPort = new OutPort(ADDRESS_PORT_NAME,
            IMEMADDRWIDTH, BIT_VECTOR, Signal(SignalType::ADDRESS));
        NetlistPort* ifetchDataPort = new InPort(DATA_PORT_NAME,
            IMEMWIDTHFORMULA, BIT_VECTOR, Signal(SignalType::FETCHBLOCK));
        NetlistPortGroup* ifetchInstructionLine = new NetlistPortGroup(
            SignalGroupType::INSTRUCTION_LINE, ifetchBusyPort,
            ifetchReadEnablePort, ifetchAddressPort, ifetchDataPort);
        instructionFetch_->addPortGroup(ifetchInstructionLine);
 
        NetlistPort* ifetchPCInPort = new NetlistPort(
            PC_IN_PORT_NAME, IMEMADDRWIDTH, BIT_VECTOR, IN, *instructionFetch_);
        NetlistPort* ifetchPCLoadPort = new NetlistPort(
            PC_LOAD_PORT_NAME, "1", BIT, IN, *instructionFetch_);
        NetlistPort* ifetchRALoadPort = new NetlistPort(
            RA_LOAD_PORT_NAME, "1", BIT, IN, *instructionFetch_);
        NetlistPort* ifetchPCOpcodePort = new NetlistPort(PC_OPCODE_PORT_NAME,
            Conversion::toString(opcodePortWidth(*gcu)), opcodePortWidth(*gcu),
            BIT_VECTOR, IN, *instructionFetch_);
        NetlistPort* ifetchFetchPort =
            new NetlistPort(FETCH_PORT_NAME, "1", BIT, IN, *instructionFetch_);
        NetlistPort* ifetchGlockPort = new NetlistPort(
            GLOBAL_LOCK_PORT_NAME, "1", BIT, OUT, *instructionFetch_);
        NetlistPort* ifetchFetchBlockPort =
            new NetlistPort(FETCHBLOCK_PORT_NAME, IMEMWIDTHFORMULA, BIT_VECTOR,
                OUT, *instructionFetch_);
 
        // connect ifetch to toplevel
        netlist.connect(*tlClkPort, *ifetchClkPort);
        netlist.connect(*tlRstPort, *ifetchRstPort);
 
        netlist.connect(*toplevelInstructionLine, *ifetchInstructionLine);
 
        if (gcu->operationPortCount() > 0) {
            mapNetlistPort(*gcu->triggerPort(), *ifetchPCInPort);
        }
 
        // Add non-standard GCU ports to the block.
        for (int i = 0; i < gcu->portCount(); i++) {
            Port* port = gcu->port(i);
            if (gcu->returnAddressPort()->name() == port->name()) {
                continue;
            }
            if (!netlistPortIsMapped(*port)) {
                Direction dir;
                if (port->isInput()) {
                    dir = IN;
                } else if (port->isOutput()) {
                    dir = OUT;
                } else {
                    assert(false && "Unconneced ADF port.");
                }
                // Data port
                NetlistPort* dataPort = new NetlistPort(port->name() + "_data",
                    Conversion::toString(port->width()), BIT_VECTOR, dir,
                    *instructionFetch_);
                mapNetlistPort(*port, *dataPort);
 
                // Load port if port is input
                if (port->isInput()) {
                    NetlistPort* loadPort =
                        new NetlistPort(port->name() + "_load", "1", BIT, dir,
                            *instructionFetch_);
                    mapLoadPort(*dataPort, *loadPort);
                }
            }
        }
 
        // add decompressor block
        NetlistBlock* decompressorBlock = new NetlistBlock(
            context_.coreEntityName() + "_" + DECOMPRESSOR_BLOCK_NAME,
            "decomp");
        instructionDecompressor_ = decompressorBlock;
        toplevelBlock.addSubBlock(decompressorBlock);
        NetlistPort* decFetchPort =
            new NetlistPort(FETCH_PORT_NAME, "1", BIT, OUT, *decompressorBlock);
        NetlistPort* decLockPort =
            new NetlistPort(LOCK_PORT_NAME, "1", BIT, IN, *decompressorBlock);
        NetlistPort* decFetchBlockPort = new NetlistPort(FETCHBLOCK_PORT_NAME,
            IMEMWIDTHFORMULA, BIT_VECTOR, IN, *decompressorBlock);
        NetlistPort* decClkPort =
            new NetlistPort(CLOCK_PORT_NAME, "1", BIT, IN, *decompressorBlock);
        NetlistPort* decRstPort =
            new NetlistPort(RESET_PORT_NAME, "1", BIT, IN, *decompressorBlock);
        NetlistPort* decIWordPort = new NetlistPort(INSTRUCTIONWORD_PORT_NAME,
            INSTRUCTIONWIDTH, BIT_VECTOR, OUT, *decompressorBlock);
        NetlistPort* decGlockPort = new NetlistPort(
            GLOBAL_LOCK_PORT_NAME, "1", BIT, OUT, *decompressorBlock);
        NetlistPort* decLockReqPort = new NetlistPort(
            LOCK_REQUEST_PORT_NAME, "1", BIT, IN, *decompressorBlock);
 
        // connect ifetch to decompressor
        netlist.connect(*ifetchFetchPort, *decFetchPort);
        netlist.connect(*ifetchGlockPort, *decLockPort);
        netlist.connect(*ifetchFetchBlockPort, *decFetchBlockPort);
 
        // connect toplevel to decompressor
        netlist.connect(*tlClkPort, *decClkPort);
        netlist.connect(*tlRstPort, *decRstPort);
 
        // add decoder block
        NetlistBlock* decoderBlock = new NetlistBlock(
            context_.coreEntityName() + "_" + DECODER_BLOCK_NAME,
            "inst_decoder");
        toplevelBlock.addSubBlock(decoderBlock);
        instructionDecoder_ = decoderBlock;
        NetlistPort* decodIWordPort = new NetlistPort(DECODER_INSTR_WORD_PORT,
            INSTRUCTIONWIDTH, BIT_VECTOR, IN, *decoderBlock);
        NetlistPort* decodPCLoadPort =
            new NetlistPort(DECODER_PC_LOAD_PORT, "1", BIT, OUT, *decoderBlock);
        NetlistPort* decodRALoadPort =
            new NetlistPort(DECODER_RA_LOAD_PORT, "1", BIT, OUT, *decoderBlock);
        NetlistPort* decodPCOpcodePort = new NetlistPort(DECODER_PC_OPCODE_PORT,
            Conversion::toString(opcodePortWidth(*gcu)), opcodePortWidth(*gcu),
            BIT_VECTOR, OUT, *decoderBlock);
        NetlistPort* decodLockPort = new NetlistPort(
            DECODER_LOCK_REQ_IN_PORT, "1", BIT, IN, *decoderBlock);
        NetlistPort* decodLockReqPort = new NetlistPort(
            DECODER_LOCK_REQ_OUT_PORT, "1", BIT, OUT, *decoderBlock);
        NetlistPort* decodClkPort =
            new NetlistPort(DECODER_CLOCK_PORT, "1", BIT, IN, *decoderBlock);
        NetlistPort* decodRstPort =
            new NetlistPort(DECODER_RESET_PORT, "1", BIT, IN, *decoderBlock);
        NetlistPort* decodLockedPort = new NetlistPort(
            DECODER_LOCK_STATUS_PORT, "1", BIT, OUT, *decoderBlock);
 
        // connect decoder to decompressor
        netlist.connect(*decIWordPort, *decodIWordPort);
        netlist.connect(*decGlockPort, *decodLockPort);
        netlist.connect(*decLockReqPort, *decodLockReqPort);
 
        // connect decoder to top-level
        netlist.connect(*decodClkPort, *tlClkPort);
        netlist.connect(*decodRstPort, *tlRstPort);
 
        // connect decoder to ifetch
        netlist.connect(*decodPCLoadPort, *ifetchPCLoadPort);
        netlist.connect(*decodRALoadPort, *ifetchRALoadPort);
        netlist.connect(*decodPCOpcodePort, *ifetchPCOpcodePort);
 
        // connect lock status signal port
        netlist.connect(*tlLockStatusPort, *decodLockedPort);
 
        Netlist::connectClocks(toplevelBlock);
        Netlist::connectResets(toplevelBlock);
    }

References __func__, ProGe::NetlistBlock::addParameter(), ProGe::NetlistBlock::addPortGroup(), ProGe::ADDRESS, ADDRESS_PORT_NAME, ProGe::NetlistBlock::addSubBlock(), ProGe::ProGeContext::adf(), assert, ProGe::BIT, ProGe::BIT_VECTOR, BUSY_PORT_NAME, ProGe::CLOCK, CLOCK_PORT_NAME, ProGe::Netlist::connect(), ProGe::Netlist::connectClocks(), ProGe::Netlist::connectResets(), context_, TTAMachine::Machine::controlUnit(), ProGe::CORE_HALT_STATUS, ProGe::ProGeContext::coreEntityName(), DATA_PORT_NAME, DECODER_BLOCK_NAME, DECODER_CLOCK_PORT, DECODER_INSTR_WORD_PORT, DECODER_LOCK_REQ_IN_PORT, DECODER_LOCK_REQ_OUT_PORT, DECODER_LOCK_STATUS_PORT, DECODER_PC_LOAD_PORT, DECODER_PC_OPCODE_PORT, DECODER_RA_LOAD_PORT, DECODER_RESET_PORT, DECOMPRESSOR_BLOCK_NAME, FETCH_PORT_NAME, ProGe::FETCHBLOCK, FETCHBLOCK_PORT_NAME, GLOBAL_LOCK_PORT_NAME, IFETCH_BLOCK_NAME, IMEMADDRWIDTH, IMEMWIDTHFORMULA, ProGe::IN, ProGe::INSTRUCTION_LINE, instructionDecoder_, instructionDecompressor_, instructionFetch_, INSTRUCTIONWIDTH, INSTRUCTIONWORD_PORT_NAME, TTAMachine::Port::isInput(), TTAMachine::Port::isOutput(), TTAMachine::Machine::isRISCVMachine(), loadPort(), LOCK_PORT_NAME, LOCK_REQUEST_PORT_NAME, LOCK_STATUS_PORT_NAME, ProGe::LOW, mapClockPort(), mapLoadPort(), mapNetlistPort(), mapResetPort(), TTAMachine::Port::name(), ProGe::NetlistBlock::netlist(), netlistPortIsMapped(), opcodePortWidth(), TTAMachine::FunctionUnit::operationPortCount(), ProGe::OUT, PC_IN_PORT_NAME, PC_LOAD_PORT_NAME, PC_OPCODE_PORT_NAME, TTAMachine::FunctionUnit::port(), TTAMachine::Unit::portCount(), RA_IN_PORT_NAME, RA_LOAD_PORT_NAME, RA_OUT_PORT_NAME, raInPort_, raOutPort_, READ_ENABLE_PORT_NAME, ProGe::READ_REQUEST, ProGe::READ_REQUEST_READY, ProGe::RESET, RESET_PORT_NAME, TTAMachine::ControlUnit::returnAddressPort(), Conversion::toString(), TTAMachine::FunctionUnit::triggerPort(), and TTAMachine::Port::width().

Referenced by generate().

Here is the call graph for this function:

addGeneratableFUsToNetlist()

GeneratableFUNetlistBlock * ProGe::NetlistGenerator::addGeneratableFUsToNetlist ( const IDF::FUGenerated &  fug, NetlistBlock &  netlistBlock  )

private

Definition at line 898 of file NetlistGenerator.cc.

                                                            {
 
        std::string fuName = "fu_" + fug.name();
        std::transform(fuName.begin(), fuName.end(), fuName.begin(), ::tolower);
 
        GeneratableFUNetlistBlock* block = new GeneratableFUNetlistBlock(
            fuName, fuName + "_generated", *this);
        coreBlock.addSubBlock(block);
 
        FunctionUnit* fu =
            context_.adf().functionUnitNavigator().item(fug.name());
 
        mapNetlistBlock(*fu, *block);
 
        // add clock port
        NetlistPort* clkPort = new NetlistPort("clk", "1", 1, BIT, IN, *block);
        mapClockPort(*block, *clkPort);
        // connect clock port
        NetlistPort& tlClkPort = this->clkPort(coreBlock);
        coreBlock.netlist().connect(*clkPort, tlClkPort);
 
        // add reset port
        NetlistPort* rstPort = new NetlistPort("rstx", "1", 1, BIT, IN, *block);
        mapResetPort(*block, *rstPort);
        // connect reset port
        NetlistPort& tlRstPort = this->rstPort(coreBlock);
        coreBlock.netlist().connect(*rstPort, tlRstPort);
 
        // add global lock port
        NetlistPort* glockPort =
            new NetlistPort("glock_in", "1", 1, BIT, IN, *block);
        mapGlobalLockPort(*block, *glockPort);
 
        // opcode port.
        int opcodeWidth = static_cast<int>(std::ceil(
            std::log2(fu->operationCount())));
        if (fu->operationCount() > 1) {
            NetlistPort* opcodePort = new NetlistPort("operation_in",
                std::to_string(opcodeWidth), BIT_VECTOR, IN, *block);
            mapFUOpcodePort(*block, *opcodePort);
        }
 
        // global lock request port
        NetlistPort* glockReqPort = new NetlistPort(
            "glockreq_out", "1", 1, BIT, OUT, *block);
        mapGlobalLockRequestPort(*block, *glockReqPort);
 
        // operand ports.
        for (int i = 0; i < fu->portCount(); ++i) {
            FUPort* adfPort = dynamic_cast<FUPort*>(fu->port(i));
 
            if (adfPort->isInput()) {
                block->addInOperand(adfPort, i);
            } else {
                block->addOutOperand(adfPort);
            }
        }
 
        return block;
    }

References ProGe::GeneratableFUNetlistBlock::addInOperand(), ProGe::GeneratableFUNetlistBlock::addOutOperand(), ProGe::NetlistBlock::addSubBlock(), ProGe::ProGeContext::adf(), ProGe::BIT, ProGe::BIT_VECTOR, clkPort(), ProGe::Netlist::connect(), context_, TTAMachine::Machine::functionUnitNavigator(), GeneratableFUNetlistBlock, glockPort(), glockReqPort(), ProGe::IN, TTAMachine::Port::isInput(), TTAMachine::Machine::Navigator< ComponentType >::item(), mapClockPort(), mapFUOpcodePort(), mapGlobalLockPort(), mapGlobalLockRequestPort(), mapNetlistBlock(), mapResetPort(), IDF::FUGenerated::name(), ProGe::NetlistBlock::netlist(), TTAMachine::FunctionUnit::operationCount(), ProGe::OUT, TTAMachine::FunctionUnit::port(), TTAMachine::Unit::portCount(), and rstPort().

Referenced by generate().

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addIUToNetlist()

void ProGe::NetlistGenerator::addIUToNetlist ( const ProGeOptions &  options, const IDF::RFImplementationLocation &  location, NetlistBlock &  netlistBlock  )

private

Adds the IU identified by the given RFImplementationLocation instance to the netlist.

Parameters

location	The RFImplementationLocation instance.
netlist	The netlist.

Exceptions

IOException	If the HDB that contains the implementation cannot be accessed.
InvalidData	If the MachineImplementation instance or HDB is erroneous.

Definition at line 1318 of file NetlistGenerator.cc.

                                    {
        if (!context_.adf().immediateUnitNavigator().hasItem(
                location.unitName())) {
            string errorMsg = "ADF does not contain immediate unit '" +
                              location.unitName() + "' referred to in IDF.";
            throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
        }
        ImmediateUnit* iu =
            context_.adf().immediateUnitNavigator().item(location.unitName());
        addBaseRFToNetlist(options, *iu, location, netlistBlock,
            IU_NAME_PREFIX);
    }

References __func__, addBaseRFToNetlist(), ProGe::ProGeContext::adf(), context_, TTAMachine::Machine::Navigator< ComponentType >::hasItem(), TTAMachine::Machine::immediateUnitNavigator(), TTAMachine::Machine::Navigator< ComponentType >::item(), IU_NAME_PREFIX, netlistBlock(), options, and IDF::UnitImplementationLocation::unitName().

Referenced by generate().

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addRFToNetlist()

void ProGe::NetlistGenerator::addRFToNetlist ( const ProGeOptions &  options, const IDF::RFImplementationLocation &  location, NetlistBlock &  netlistBlock  )

private

Adds the RF identified by the given RFImplementationLocation instance to the netlist.

Parameters

location	The RFImplementationLocation instance.
netlist	The netlist.

Exceptions

IOException	If the HDB that contains the implementation cannot be accessed.
InvalidData	If the MachineImplementation instance or HDB is erroneous.

Definition at line 1289 of file NetlistGenerator.cc.

                                    {
        if (!context_.adf().registerFileNavigator().hasItem(
                location.unitName())) {
            string errorMsg = "ADF does not contain register file '" +
                              location.unitName() + "' referred to in IDF.";
            throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
        }
        RegisterFile* rf =
            context_.adf().registerFileNavigator().item(location.unitName());
        addBaseRFToNetlist(options, *rf, location, netlistBlock,
            RF_NAME_PREFIX);
    }

References __func__, addBaseRFToNetlist(), ProGe::ProGeContext::adf(), context_, TTAMachine::Machine::Navigator< ComponentType >::hasItem(), TTAMachine::Machine::Navigator< ComponentType >::item(), netlistBlock(), options, TTAMachine::Machine::registerFileNavigator(), RF_NAME_PREFIX, and IDF::UnitImplementationLocation::unitName().

Referenced by generate().

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calculateAddressWidth()

unsigned int ProGe::NetlistGenerator::calculateAddressWidth ( TTAMachine::FunctionUnit const *  fu ) const

private

Calculates the address width of an address space in FU

Exceptions

Invalid

data If the FU doesn't have an address space or the address space is invalid

Definition at line 1856 of file NetlistGenerator.cc.

                                                {
        if (fu->hasAddressSpace() && fu->addressSpace() != NULL) {
            AddressSpace* AS = fu->addressSpace();
            unsigned int highestAddr = AS->end();
            unsigned int lowestAddr = AS->start();
            if (highestAddr == 0 || lowestAddr >= highestAddr) {
                string errorMessage = "Invalid address space";
                throw InvalidData(
                    __FILE__, __LINE__, __func__, errorMessage.c_str());
            }
            return static_cast<unsigned int>(ceil(log(highestAddr) / log(2)));
        } else {
            string errorMessage = "Tried to resolve address space width "
                                  "from FU '" +
                                  fu->name() +
                                  "' that doesn't have address space";
            throw InvalidData(
                __FILE__, __LINE__, __func__, errorMessage.c_str());
        }
        // never reached
        return 0;
    }

References __func__, TTAMachine::FunctionUnit::addressSpace(), TTAMachine::AddressSpace::end(), TTAMachine::FunctionUnit::hasAddressSpace(), TTAMachine::Component::name(), and TTAMachine::AddressSpace::start().

Referenced by addFUToNetlist().

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checkInstanceName()

TCEString ProGe::NetlistGenerator::checkInstanceName ( const TCEString &  baseInstanceName, const TCEString &  moduleName  ) const

private

Return fixed instance name if instance name is equal to module name.

Parameters

baseInstanceName	Default name for a component instance
moduleName	Name for the component module defined in HDB

Returns

Instance name differing from the module name.

Definition at line 2080 of file NetlistGenerator.cc.

                                                                              {
 
        TCEString newInstanceName;
        if (baseInstanceName.lower() == moduleName.lower()) {
            newInstanceName = baseInstanceName + INSTANCE_SUFFIX;
        } else {
            newInstanceName = baseInstanceName;
        }
        return newInstanceName;
    }

References INSTANCE_SUFFIX, and TCEString::lower().

Referenced by addBaseRFToNetlist(), and addFUToNetlist().

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clkPort()

NetlistPort & ProGe::NetlistGenerator::clkPort

(

const NetlistBlock &

block

)

const

Returns the clock port of the given block in the netlist.

Parameters

block

The block in the netlist.

Returns

The clock port of the given block.

Exceptions

InstanceNotFound

If the netlist does not contain the port.

Definition at line 425 of file NetlistGenerator.cc.

                                                             {
        try {
            return *MapTools::valueForKey<NetlistPort*>(clkPorts_, &block);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format("Cannot find clock port in netlist block "
                               "instance name: "
                               "'%s', module name: '%s'") %
                    block.instanceName() % block.moduleName())
                    .str());
        }
    }

References __func__, clkPorts_, ProGe::BaseNetlistBlock::instanceName(), MapTools::keyForValue(), and ProGe::BaseNetlistBlock::moduleName().

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGeneratableFUsToNetlist(), DefaultICDecoderGenerator::addRV32MicroCode(), DefaultICDecoderGenerator::generateDebuggerCode(), and mapClockPort().

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context()

const ProGeContext & ProGe::NetlistGenerator::context ( ) const

inline

Definition at line 125 of file NetlistGenerator.hh.

{ return context_; }

References context_.

Referenced by DefaultICDecoderGenerator::generate().

findCorrespondingPort()

TTAMachine::FUPort & ProGe::NetlistGenerator::findCorrespondingPort ( const TTAMachine::FunctionUnit &  fuToSearch, const TTAMachine::FunctionUnit &  origFU, const std::string &  portName  )

staticprivate

Finds the corresponding ports from the given function units.

Parameters

fuToSearch	The FU that is searched for the corresponding port.
origFU	The original FU.
portName	Name of the port in the original FU.

Returns

The corresponding port in fuToSearch FU.

Exceptions

InstanceNotFound

If there is no corresponding port.

Definition at line 1963 of file NetlistGenerator.cc.

                                                                         {
        FUPort* correspondingPort = NULL;
        assert(origFU.hasOperationPort(portName));
        const FUPort* origPort = origFU.operationPort(portName);
        for (int i = 0; i < origFU.operationCount(); i++) {
            HWOperation* origOperation = origFU.operation(i);
            string opName = origOperation->name();
            if (fuToSearch.hasOperation(opName)) {
                HWOperation* operation = fuToSearch.operation(opName);
                if (!origOperation->isBound(*origPort)) {
                    continue;
                }
                int origIO = origOperation->io(*origPort);
                FUPort* port = operation->port(origIO);
                if (port == NULL) {
                    throw InstanceNotFound(__FILE__, __LINE__, __func__);
                }
                if (correspondingPort == NULL) {
                    correspondingPort = port;
                } else if (correspondingPort != port) {
                    throw InstanceNotFound(__FILE__, __LINE__, __func__);
                }
            }
        }
 
        if (correspondingPort == NULL) {
            THROW_EXCEPTION(InstanceNotFound,
                std::string("Corresponding port for [") + portName +
                    "] defined in HDB was not found in FU of ADF: [" +
                    fuToSearch.name() + "].");
        }
 
        return *correspondingPort;
    }

References __func__, assert, TTAMachine::FunctionUnit::hasOperation(), TTAMachine::FunctionUnit::hasOperationPort(), TTAMachine::HWOperation::io(), TTAMachine::HWOperation::isBound(), TTAMachine::HWOperation::name(), TTAMachine::Component::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), TTAMachine::FunctionUnit::operationPort(), TTAMachine::HWOperation::port(), and THROW_EXCEPTION.

Referenced by addFUToNetlist().

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fuEntry()

FUEntry & ProGe::NetlistGenerator::fuEntry

(

const std::string &

fuName

)

const

Returns the FU entry which was selected to represent the given FU.

Parameters

fuName

Name of the FU in ADF.

Returns

The FU entry.

Exceptions

InstanceNotFound

If the netlist is not created yet or if there was no FU entry for the given FU.

Definition at line 657 of file NetlistGenerator.cc.

                                                           {
        try {
            return *MapTools::valueForKey<FUEntry*>(fuEntryMap_, fuName);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                "Cannot find function unit entry from the netlist.");
        }
    }

References __func__, fuEntryMap_, and MapTools::keyForValue().

Referenced by isParameterizable().

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fuGuardPort()

NetlistPort & ProGe::NetlistGenerator::fuGuardPort

(

const NetlistPort &

fuPort

)

const

Returns the guard port of the given FU data port.

Parameters

fuPort

The FU data port.

Returns

The guard port.

Exceptions

InstanceNotFound

If the netlist does not contain the port.

Definition at line 402 of file NetlistGenerator.cc.

                                                                 {
        try {
            return *MapTools::valueForKey<NetlistPort*>(
                fuGuardPortMap_, &fuPort);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format(
                     "Cannot find guard port '%s' in instance name: '%s', "
                     "module name: '%s'") %
                    fuPort.name() % fuPort.parentBlock().instanceName() %
                    fuPort.parentBlock().moduleName())
                    .str());
        }
    }

References __func__, fuGuardPortMap_, ProGe::BaseNetlistBlock::instanceName(), MapTools::keyForValue(), ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistPort::name(), and ProGe::NetlistPort::parentBlock().

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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fuOpcodePort()

NetlistPort & ProGe::NetlistGenerator::fuOpcodePort

(

const NetlistBlock &

fuBlock

)

const

Returns the opcode port of the given FU.

Parameters

fuBlock

The FU.

Returns

The opcode port.

Exceptions

InstanceNotFound

If the given FU does not have an opcode port.

Definition at line 380 of file NetlistGenerator.cc.

                                                                    {
        try {
            return *MapTools::valueForKey<NetlistPort*>(
                fuOpcodePorts_, &fuBlock);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format("Cannot find opcode port in function unit "
                               "instance name: '%s',"
                               "module name: '%s'") %
                    fuBlock.instanceName() % fuBlock.moduleName())
                    .str());
        }
    }

References __func__, fuOpcodePorts_, ProGe::BaseNetlistBlock::instanceName(), MapTools::keyForValue(), and ProGe::BaseNetlistBlock::moduleName().

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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gcuReturnAddressInPort()

NetlistPort & ProGe::NetlistGenerator::gcuReturnAddressInPort

(

)

const

Returns the return address in port of GCU.

Returns

The return address in port.

Exceptions

InstanceNotFound

If GCU does not have the port.

Definition at line 551 of file NetlistGenerator.cc.

                                                   {
        if (raInPort_ != NULL) {
            return *raInPort_;
        } else {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                "Cannot find return address of in port of GCU");
        }
    }

References __func__, and raInPort_.

Referenced by DefaultICGenerator::addICToNetlist(), and DefaultICDecoderGenerator::generateDebuggerCode().

gcuReturnAddressOutPort()

NetlistPort & ProGe::NetlistGenerator::gcuReturnAddressOutPort

(

)

const

Returns the return address out port of GCU.

Returns

The return address out port.

Exceptions

InstanceNotFound

If GCU does not have the port.

Definition at line 567 of file NetlistGenerator.cc.

                                                    {
        if (raOutPort_ != NULL) {
            return *raOutPort_;
        } else {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                "Cannot find return address of out port of GCU");
        }
    }

References __func__, and raOutPort_.

Referenced by DefaultICGenerator::addICToNetlist().

generate()

NetlistBlock * ProGe::NetlistGenerator::generate	(	const ProGeOptions &	options,
		int	imemWidthInMAUs,
		TCEString	entityNameStr = TOPLEVEL_BLOCK_DEFAULT_NAME,
		std::ostream &	warningStream = std::cerr
	)

Generates the netlist block of the processor.

Parameters

imemWidthInMAUs	Width of instruction memory in MAUs.
entityNameStr	The name string used to make the netlist blocks uniquely named.

Returns

The newly generated netlist block representing a single TTA Core.

Exceptions

IOException	If some of the HDBs given in IDF cannot be accessed.
InvalidData	If HDB or IDF is invalid.
OutOfRange	If the given width of instruction memory is not positive
InstanceNotFound	Something missing missing from HDB.

Definition at line 188 of file NetlistGenerator.cc.

                                             {
        if (imemWidthInMAUs < 1) {
            string errorMsg =
                "Instruction memory width in MAUs must be positive.";
            throw OutOfRange(__FILE__, __LINE__, __func__, errorMsg);
        }
 
        // add toplevel block
        coreBlock_ = new NetlistBlock(entityNameStr, "tta_core");
        coreBlock_->addPackage(context_.coreEntityName() + "_globals");
        coreBlock_->addPackage(context_.coreEntityName() + "_imem_mau");
 
        // add GCU to the netlist
        addGCUToNetlist(*coreBlock_, imemWidthInMAUs);
 
        // add Genrated FUs to the toplevel netlist.
        for (auto fug : context_.idf().FUGenerations()) {
            addGeneratableFUsToNetlist(fug, *coreBlock_);
        }
 
        // add function units to the netlist
        for (int i = 0; i < context_.idf().fuImplementationCount(); i++) {
            IDF::FUImplementationLocation& location =
                context_.idf().fuImplementation(i);
            addFUToNetlist(location, *coreBlock_, warningStream);
        }
 
        // add register files to the netlist
        for (int i = 0; i < context_.idf().rfImplementationCount(); i++) {
            RFImplementationLocation& location =
                context_.idf().rfImplementation(i);
            addRFToNetlist(options, location, *coreBlock_);
        }
 
        // add immediate units to the netlist
        for (int i = 0; i < context_.idf().iuImplementationCount(); i++) {
            RFImplementationLocation& location =
                context_.idf().iuImplementation(i);
            addIUToNetlist(options, location, *coreBlock_);
        }
 
        plugin_.completeNetlist(*coreBlock_, *this);
 
        return coreBlock_;
    }

References __func__, addFUToNetlist(), addGCUToNetlist(), addGeneratableFUsToNetlist(), addIUToNetlist(), ProGe::NetlistBlock::addPackage(), addRFToNetlist(), ProGe::ICDecoderGeneratorPlugin::completeNetlist(), context_, coreBlock_, ProGe::ProGeContext::coreEntityName(), IDF::MachineImplementation::FUGenerations(), IDF::MachineImplementation::fuImplementation(), ProGe::ProGeContext::idf(), IDF::MachineImplementation::iuImplementation(), options, plugin_, and IDF::MachineImplementation::rfImplementation().

Referenced by ProGe::ProcessorGenerator::generateProcessor().

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glockPort()

NetlistPort & ProGe::NetlistGenerator::glockPort

(

const NetlistBlock &

block

)

const

Returns the global lock port of the given block in the netlist.

Parameters

block

The block in the netlist.

Returns

The global lock port of the given block.

Exceptions

InstanceNotFound

If the netlist does not contain the port.

Definition at line 477 of file NetlistGenerator.cc.

                                                               {
        try {
            return *MapTools::valueForKey<NetlistPort*>(glockPorts_, &block);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format("Cannot find global lock port in netlist block "
                               "instance name:"
                               " '%s', module name: '%s'") %
                    block.instanceName() % block.moduleName())
                    .str());
        }
    }

References __func__, glockPorts_, ProGe::BaseNetlistBlock::instanceName(), MapTools::keyForValue(), and ProGe::BaseNetlistBlock::moduleName().

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGeneratableFUsToNetlist(), DefaultDecoderGenerator::addGlockPortToDecoder(), and mapGlobalLockPort().

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glockReqPort()

NetlistPort & ProGe::NetlistGenerator::glockReqPort

(

const NetlistBlock &

block

)

const

Returns the global lock request port of the given block in the netlist.

Parameters

block

The block in the netlist.

Returns

The global lock request port of the given block.

Exceptions

InstanceNotFound

If the netlist does not contain the port.

Definition at line 510 of file NetlistGenerator.cc.

                                                                  {
        try {
            return *MapTools::valueForKey<NetlistPort*>(glockReqPorts_, &block);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format("Cannot find global lock request port in "
                               "netlist block "
                               "instance name: '%s', module name: '%s'") %
                    block.instanceName() % block.moduleName())
                    .str());
        }
    }

References __func__, glockReqPorts_, ProGe::BaseNetlistBlock::instanceName(), MapTools::keyForValue(), and ProGe::BaseNetlistBlock::moduleName().

Referenced by addFUToNetlist(), addGeneratableFUsToNetlist(), DefaultDecoderGenerator::addLockReqPortToDecoder(), and mapGlobalLockRequestPort().

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hasGlockPort()

bool ProGe::NetlistGenerator::hasGlockPort

(

const NetlistBlock &

block

)

const

Tells whether the given netlist block has a global lock port.

Parameters

block

The netlist block.

Returns

True if the block has a global lock port, otherwise false.

Definition at line 465 of file NetlistGenerator.cc.

                                                                       {
        return MapTools::containsKey(glockPorts_, &block);
    }

References MapTools::containsKey(), and glockPorts_.

Referenced by DefaultDecoderGenerator::addGlockPortToDecoder(), and DefaultDecoderGenerator::glockPortWidth().

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hasGlockReqPort()

bool ProGe::NetlistGenerator::hasGlockReqPort

(

const NetlistBlock &

block

)

const

Tells whether the given netlist block has global lock request port.

Parameters

block

The netlist block.

Returns

True if the block has a global lock request port, otherwise false.

Definition at line 497 of file NetlistGenerator.cc.

                                                                          {
        return MapTools::containsKey(glockReqPorts_, &block);
    }

References MapTools::containsKey(), and glockReqPorts_.

Referenced by DefaultDecoderGenerator::addLockReqPortToDecoder(), and DefaultDecoderGenerator::glockRequestWidth().

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hasOpcodePort()

bool ProGe::NetlistGenerator::hasOpcodePort

(

const NetlistPort &

port

)

const

Returns true if the given RF port has opcode port. Otherwise, returns false.

Definition at line 322 of file NetlistGenerator.cc.

                                                                      {
        return MapTools::containsKey(rfOpcodePortMap_, &port);
    }

References MapTools::containsKey(), and rfOpcodePortMap_.

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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immediateUnitWritePort()

NetlistPort & ProGe::NetlistGenerator::immediateUnitWritePort

(

const TTAMachine::ImmediateUnit &

iu

)

const

Returns a netlist port that is the write port of the given immediate unit.

Parameters

iu	The immediate unit.

Returns

The netlist port.

Exceptions

InstanceNotFound

If the port is not found.

Definition at line 532 of file NetlistGenerator.cc.

                                                 {
        try {
            return *MapTools::valueForKey<NetlistPort*>(iuPortMap_, &iu);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format("Cannot find immediate unit '%s' write port.") %
                    iu.name())
                    .str());
        }
    }

References __func__, iuPortMap_, MapTools::keyForValue(), and TTAMachine::Component::name().

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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inferLSUSignal()

Signal ProGe::NetlistGenerator::inferLSUSignal ( const std::string &  portName )

staticprivate

Definition at line 2151 of file NetlistGenerator.cc.

                                                                     {
        size_t pos = 0;
        if (((pos = portName.find("addr")) != std::string::npos)) {
            return SignalType::ADDRESS;
        } else if (((pos = portName.find("data")) != std::string::npos)) {
            if ((portName.find("_in", pos + 4)) != std::string::npos) {
                return SignalType::READ_DATA;
            } else if ((portName.find("_out", pos + 4)) != std::string::npos) {
                return SignalType::WRITE_DATA;
            }
        } else if (((pos = portName.find("mem_en")) != std::string::npos)) {
            if ((portName.find("_x", pos + 6)) != std::string::npos) {
                return Signal(SignalType::READ_WRITE_REQUEST, ActiveState::LOW);
            } else {
                return SignalType::READ_WRITE_REQUEST;
            }
        } else if (((pos = portName.find("wr_mask")) != std::string::npos)) {
            if ((portName.find("_x", pos + 7)) != std::string::npos) {
                return Signal(SignalType::WRITE_BITMASK, ActiveState::LOW);
            } else {
                return SignalType::WRITE_BITMASK;
            }
        } else if (((pos = portName.find("wr_en")) != std::string::npos)) {
            if ((portName.find("_x", pos + 5)) != std::string::npos) {
                return Signal(SignalType::WRITEMODE, ActiveState::LOW);
            } else {
                return SignalType::WRITEMODE;
            }
        }
        return SignalType::UNDEFINED;
    }

References ProGe::ADDRESS, ProGe::LOW, ProGe::READ_DATA, ProGe::READ_WRITE_REQUEST, ProGe::UNDEFINED, ProGe::WRITE_BITMASK, ProGe::WRITE_DATA, and ProGe::WRITEMODE.

Referenced by addFUExternalPortsToNetlist().

instructionDecoder()

NetlistBlock & ProGe::NetlistGenerator::instructionDecoder

(

)

const

Returns the instruction decoder block in the netlist.

Returns

The instruction decoder block.

Exceptions

InstanceNotFound

If there is no instruction decoder in the netlist.

Definition at line 600 of file NetlistGenerator.cc.

                                               {
        if (instructionDecoder_ == NULL) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                "Cannot find instruction decoder block from the netlist.");
        } else {
            return *instructionDecoder_;
        }
    }

References __func__, and instructionDecoder_.

Referenced by DefaultICDecoderGenerator::addRV32MicroCode(), DefaultDecoderGenerator::completeDecoderBlock(), DefaultICDecoderGenerator::generateDebuggerCode(), and DefaultDecoderGenerator::opcodeWidth().

instructionDecompressor()

NetlistBlock & ProGe::NetlistGenerator::instructionDecompressor

(

)

const

Returns the instruction decompressor block in the netlist.

Returns

The instruction decompressor block.

Exceptions

InstanceNotFound

If there is no instruction decompressor in the netlist.

Definition at line 636 of file NetlistGenerator.cc.

                                                    {
        if (instructionDecompressor_ == NULL) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                "Cannot find instruction decompressor block from the "
                "netlist.");
        } else {
            return *instructionDecompressor_;
        }
    }

References __func__, and instructionDecompressor_.

Referenced by DefaultICDecoderGenerator::addRV32MicroCode().

instructionFetch()

NetlistBlock & ProGe::NetlistGenerator::instructionFetch

(

)

const

Returns the instruction fetch block in the netlist.

Returns

The instruction fetch block.

Exceptions

InstanceNotFound

If there is no instruction fetch in the netlist.

Definition at line 617 of file NetlistGenerator.cc.

                                             {
        if (instructionFetch_ == NULL) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                "Cannot find instruction fetch block from the netlist.");
        } else {
            return *instructionFetch_;
        }
    }

References __func__, and instructionFetch_.

Referenced by DefaultICDecoderGenerator::addDummyIfetchDebugPorts(), DefaultICDecoderGenerator::addInstructioRegisterBypass(), DefaultICDecoderGenerator::addRV32MicroCode(), DefaultICDecoderGenerator::generate(), and DefaultICDecoderGenerator::generateDebuggerCode().

instructionMemory()

TTAMachine::AddressSpace & ProGe::NetlistGenerator::instructionMemory ( const TTAMachine::Machine &  machine )

staticprivate

Returns the address space that represents the instruction memory of the given machine.

Parameters

machine

The machine.

Returns

The address space.

Exceptions

IllegalMachine

If the machine does not have the instruction memory address space.

Definition at line 2041 of file NetlistGenerator.cc.

                                                                        {
        ControlUnit* cu = machine.controlUnit();
        if (cu == NULL) {
            string errorMsg = "The machine does not have a control unit.";
            throw IllegalMachine(__FILE__, __LINE__, __func__, errorMsg);
        }
 
        AddressSpace* iMem = cu->addressSpace();
        if (iMem == NULL) {
            string errorMsg =
                "The control unit does not have an address space.";
            throw IllegalMachine(__FILE__, __LINE__, __func__, errorMsg);
        }
 
        return *iMem;
    }

References __func__, TTAMachine::FunctionUnit::addressSpace(), TTAMachine::Machine::controlUnit(), and machine.

Referenced by instructionMemoryAddressWidth(), and instructionMemoryWidth().

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instructionMemoryAddressWidth()

int ProGe::NetlistGenerator::instructionMemoryAddressWidth ( const TTAMachine::Machine &  machine )

staticprivate

Explores the given machine for the width of the instruction memory address.

Parameters

machine

The machine.

Returns

The width of the instruction memory address.

Exceptions

IllegalMachine

If the machine is erroneous.

Definition at line 2009 of file NetlistGenerator.cc.

                                          {
        AddressSpace& iMem = instructionMemory(machine);
        return MathTools::requiredBits(iMem.end());
    }

References TTAMachine::AddressSpace::end(), instructionMemory(), machine, and MathTools::requiredBits().

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instructionMemoryWidth()

int ProGe::NetlistGenerator::instructionMemoryWidth ( const TTAMachine::Machine &  machine )

staticprivate

Explores the given machine for the width of the instruction memory.

Parameters

machine

The machine.

Returns

The width of the instruction memory.

Exceptions

IllegalMachine

If the machine is erroneous.

Definition at line 2023 of file NetlistGenerator.cc.

                                          {
        AddressSpace& iMem = instructionMemory(machine);
        return iMem.width();
    }

References instructionMemory(), machine, and TTAMachine::AddressSpace::width().

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isLSU()

bool ProGe::NetlistGenerator::isLSU ( const TTAMachine::FunctionUnit &  fu ) const

private

(Ugly) heursitics for identifying an LSU.

If it has an address space and implements a memory operation, it is an LSU

Parameters

fu	Function unit to be tested

Returns

Is the fu an LSU

Definition at line 2102 of file NetlistGenerator.cc.

                                                                       {
 
        if (!fu.hasAddressSpace()) {
            return false;
        }
 
        const int opCount = 18;
        TCEString ops[opCount] = {
            "ldw", "ldh", "ldq", "ldw2", "ldw4",
            "stw", "sth", "stq", "stw2", "stw4",
            "ld8", "ldu8", "ld16","ldu16", "ld32",
            "st8", "st16", "st32"
        };
 
        for (auto& op : ops) {
            if (fu.hasOperationLowercase(op)) {
                return true;
            }
        }
        return false;
    }

References TTAMachine::FunctionUnit::hasAddressSpace(), and TTAMachine::FunctionUnit::hasOperationLowercase().

Referenced by addFUToNetlist().

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isLSUDataPort()

bool ProGe::NetlistGenerator::isLSUDataPort ( const TTAMachine::FunctionUnit &  adfFU, const std::string &  portName  )

staticprivate

(Ugly) heuristics for identifying an LSU data memory port.

The identification is made by partial match of the port's name.

Parameters

portName

The port name given in HDB.

Returns

True if the port is LSU data memory port.

Definition at line 2132 of file NetlistGenerator.cc.

                                                                        {
 
        if (!adfFU.hasAddressSpace()) {
            return false;
        }
 
        static const std::set<std::string> magicWords{
            "addr", "data", "mem_en", "wr_en", "wr_mask"};
 
        for (auto magicWord : magicWords) {
            if (portName.find(magicWord) != std::string::npos) {
                return true;
            }
        }
 
        return false;
    }

References TTAMachine::FunctionUnit::hasAddressSpace().

Referenced by addFUExternalPortsToNetlist().

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isParameterizable()

bool ProGe::NetlistGenerator::isParameterizable ( const std::string &  paramName, const HDB::FUEntry *  fuEntry  ) const

private

Checks if the given parameter is defined parametrizable in the given FUImplementation

Parameters

paramName	Name of the parameter
fuImplementation	FUImplementation to be tested

Definition at line 1832 of file NetlistGenerator.cc.

                                                               {
        FUImplementation& fuImplementation = fuEntry->implementation();
 
        for (int i = 0; i < fuImplementation.architecturePortCount(); i++) {
 
            FUPortImplementation& port = fuImplementation.architecturePort(i);
            string widthFormula = port.widthFormula();
            if (widthFormula == paramName) {
                return fuEntry->architecture().hasParameterizedWidth(
                    port.architecturePort());
            }
        }
        return false;
    }

References HDB::FUEntry::architecture(), HDB::FUPortImplementation::architecturePort(), HDB::FUImplementation::architecturePort(), HDB::FUImplementation::architecturePortCount(), fuEntry(), HDB::FUArchitecture::hasParameterizedWidth(), HDB::FUEntry::implementation(), and HDB::FUPortImplementation::widthFormula().

Referenced by addFUToNetlist().

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loadPort()

NetlistPort & ProGe::NetlistGenerator::loadPort

(

const NetlistPort &

port

)

const

Returns the load enable port of the given port in the netlist.

Parameters

port	The architectural port in the netlist.

Returns

The load enable port of the given port.

Exceptions

InstanceNotFound

If the netlist does not contain the port.

Definition at line 304 of file NetlistGenerator.cc.

                                                            {
        try {
            return *MapTools::valueForKey<NetlistPort*>(loadPortMap_, &port);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format(
                     "Cannot find load port '%s' in instance name: '%s', "
                     "module name: '%s'") %
                    port.name() % port.parentBlock().instanceName() %
                    port.parentBlock().moduleName())
                    .str());
        }
    }

References __func__, ProGe::BaseNetlistBlock::instanceName(), MapTools::keyForValue(), loadPortMap_, ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistPort::name(), and ProGe::NetlistPort::parentBlock().

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), DefaultDecoderGenerator::completeDecoderBlock(), and mapLoadPort().

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mapClockPort()

void ProGe::NetlistGenerator::mapClockPort ( const NetlistBlock &  block, NetlistPort &  clkPort  )

private

Maps the given clock port for the given block.

Parameters

block	The netlist block.
clkPort	The clock port of the block.

Definition at line 1733 of file NetlistGenerator.cc.

                                                         {
 
        assert(!MapTools::containsKey(clkPorts_, &block));
        clkPorts_.insert(
            std::pair<const NetlistBlock*, NetlistPort*>(&block, &clkPort));
    }

References assert, clkPort(), clkPorts_, and MapTools::containsKey().

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), and addGeneratableFUsToNetlist().

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mapFUGuardPort()

void ProGe::NetlistGenerator::mapFUGuardPort ( const NetlistPort &  dataPort, NetlistPort &  guardPort  )

private

Maps the given guard port for the given FU data port.

Parameters

dataPort	The data port.
guardPort	The guard port.

Definition at line 1803 of file NetlistGenerator.cc.

                                                             {
 
        assert(!MapTools::containsKey(fuGuardPortMap_, &dataPort));
        fuGuardPortMap_.insert(
            std::pair<const NetlistPort*, NetlistPort*>(&dataPort, &guardPort));
    }

References assert, MapTools::containsKey(), and fuGuardPortMap_.

Referenced by addFUToNetlist().

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mapFUOpcodePort()

void ProGe::NetlistGenerator::mapFUOpcodePort ( const NetlistBlock &  block, NetlistPort &  port  )

private

Maps the given opcode port for the given FU block.

Parameters

block	The FU block.
opcodePort	The opcode port of the FU block.

Definition at line 1719 of file NetlistGenerator.cc.

                                                      {
 
        assert(!MapTools::containsKey(fuOpcodePorts_, &block));
        fuOpcodePorts_.insert(
            std::pair<const NetlistBlock*, NetlistPort*>(&block, &port));
    }

References assert, MapTools::containsKey(), and fuOpcodePorts_.

Referenced by addFUToNetlist(), and addGeneratableFUsToNetlist().

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mapGlobalLockPort()

void ProGe::NetlistGenerator::mapGlobalLockPort ( const NetlistBlock &  block, NetlistPort &  glockPort  )

private

Maps the given global lock port for the given block.

Parameters

block	The netlist block.
glockPort	The global lock port of the block.

Definition at line 1761 of file NetlistGenerator.cc.

                                                           {
 
        assert(!MapTools::containsKey(glockPorts_, &block));
        glockPorts_.insert(
            std::pair<const NetlistBlock*, NetlistPort*>(&block, &glockPort));
    }

References assert, MapTools::containsKey(), glockPort(), and glockPorts_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), and addGeneratableFUsToNetlist().

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mapGlobalLockRequestPort()

void ProGe::NetlistGenerator::mapGlobalLockRequestPort	(	const NetlistBlock &	block,
		NetlistPort &	glockReqPort
	)

Maps the given global lock request port for the given block.

Parameters

block	The netlist block.
glockReqPort	The global lock request port of the block.

Definition at line 1775 of file NetlistGenerator.cc.

                                                              {
 
        assert(!MapTools::containsKey(glockReqPorts_, &block));
        glockReqPorts_.insert(std::pair<const NetlistBlock*, NetlistPort*>(
            &block, &glockReqPort));
    }

References assert, MapTools::containsKey(), glockReqPort(), and glockReqPorts_.

Referenced by addFUToNetlist(), and addGeneratableFUsToNetlist().

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mapImmediateUnitWritePort()

void ProGe::NetlistGenerator::mapImmediateUnitWritePort ( const TTAMachine::ImmediateUnit &  iu, NetlistPort &  port  )

private

Maps the given netlist port as a write port of the given immediate unit.

Parameters

iu	The immediate unit.
port	The netlist port.

Definition at line 1818 of file NetlistGenerator.cc.

                                                              {
 
        iuPortMap_.insert(
            std::pair<const ImmediateUnit*, NetlistPort*>(&iu, &port));
    }

References iuPortMap_.

Referenced by addBaseRFToNetlist().

mapLoadPort()

void ProGe::NetlistGenerator::mapLoadPort ( const NetlistPort &  port, NetlistPort &  loadPort  )

private

Maps the given load port for the given architectural port.

Parameters

port	The architectural port in the netlist.
loadPort	The load port of the architectural port.

Definition at line 1691 of file NetlistGenerator.cc.

                                                        {
 
        assert(!MapTools::containsKey(loadPortMap_, &port));
        loadPortMap_.insert(
            std::pair<const NetlistPort*, NetlistPort*>(&port, &loadPort));
    }

References assert, MapTools::containsKey(), loadPort(), and loadPortMap_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), and ProGe::GeneratableFUNetlistBlock::addInOperand().

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mapNetlistBlock()

void ProGe::NetlistGenerator::mapNetlistBlock ( const TTAMachine::Unit &  unit, NetlistBlock &  netlistBlock  )

private

Maps the given ADF Function Unit to the given netlist block.

Parameters

adfFU	The Function Unit in ADF (Machine Object Model).
netlistBlock	The corresponding block in the netlist.

Definition at line 1668 of file NetlistGenerator.cc.

                                                                {
        assert(!MapTools::containsKey(unitCorrespondenceMap_, &unit));
        unitCorrespondenceMap_.insert(
            std::pair<const Unit*, NetlistBlock*>(&unit, &netlistBlock));
    }

References assert, MapTools::containsKey(), netlistBlock(), and unitCorrespondenceMap_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), and addGeneratableFUsToNetlist().

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mapNetlistPort()

void ProGe::NetlistGenerator::mapNetlistPort ( const TTAMachine::Port &  adfPort, NetlistPort &  netlistPort  )

private

Maps the given ADF port to the given netlist port.

Parameters

adfPort	The port in ADF (Machine Object Model).
netlistPort	The corresponding port in the netlist.

Definition at line 1650 of file NetlistGenerator.cc.

                                                                 {
 
        if (portCorrespondenceMap_.count(&adfPort) != 0) {
            auto range = portCorrespondenceMap_.equal_range(&adfPort);
            for (auto i = range.first; i != range.second; ++i) {
                assert(i->second->direction() != netlistPort.direction());
            }
        }
        portCorrespondenceMap_.emplace(&adfPort, &netlistPort);
    }

References assert, ProGe::NetlistPort::direction(), netlistPort(), and portCorrespondenceMap_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), ProGe::GeneratableFUNetlistBlock::addInOperand(), and ProGe::GeneratableFUNetlistBlock::addOutOperand().

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mapResetPort()

void ProGe::NetlistGenerator::mapResetPort ( const NetlistBlock &  block, NetlistPort &  resetPort  )

private

Maps the given reset port for the given block.

Parameters

block	The netlist block.
resetPort	The reset port of the block.

Definition at line 1747 of file NetlistGenerator.cc.

                                                           {
 
        assert(!MapTools::containsKey(rstPorts_, &block));
        rstPorts_.insert(
            std::pair<const NetlistBlock*, NetlistPort*>(&block, &resetPort));
    }

References assert, MapTools::containsKey(), and rstPorts_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGCUToNetlist(), and addGeneratableFUsToNetlist().

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mapRFGuardPort()

void ProGe::NetlistGenerator::mapRFGuardPort ( const NetlistBlock &  block, NetlistPort &  guardPort  )

private

Maps the given guard port for the given RF block.

Parameters

block	The netlist block.
guardPort	The guard port of the block.

Definition at line 1789 of file NetlistGenerator.cc.

                                                           {
 
        assert(!MapTools::containsKey(rfGuardPorts_, &block));
        rfGuardPorts_.insert(
            std::pair<const NetlistBlock*, NetlistPort*>(&block, &guardPort));
    }

References assert, MapTools::containsKey(), and rfGuardPorts_.

Referenced by addBaseRFToNetlist().

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mapRFOpcodePort()

void ProGe::NetlistGenerator::mapRFOpcodePort ( const NetlistPort &  port, NetlistPort &  opcodePort  )

private

Maps the given opcode port for the given architectural RF port.

Parameters

port	The architectural port in the netlist.
opcodePort	The opcode port of the architectural port.

Definition at line 1705 of file NetlistGenerator.cc.

                                                          {
 
        assert(!MapTools::containsKey(rfOpcodePortMap_, &port));
        rfOpcodePortMap_.insert(
            std::pair<const NetlistPort*, NetlistPort*>(&port, &opcodePort));
    }

References assert, MapTools::containsKey(), and rfOpcodePortMap_.

Referenced by addBaseRFToNetlist().

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netlistBlock()

NetlistBlock & ProGe::NetlistGenerator::netlistBlock

(

const TTAMachine::Unit &

unit

)

const

Returns the netlist block which is corresponding to the given unit in the machine object model.

Parameters

unit	The Unit in the machine object model

Returns

The corresponding block in the netlist.

Exceptions

InstanceNotFound

If the netlist does not contain the block.

Definition at line 283 of file NetlistGenerator.cc.

                                                                   {
        try {
            return *MapTools::valueForKey<NetlistBlock*>(
                unitCorrespondenceMap_, &unit);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format(
                     "Cannot find corresponding netlist block for '%s'") %
                    unit.name())
                    .str());
        }
    }

References __func__, MapTools::keyForValue(), TTAMachine::Component::name(), and unitCorrespondenceMap_.

Referenced by DefaultDecoderGenerator::addGlockPortToDecoder(), addIUToNetlist(), DefaultDecoderGenerator::addLockReqPortToDecoder(), addRFToNetlist(), DefaultDecoderGenerator::completeDecoderBlock(), DefaultDecoderGenerator::glockPortWidth(), DefaultDecoderGenerator::glockRequestWidth(), and mapNetlistBlock().

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netlistPort()

NetlistPort & ProGe::NetlistGenerator::netlistPort	(	const TTAMachine::Port &	port,
		Direction	dir = IN
	)		const

Returns the netlist port which is corresponding to the given port in the machine object model.

Parameters

port	The port in the machine object model

Returns

The corresponding port in the netlist.

Exceptions

InstanceNotFound

If the netlist does not contain the port.

Definition at line 247 of file NetlistGenerator.cc.

                                                         {
        if (portCorrespondenceMap_.count(&port) > 0) {
            // Override direction with port direction if the port is
            // unidirectional
            if (!(port.isInput() && port.isOutput())) {
                dir = port.isInput() ? IN : OUT;
            }
 
            auto range = portCorrespondenceMap_.equal_range(&port);
            for (auto i = range.first; i != range.second; ++i) {
                if(i->second->direction() == dir)
                    return *i->second;
            }
            return *MapTools::valueForKey<NetlistPort*>(
                portCorrespondenceMap_, &port);
        }
 
        throw InstanceNotFound(__FILE__, __LINE__, __func__,
            (boost::format(
                "Cannot find netlist port '%s' in parent unit: '%s'") %
                port.name() % port.parentUnit()->name())
                .str());
    }

References __func__, ProGe::IN, TTAMachine::Port::isInput(), TTAMachine::Port::isOutput(), MapTools::keyForValue(), TTAMachine::Component::name(), TTAMachine::Port::name(), ProGe::OUT, TTAMachine::Port::parentUnit(), and portCorrespondenceMap_.

Referenced by DefaultICGenerator::addICToNetlist(), DefaultDecoderGenerator::completeDecoderBlock(), and mapNetlistPort().

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netlistPortIsMapped()

bool ProGe::NetlistGenerator::netlistPortIsMapped ( const TTAMachine::Port &  adfPort )

private

Returns true if the given ADF port is mapped to some netlist port.

Parameters

adfPort

The port in ADF (Machine Object Model).

Definition at line 1681 of file NetlistGenerator.cc.

                                                                       {
        return portCorrespondenceMap_.count(&adfPort) != 0;
    }

References portCorrespondenceMap_.

Referenced by addGCUToNetlist().

opcodePortWidth() [1/2]

int ProGe::NetlistGenerator::opcodePortWidth ( const HDB::FUEntry &  fu, std::ostream &  warningStream  )

staticprivate

Calculates the required opcode port width for the given FU.

Parameters

fu	The FU.
warningStream	Output stream where warnings are written

Returns

The required width of opcode port.

Exceptions

InvalidData

If the HDB is missing some information.

Definition at line 1889 of file NetlistGenerator.cc.

                                                      {
        assert(fu.hasImplementation());
        assert(fu.hasArchitecture());
        FUImplementation& implementation = fu.implementation();
        FunctionUnit& architecture = fu.architecture().architecture();
        int portWidth = 0;
 
        // operation codes are now numbered according to their alphabetical
        // order
        set<string> opcodeSet;
        for (int i = 0; i < architecture.operationCount(); i++) {
            HWOperation* operation = architecture.operation(i);
            opcodeSet.insert(operation->name());
        }
 
        int opcode = 0;
        for (set<string>::iterator iter = opcodeSet.begin();
             iter != opcodeSet.end(); iter++) {
            // there is an old opcode value in hdb
            if (opcodeSet.size() != 1 && implementation.hasOpcode(*iter)) {
                // old value differs from current guide line
                if (opcode != implementation.opcode(*iter)) {
                    warningStream << "Warning: Opcode defined in HDB for "
                                  << "operation " << *iter
                                  << " does not comply with the requirement "
                                  << "for numbering the operation codes "
                                  << "according to alphabetical order of "
                                  << "operations. Please fix the vhdl and "
                                  << "hdb entry." << std::endl;
                }
            }
            int requiredBits = MathTools::requiredBits(opcode);
            if (requiredBits > portWidth) {
                portWidth = requiredBits;
            }
            opcode++;
        }
 
        return portWidth;
    }

References HDB::FUArchitecture::architecture(), HDB::FUEntry::architecture(), assert, HDB::FUEntry::hasArchitecture(), HDB::FUEntry::hasImplementation(), HDB::FUEntry::implementation(), implementation, TTAMachine::HWOperation::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), and MathTools::requiredBits().

Referenced by addFUToNetlist(), and addGCUToNetlist().

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opcodePortWidth() [2/2]

int ProGe::NetlistGenerator::opcodePortWidth ( const TTAMachine::ControlUnit &  gcu )

staticprivate

Calculates the required opcode port width for the given GCU.

Parameters

gcu

The GCU.

Returns

The required width of opcode port.

Definition at line 1937 of file NetlistGenerator.cc.

                                                                          {
        set<string> opcodeSet;
        for (int i = 0; i < gcu.operationCount(); i++) {
            HWOperation* operation = gcu.operation(i);
            opcodeSet.insert(operation->name());
        }
 
        // Assumes that operations of GCU are coded as
        // 0..operationCount()-1.
        if (opcodeSet.size() < 2) {
            return 1;
        } else {
            return MathTools::requiredBits(opcodeSet.size() - 1);
        }
    }

References TTAMachine::HWOperation::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), and MathTools::requiredBits().

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rfEntry()

HDB::RFEntry & ProGe::NetlistGenerator::rfEntry

(

const std::string &

rfName

)

const

Returns the RF entry which was selected to represent the given RF.

Parameters

fuName

Name of the RF in ADF.

Returns

The RF entry.

Exceptions

InstanceNotFound

If the netlist is not created yet or if there was no RF entry for the given RF.

Definition at line 676 of file NetlistGenerator.cc.

                                                           {
        try {
            return *MapTools::valueForKey<RFEntry*>(rfEntryMap_, rfName);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                "Cannot find register file entry from the netlist.");
        }
    }

References __func__, MapTools::keyForValue(), and rfEntryMap_.

Referenced by DefaultDecoderGenerator::sacEnabled().

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rfGuardPort()

NetlistPort & ProGe::NetlistGenerator::rfGuardPort

(

const NetlistBlock &

rfBlock

)

const

Returns the guard port of the given RF block in the netlist.

Parameters

rfBlock

The RF block in the netlist.

Returns

The guard port of the given block.

Exceptions

InstanceNotFound

If the netlist does not contain the port.

Definition at line 357 of file NetlistGenerator.cc.

                                                                   {
        try {
            return *MapTools::valueForKey<NetlistPort*>(
                rfGuardPorts_, &rfBlock);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format("Cannot find guard port in register file "
                               "instance name: '%s',"
                               "module name: '%s'") %
                    rfBlock.instanceName() % rfBlock.moduleName())
                    .str());
        }
    }

References __func__, ProGe::BaseNetlistBlock::instanceName(), MapTools::keyForValue(), ProGe::BaseNetlistBlock::moduleName(), and rfGuardPorts_.

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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rfOpcodePort()

NetlistPort & ProGe::NetlistGenerator::rfOpcodePort

(

const NetlistPort &

port

)

const

Returns the opcode port of the given RF port in the netlist.

Parameters

port	The architectural RF port in the netlist.

Returns

The opcode port of the given port.

Exceptions

InstanceNotFound

If the netlist does not contain the port.

Definition at line 334 of file NetlistGenerator.cc.

                                                                {
        try {
            return *MapTools::valueForKey<NetlistPort*>(
                rfOpcodePortMap_, &port);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format("Cannot find rf opcode port '%s' in "
                               "instance name: '%s', "
                               "module name: '%s'") %
                    port.name() % port.parentBlock().instanceName() %
                    port.parentBlock().moduleName())
                    .str());
        }
    }

References __func__, ProGe::BaseNetlistBlock::instanceName(), MapTools::keyForValue(), ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistPort::name(), ProGe::NetlistPort::parentBlock(), and rfOpcodePortMap_.

Referenced by DefaultDecoderGenerator::completeDecoderBlock().

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rstPort()

NetlistPort & ProGe::NetlistGenerator::rstPort

(

const NetlistBlock &

block

)

const

Returns the reset port of the given block in the netlist.

Parameters

block

The block in the netlist.

Returns

The reset port of the given block.

Exceptions

InstanceNotFound

If the netlist does not contain the port.

Definition at line 446 of file NetlistGenerator.cc.

                                                             {
        try {
            return *MapTools::valueForKey<NetlistPort*>(rstPorts_, &block);
        } catch (const Exception&) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                (boost::format("Cannot find reset port in netlist block "
                               "instance name: "
                               "'%s', module name: '%s'") %
                    block.instanceName() % block.moduleName())
                    .str());
        }
    }

References __func__, ProGe::BaseNetlistBlock::instanceName(), MapTools::keyForValue(), ProGe::BaseNetlistBlock::moduleName(), and rstPorts_.

Referenced by addBaseRFToNetlist(), addFUToNetlist(), addGeneratableFUsToNetlist(), DefaultICDecoderGenerator::addRV32MicroCode(), and DefaultICDecoderGenerator::generateDebuggerCode().

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translateDirection()

ProGe::Direction ProGe::NetlistGenerator::translateDirection ( HDB::Direction  direction )

staticprivate

Definition at line 2059 of file NetlistGenerator.cc.

                                                               {
        switch (direction) {
        case HDB::IN:
            return IN;
        case HDB::OUT:
            return OUT;
        case HDB::BIDIR:
            return BIDIR;
        default:
            assert(false && "Unknown HDB::direction.");
            return IN;
        }
    }

References assert, HDB::BIDIR, ProGe::BIDIR, HDB::IN, ProGe::IN, HDB::OUT, and ProGe::OUT.

Referenced by addBaseRFToNetlist(), addFUExternalPortsToNetlist(), and addFUToNetlist().

ttaCore()

NetlistBlock & ProGe::NetlistGenerator::ttaCore

(

)

const

Returns the TTA core block in the netlist.

Returns

The TTA core block.

Exceptions

InstanceNotFound

If there is no instruction decoder in the netlist.

Definition at line 584 of file NetlistGenerator.cc.

                                    {
        if (coreBlock_ == NULL) {
            throw InstanceNotFound(__FILE__, __LINE__, __func__,
                "Cannot find TTA core block from the netlist.");
        }
        return *coreBlock_;
    }

References __func__, and coreBlock_.

Friends And Related Symbol Documentation

GeneratableFUNetlistBlock

friend class GeneratableFUNetlistBlock

friend

Definition at line 85 of file NetlistGenerator.hh.

Referenced by addGeneratableFUsToNetlist().

Member Data Documentation

ADDR_WIDTH

const std::string ProGe::NetlistGenerator::ADDR_WIDTH

static

Definition at line 152 of file NetlistGenerator.hh.

clkPorts_

PortPurposeMap ProGe::NetlistGenerator::clkPorts_

private

Maps clock ports.

Definition at line 258 of file NetlistGenerator.hh.

Referenced by clkPort(), and mapClockPort().

context_

const ProGeContext& ProGe::NetlistGenerator::context_

private

Definition at line 246 of file NetlistGenerator.hh.

Referenced by addFUToNetlist(), addGCUToNetlist(), addGeneratableFUsToNetlist(), addIUToNetlist(), addRFToNetlist(), context(), and generate().

coreBlock_

NetlistBlock* ProGe::NetlistGenerator::coreBlock_

private

The TTA core block.

Definition at line 274 of file NetlistGenerator.hh.

Referenced by generate(), and ttaCore().

DECODER_CLOCK_PORT

const std::string ProGe::NetlistGenerator::DECODER_CLOCK_PORT = CLOCK_PORT_NAME

static

Clock port name in instruction decoder.

Definition at line 132 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), DefaultICGenerator::addICToNetlist(), DefaultDecoderGenerator::writeLongImmediateWriteProcess(), and DefaultDecoderGenerator::writeMainDecodingProcess().

DECODER_INSTR_WORD_PORT

const std::string ProGe::NetlistGenerator::DECODER_INSTR_WORD_PORT

static

Initial value:

=
        INSTRUCTIONWORD_PORT_NAME

Instruction word port name in instruction decoder.

Definition at line 128 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), DefaultDecoderGenerator::writeInstructionDismembering(), and DefaultDecoderGenerator::writeInstructionTemplateProcedures().

DECODER_LOCK_REQ_IN_PORT

const std::string ProGe::NetlistGenerator::DECODER_LOCK_REQ_IN_PORT

static

Initial value:

=
        LOCK_PORT_NAME

Lock request in port name in instruction decoder.

Definition at line 142 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), DefaultDecoderGenerator::writeGlockMapping(), DefaultDecoderGenerator::writeInstructionDecoder(), DefaultDecoderGenerator::writeLockDumpCode(), DefaultDecoderGenerator::writeLongImmediateWriteProcess(), and DefaultDecoderGenerator::writeMainDecodingProcess().

DECODER_LOCK_REQ_OUT_PORT

const std::string ProGe::NetlistGenerator::DECODER_LOCK_REQ_OUT_PORT

static

Initial value:

=
        LOCK_REQUEST_PORT_NAME

Lock request out port name in instruction decoder.

Definition at line 140 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), DefaultDecoderGenerator::writeGlockMapping(), and DefaultDecoderGenerator::writeInstructionDecoder().

DECODER_LOCK_STATUS_PORT

const std::string ProGe::NetlistGenerator::DECODER_LOCK_STATUS_PORT

static

Initial value:

=
        LOCK_STATUS_PORT_NAME

Definition at line 144 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and DefaultDecoderGenerator::writeGlockMapping().

DECODER_PC_LOAD_PORT

const std::string ProGe::NetlistGenerator::DECODER_PC_LOAD_PORT

static

Initial value:

=
        PC_LOAD_PORT_NAME

PC load port name in instruction decoder.

Definition at line 136 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and DefaultDecoderGenerator::writeControlRegisterMappings().

DECODER_PC_OPCODE_PORT

const std::string ProGe::NetlistGenerator::DECODER_PC_OPCODE_PORT

static

Initial value:

=
        PC_OPCODE_PORT_NAME

PC opcode port name in instruction decoder.

Definition at line 138 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), DefaultDecoderGenerator::opcodeWidth(), and DefaultDecoderGenerator::writeControlRegisterMappings().

DECODER_RA_LOAD_PORT

const std::string ProGe::NetlistGenerator::DECODER_RA_LOAD_PORT

static

Initial value:

=
        RA_LOAD_PORT_NAME

RA load port name in instruction decoder.

Definition at line 134 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and DefaultDecoderGenerator::writeControlRegisterMappings().

DECODER_RESET_PORT

const std::string ProGe::NetlistGenerator::DECODER_RESET_PORT = RESET_PORT_NAME

static

Reset port name in instruction decoder.

Definition at line 130 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), DefaultICGenerator::addICToNetlist(), DefaultDecoderGenerator::writeLongImmediateWriteProcess(), DefaultDecoderGenerator::writeMainDecodingProcess(), and DefaultDecoderGenerator::writeRFSRAMDecodingProcess().

DECOMP_GLOCK_PORT

const std::string ProGe::NetlistGenerator::DECOMP_GLOCK_PORT

static

Initial value:

=
        GLOBAL_LOCK_PORT_NAME

Global lock out port name in decompressor.

Definition at line 148 of file NetlistGenerator.hh.

DECOMP_INSTR_WORD_PORT

const std::string ProGe::NetlistGenerator::DECOMP_INSTR_WORD_PORT

static

Initial value:

=
        INSTRUCTIONWORD_PORT_NAME

Instruction word port name in decompressor.

Definition at line 150 of file NetlistGenerator.hh.

DECOMP_LOCK_REQ_IN_PORT

const std::string ProGe::NetlistGenerator::DECOMP_LOCK_REQ_IN_PORT

static

Initial value:

=
        LOCK_REQUEST_PORT_NAME

Lock request in port name in decompressor.

Definition at line 146 of file NetlistGenerator.hh.

FETCHBLOCK_PORT_NAME

const std::string ProGe::NetlistGenerator::FETCHBLOCK_PORT_NAME = "fetchblock"

static

Definition at line 154 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and DefaultICDecoderGenerator::addRV32MicroCode().

fuEntryMap_

FUEntryMap ProGe::NetlistGenerator::fuEntryMap_

private

Maps FU implementations for different FU's.

Definition at line 282 of file NetlistGenerator.hh.

Referenced by addFUToNetlist(), fuEntry(), and ~NetlistGenerator().

fuGuardPortMap_

PortRelationMap ProGe::NetlistGenerator::fuGuardPortMap_

private

Maps FU guard ports.

Definition at line 268 of file NetlistGenerator.hh.

Referenced by fuGuardPort(), and mapFUGuardPort().

fuOpcodePorts_

PortPurposeMap ProGe::NetlistGenerator::fuOpcodePorts_

private

Maps FU opcode ports.

Definition at line 270 of file NetlistGenerator.hh.

Referenced by fuOpcodePort(), and mapFUOpcodePort().

glockPorts_

PortPurposeMap ProGe::NetlistGenerator::glockPorts_

private

Maps global lock ports.

Definition at line 264 of file NetlistGenerator.hh.

Referenced by glockPort(), hasGlockPort(), and mapGlobalLockPort().

glockReqPorts_

PortPurposeMap ProGe::NetlistGenerator::glockReqPorts_

private

Maps global lock request ports.

Definition at line 266 of file NetlistGenerator.hh.

Referenced by glockReqPort(), hasGlockReqPort(), and mapGlobalLockRequestPort().

instructionDecoder_

NetlistBlock* ProGe::NetlistGenerator::instructionDecoder_

private

The instruction decoder block.

Definition at line 276 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and instructionDecoder().

instructionDecompressor_

NetlistBlock* ProGe::NetlistGenerator::instructionDecompressor_

private

The instruction decompressor block.

Definition at line 278 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and instructionDecompressor().

instructionFetch_

NetlistBlock* ProGe::NetlistGenerator::instructionFetch_

private

The instruction fetch block.

Definition at line 280 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and instructionFetch().

iuPortMap_

IUPortMap ProGe::NetlistGenerator::iuPortMap_

private

Maps the created netlist ports to immediate units.

Definition at line 272 of file NetlistGenerator.hh.

Referenced by immediateUnitWritePort(), and mapImmediateUnitWritePort().

loadPortMap_

PortRelationMap ProGe::NetlistGenerator::loadPortMap_

private

Maps loads ports.

Definition at line 254 of file NetlistGenerator.hh.

Referenced by loadPort(), and mapLoadPort().

plugin_

ICDecoderGeneratorPlugin& ProGe::NetlistGenerator::plugin_

private

The generator plugin.

Definition at line 248 of file NetlistGenerator.hh.

Referenced by generate().

portCorrespondenceMap_

PortCorrespondenceMap ProGe::NetlistGenerator::portCorrespondenceMap_

private

Maps the ADF ports to the netlist ports.

Definition at line 250 of file NetlistGenerator.hh.

Referenced by addBaseRFToNetlist(), mapNetlistPort(), netlistPort(), and netlistPortIsMapped().

raInPort_

NetlistPort* ProGe::NetlistGenerator::raInPort_

private

Return address in port in GCU (ifetch).

Definition at line 286 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and gcuReturnAddressInPort().

raOutPort_

NetlistPort* ProGe::NetlistGenerator::raOutPort_

private

Returns address out port in GCU (ifetch).

Definition at line 288 of file NetlistGenerator.hh.

Referenced by addGCUToNetlist(), and gcuReturnAddressOutPort().

rfEntryMap_

RFEntryMap ProGe::NetlistGenerator::rfEntryMap_

private

Maps RF implementations for different RF's.

Definition at line 284 of file NetlistGenerator.hh.

Referenced by addBaseRFToNetlist(), rfEntry(), and ~NetlistGenerator().

rfGuardPorts_

PortPurposeMap ProGe::NetlistGenerator::rfGuardPorts_

private

Maps RF guard ports.

Definition at line 262 of file NetlistGenerator.hh.

Referenced by mapRFGuardPort(), and rfGuardPort().

rfOpcodePortMap_

PortRelationMap ProGe::NetlistGenerator::rfOpcodePortMap_

private

Maps opcode ports.

Definition at line 256 of file NetlistGenerator.hh.

Referenced by hasOpcodePort(), mapRFOpcodePort(), and rfOpcodePort().

rstPorts_

PortPurposeMap ProGe::NetlistGenerator::rstPorts_

private

Maps reset ports.

Definition at line 260 of file NetlistGenerator.hh.

Referenced by mapResetPort(), and rstPort().

unitCorrespondenceMap_

UnitCorrespondenceMap ProGe::NetlistGenerator::unitCorrespondenceMap_

private

Maps the ADF units to the netlist blocks.

Definition at line 252 of file NetlistGenerator.hh.

Referenced by mapNetlistBlock(), and netlistBlock().

---

The documentation for this class was generated from the following files:

• NetlistGenerator.hh
• NetlistGenerator.cc