OpenASIP 2.2
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RFTestbenchGenerator.hh
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1/*
2 Copyright (c) 2002-2010 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file RFTestbenchGenerator.hh
26 *
27 * Declaration of RFTestbenchGenerator class
28 *
29 * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
30 * @note rating: red
31 */
32
33#ifndef TTA_RF_TESTBENCH_GENERATOR_HH
34#define TTA_RF_TESTBENCH_GENERATOR_HH
35
36#include <string>
37#include <fstream>
38#include <vector>
39#include "TestbenchGenerator.hh"
40#include "HDBManager.hh"
41#include "RFEntry.hh"
42#include "MemorySystem.hh"
43
44class MachineState;
45
46namespace TTAMachine {
47 class RegisterFile;
48 class Machine;
49}
50
52public:
54
55 virtual ~RFTestbenchGenerator();
56
57 virtual void generateTestbench(std::ofstream& file);
58
59private:
60 void createMachineState();
61
62 void parseRfPorts();
63
65
66 void createStimulus();
67
68 void createTbCode();
69
70 void
72 PortDataArray& inputData,
73 PortDataArray& inputOpcode,
74 PortDataArray& inputLoad,
75 PortDataArray& outputData,
76 PortDataArray& outputOpcode,
77 PortDataArray& outputLoad);
78
79 void
81 std::ostringstream& stream,
82 PortDataArray& array,
83 int portWidth);
84
85 int opcodePortWidth() const;
86
91
95
96 std::vector<std::string> inputPorts_;
97 std::vector<std::string> inputLoadPorts_;
98 std::vector<std::string> inputOpcodePorts_;
99 std::vector<std::string> outputPorts_;
100 std::vector<std::string> outputLoadPorts_;
101 std::vector<std::string> outputOpcodePorts_;
102
103 static const std::string RF_NAME_;
104};
105
106#endif
void writeDataArrays(std::ostringstream &stream, PortDataArray &array, int portWidth)
HDB::RFArchitecture * rfArch_
static const std::string RF_NAME_
virtual void generateTestbench(std::ofstream &file)
TTAMachine::RegisterFile * machRf_
std::vector< std::string > outputPorts_
std::vector< std::string > inputPorts_
HDB::RFImplementation * rfImpl_
std::vector< std::string > outputOpcodePorts_
TTAMachine::Machine * machine_
std::vector< std::string > inputLoadPorts_
void createStimulusArrays(PortDataArray &inputData, PortDataArray &inputOpcode, PortDataArray &inputLoad, PortDataArray &outputData, PortDataArray &outputOpcode, PortDataArray &outputLoad)
std::vector< std::string > inputOpcodePorts_
std::vector< std::string > outputLoadPorts_
std::map< std::string, std::vector< uint32_t > > PortDataArray