OpenASIP 2.2
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VHDLNetlistWriter.hh
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1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file VHDLNetlistWriter.hh
26 *
27 * Declaration of VHDLNetlistWriter class.
28 *
29 * @author Lasse Laasonen 2005 (lasse.laasonen-no.spam-tut.fi)
30 * @author Henry Linjamäki 2015 (henry.linjamaki-no.spam.tut.fi)
31 * @note rating: red
32 */
33
34#ifndef TTA_VHDL_NETLIST_WRITER_HH
35#define TTA_VHDL_NETLIST_WRITER_HH
36
37#include <map>
38#include <string>
39#include <boost/graph/graph_traits.hpp>
40
41#include "NetlistWriter.hh"
42#include "Netlist.hh"
43#include "ProGeTypes.hh"
44
45namespace ProGe {
46
47class BaseNetlistBlock;
48
49/**
50 * Writes VHDL files which implement the given netlist block.
51 */
53public:
54 VHDLNetlistWriter(const BaseNetlistBlock& targetBlock);
55 virtual ~VHDLNetlistWriter();
56
57 virtual void write(const std::string& dstDirectory);
58
59 static void writeGenericDeclaration(
60 const BaseNetlistBlock& block,
61 unsigned int indentationLevel,
62 const std::string& indentation,
63 std::ostream& stream);
64 static void writePortDeclaration(
65 const BaseNetlistBlock& block,
66 unsigned int indentationLevel,
67 const std::string& indentation,
68 std::ostream& stream);
69
70private:
71 typedef boost::graph_traits<Netlist>::vertex_descriptor
73 typedef boost::graph_traits<Netlist>::edge_descriptor
75 typedef boost::graph_traits<Netlist>::out_edge_iterator
77
78 void writeNetlistParameterPackage(const std::string& dstDirectory) const;
79 std::string netlistParameterPkgName() const;
80 void writeBlock(
81 const BaseNetlistBlock& block, const std::string& dstDirectory);
83 const BaseNetlistBlock& block,
84 std::ofstream& stream);
86 const BaseNetlistBlock& block,
87 std::ofstream& stream) const;
88
89 void writeConnection(
90 const BaseNetlistBlock& block,
91 std::ofstream& stream,
92 edge_descriptor edgeDescriptor,
93 NetlistPort* srcPort,
94 NetlistPort* dstPort) const;
95
97 const BaseNetlistBlock& block,
98 std::ofstream& stream) const;
100 const BaseNetlistBlock& block,
101 std::ofstream& stream) const;
102 std::string indentation(unsigned int level) const;
103
104 TCEString genericMapStringValue(const TCEString& generic) const;
105
106 static std::string directionString(Direction direction);
107 static std::string generateIndentation(
108 unsigned int level, const std::string& indentation);
109 static bool isNumber(const std::string& formula);
110 static bool usesParameterWidth(const NetlistPort& port);
111 static std::string portSignalName(const NetlistPort& port);
112 static std::string portSignalType(const NetlistPort& port);
113 static TCEString signalRange(
114 int high,
115 int low,
116 bool allowShort = false);
117 static TCEString parameterWidthValue(const NetlistPort& port);
118 static std::string signalAssignment(
119 const NetlistPort& dst, const NetlistPort& src);
120
121 /// Width of the ground signal.
123
124};
125}
126
127#endif
static TCEString signalRange(int high, int low, bool allowShort=false)
boost::graph_traits< Netlist >::edge_descriptor edge_descriptor
virtual void write(const std::string &dstDirectory)
static void writePortDeclaration(const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
std::string indentation(unsigned int level) const
static std::string directionString(Direction direction)
void writeNetlistParameterPackage(const std::string &dstDirectory) const
int groundWidth_
Width of the ground signal.
boost::graph_traits< Netlist >::vertex_descriptor vertex_descriptor
void writeComponentDeclarations(const BaseNetlistBlock &block, std::ofstream &stream) const
void writeSignalDeclarations(const BaseNetlistBlock &block, std::ofstream &stream)
static void writeGenericDeclaration(const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
static std::string signalAssignment(const NetlistPort &dst, const NetlistPort &src)
boost::graph_traits< Netlist >::out_edge_iterator out_edge_iterator
void writePortMappings(const BaseNetlistBlock &block, std::ofstream &stream) const
static std::string portSignalType(const NetlistPort &port)
std::string netlistParameterPkgName() const
void writeBlock(const BaseNetlistBlock &block, const std::string &dstDirectory)
static TCEString parameterWidthValue(const NetlistPort &port)
static bool usesParameterWidth(const NetlistPort &port)
static std::string portSignalName(const NetlistPort &port)
TCEString genericMapStringValue(const TCEString &generic) const
void writeSignalAssignments(const BaseNetlistBlock &block, std::ofstream &stream) const
void writeConnection(const BaseNetlistBlock &block, std::ofstream &stream, edge_descriptor edgeDescriptor, NetlistPort *srcPort, NetlistPort *dstPort) const
static bool isNumber(const std::string &formula)
static std::string generateIndentation(unsigned int level, const std::string &indentation)
Definition FUGen.hh:54
Direction
Direction of the port.
Definition ProGeTypes.hh:52