ProGe::VHDLNetlistWriter Class Reference

#include <VHDLNetlistWriter.hh>

Inheritance diagram for ProGe::VHDLNetlistWriter:

Collaboration diagram for ProGe::VHDLNetlistWriter:

Public Member Functions
	VHDLNetlistWriter (const BaseNetlistBlock &targetBlock)
virtual	~VHDLNetlistWriter ()
virtual void	write (const std::string &dstDirectory)
Public Member Functions inherited from ProGe::NetlistWriter
	NetlistWriter (const BaseNetlistBlock &targetBlock)
virtual	~NetlistWriter ()

Static Public Member Functions
static void	writeGenericDeclaration (const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)
static void	writePortDeclaration (const BaseNetlistBlock &block, unsigned int indentationLevel, const std::string &indentation, std::ostream &stream)

Private Types
typedef boost::graph_traits< Netlist >::vertex_descriptor	vertex_descriptor
typedef boost::graph_traits< Netlist >::edge_descriptor	edge_descriptor
typedef boost::graph_traits< Netlist >::out_edge_iterator	out_edge_iterator

Private Member Functions
void	writeNetlistParameterPackage (const std::string &dstDirectory) const
std::string	netlistParameterPkgName () const
void	writeBlock (const BaseNetlistBlock &block, const std::string &dstDirectory)
void	writeSignalDeclarations (const BaseNetlistBlock &block, std::ofstream &stream)
void	writeSignalAssignments (const BaseNetlistBlock &block, std::ofstream &stream) const
void	writeConnection (const BaseNetlistBlock &block, std::ofstream &stream, edge_descriptor edgeDescriptor, NetlistPort *srcPort, NetlistPort *dstPort) const
void	writeComponentDeclarations (const BaseNetlistBlock &block, std::ofstream &stream) const
void	writePortMappings (const BaseNetlistBlock &block, std::ofstream &stream) const
std::string	indentation (unsigned int level) const
TCEString	genericMapStringValue (const TCEString &generic) const

Static Private Member Functions
static std::string	directionString (Direction direction)
static std::string	generateIndentation (unsigned int level, const std::string &indentation)
static bool	isNumber (const std::string &formula)
static bool	usesParameterWidth (const NetlistPort &port)
static std::string	portSignalName (const NetlistPort &port)
static std::string	portSignalType (const NetlistPort &port)
static TCEString	signalRange (int high, int low, bool allowShort=false)
static TCEString	parameterWidthValue (const NetlistPort &port)
static std::string	signalAssignment (const NetlistPort &dst, const NetlistPort &src)

Private Attributes
int	groundWidth_
	Width of the ground signal.

Additional Inherited Members
Protected Member Functions inherited from ProGe::NetlistWriter
const BaseNetlistBlock &	targetNetlistBlock () const

Detailed Description

Writes VHDL files which implement the given netlist block.

Definition at line 52 of file VHDLNetlistWriter.hh.

Member Typedef Documentation

edge_descriptor

typedef boost::graph_traits<Netlist>::edge_descriptor ProGe::VHDLNetlistWriter::edge_descriptor

private

Definition at line 74 of file VHDLNetlistWriter.hh.

out_edge_iterator

typedef boost::graph_traits<Netlist>::out_edge_iterator ProGe::VHDLNetlistWriter::out_edge_iterator

private

Definition at line 76 of file VHDLNetlistWriter.hh.

vertex_descriptor

typedef boost::graph_traits<Netlist>::vertex_descriptor ProGe::VHDLNetlistWriter::vertex_descriptor

private

Definition at line 72 of file VHDLNetlistWriter.hh.

Constructor & Destructor Documentation

VHDLNetlistWriter()

ProGe::VHDLNetlistWriter::VHDLNetlistWriter

(

const BaseNetlistBlock &

targetBlock

)

Constructor. Records the input netlist for which it can generate VHDL.

Parameters

netlist

The input netlist.

Definition at line 70 of file VHDLNetlistWriter.cc.

    : NetlistWriter(targetBlock), groundWidth_(0) {}

~VHDLNetlistWriter()

ProGe::VHDLNetlistWriter::~VHDLNetlistWriter ( )

virtual

The destructor.

Definition at line 76 of file VHDLNetlistWriter.cc.

                                      {
}

Member Function Documentation

directionString()

std::string ProGe::VHDLNetlistWriter::directionString ( Direction  direction )

staticprivate

Returns the string that means the same direction as the given one in VHDL.

Returns

The direction string.

Definition at line 688 of file VHDLNetlistWriter.cc.

                                                      {
    switch (direction) {
        case IN:
            return "in";
        case OUT:
            return "out";
        case BIDIR:
            return "inout";
        default:
            assert(false);
    }
 
    // dummy return
    assert(false);
    return "";
}

References assert, ProGe::BIDIR, ProGe::IN, and ProGe::OUT.

Referenced by writeComponentDeclarations(), and writePortDeclaration().

generateIndentation()

std::string ProGe::VHDLNetlistWriter::generateIndentation ( unsigned int  indentationLevel, const std::string &  indentation  )

staticprivate

Generates an indentation string with the given parameters.

Parameters

indentationLevel	The level of indentation.
indentation	The string used as indentation (one level).

Returns

The indentation of the given level.

Definition at line 751 of file VHDLNetlistWriter.cc.

                                  {
 
    string generatedInd("");
    for (size_t i = 0; i < indentationLevel; i++) {
        generatedInd += indentation;
    }
    return generatedInd;
}

References indentation().

Referenced by writeGenericDeclaration(), and writePortDeclaration().

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genericMapStringValue()

TCEString ProGe::VHDLNetlistWriter::genericMapStringValue ( const TCEString &  generic ) const

private

Tries to determine whether the string generic needs quot marks for generic mapping

If string literal contains '.', or "__" it cannot be a valid VHDL label (i.e. another generic), thus it needs quotation marks.

Parameters

generic

String generic value

Returns

Generic mapping string

Definition at line 829 of file VHDLNetlistWriter.cc.

                                                                       {
 
    if (generic.startsWith("\"") && generic.endsWith("\"")) {
        return generic;
    }
    std::vector<TCEString> unallowed;
    unallowed.push_back(".");
    unallowed.push_back("__");
    for (size_t i = 0; i < unallowed.size(); i++) {
        if (generic.find(unallowed.at(i)) != TCEString::npos) {
            TCEString quoted;
            quoted << "\"" << generic << "\"";
            return quoted;
        }
    }
    return generic;
}

References TCEString::endsWith(), and TCEString::startsWith().

Referenced by writePortMappings().

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indentation()

std::string ProGe::VHDLNetlistWriter::indentation ( unsigned int  level ) const

private

Returns a string which makes indetation of the given level.

Parameters

level

The indentation level.

Definition at line 739 of file VHDLNetlistWriter.cc.

                                                       {
    return StringTools::indent(level);
}

References StringTools::indent().

Referenced by generateIndentation(), writeBlock(), writeComponentDeclarations(), writeConnection(), writeGenericDeclaration(), writeNetlistParameterPackage(), writePortDeclaration(), writePortMappings(), writeSignalAssignments(), and writeSignalDeclarations().

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isNumber()

bool ProGe::VHDLNetlistWriter::isNumber ( const std::string &  formula )

staticprivate

Tells whether the given string is a non-negative integer number.

Parameters

formula

The string.

Returns

True if the given string is a non-negative integer number.

Definition at line 712 of file VHDLNetlistWriter.cc.

                                                    {
    int length = formula.length();
    for (int i = 0; i < length; i++) {
        if (!isdigit(formula[i])) {
            return false;
        }
    }
 
    return true;
}

Referenced by portSignalType(), writeComponentDeclarations(), and writePortDeclaration().

netlistParameterPkgName()

std::string ProGe::VHDLNetlistWriter::netlistParameterPkgName ( ) const

private

Returns the name of the netlist parameter package.

Returns

The name.

Definition at line 128 of file VHDLNetlistWriter.cc.

                                                 {
    return targetNetlistBlock().moduleName() + "_params";
}

References ProGe::BaseNetlistBlock::moduleName(), and ProGe::NetlistWriter::targetNetlistBlock().

Referenced by writeBlock(), and writeNetlistParameterPackage().

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parameterWidthValue()

TCEString ProGe::VHDLNetlistWriter::parameterWidthValue ( const NetlistPort &  port )

staticprivate

Returns port width value of port that uses parameter as width.

Definition at line 880 of file VHDLNetlistWriter.cc.

                                                              {
    return port.parentBlock().parameter(port.widthFormula()).value();
}

References ProGe::BaseNetlistBlock::parameter(), ProGe::NetlistPort::parentBlock(), ProGe::Parameter::value(), and ProGe::NetlistPort::widthFormula().

Referenced by portSignalType().

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portSignalName()

std::string ProGe::VHDLNetlistWriter::portSignalName ( const NetlistPort &  port )

staticprivate

Returns the name of the signal mapped to the given port.

Parameters

port

The port.

Definition at line 769 of file VHDLNetlistWriter.cc.

                                                         {
    const BaseNetlistBlock* parentBlock = &port.parentBlock();
    string signalName = "";
    if (port.hasStaticValue()) {
        string bit = "";
        if (port.staticValue().is(StaticSignal::VCC)) {
            bit = "1";
        } else {
            bit = "0";
        }
        if (port.dataType() == BIT) {
            signalName = "'" + bit + "'";
        } else {
            signalName = "(others => '" + bit + "')";
        }
    } else {
        signalName = parentBlock->instanceName() + "_" + port.name() +
            "_wire";
    }
    return signalName;
}

References ProGe::BIT, ProGe::NetlistPort::dataType(), ProGe::NetlistPort::hasStaticValue(), ProGe::BaseNetlistBlock::instanceName(), ProGe::StaticSignal::is(), ProGe::NetlistPort::name(), ProGe::NetlistPort::parentBlock(), ProGe::NetlistPort::staticValue(), and ProGe::StaticSignal::VCC.

Referenced by signalAssignment(), writeConnection(), writePortMappings(), and writeSignalDeclarations().

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portSignalType()

std::string ProGe::VHDLNetlistWriter::portSignalType ( const NetlistPort &  port )

staticprivate

Returns the type of the signal mapped to the given port.

Parameters

port

The port.

Definition at line 798 of file VHDLNetlistWriter.cc.

                                                         {
    if (port.dataType() == BIT) {
        return "std_logic";
    } else {
        if (port.realWidthAvailable()) {
            int width = port.realWidth();
            return "std_logic_vector" +
                   signalRange((width ? width - 1 : 0), 0);
        } else if (isNumber(port.widthFormula()) && 
                   (Conversion::toInt(port.widthFormula()) == 0)) {
            return "std_logic_vector" + signalRange(0, 0);
        } else if (usesParameterWidth(port)) {
            return "std_logic_vector(" + parameterWidthValue(port) +
                   "-1 downto 0)";
        } else {
            return "std_logic_vector(" + port.widthFormula() + "-1 downto 0)";
        }
    }
}

References ProGe::BIT, ProGe::NetlistPort::dataType(), isNumber(), parameterWidthValue(), ProGe::NetlistPort::realWidth(), ProGe::NetlistPort::realWidthAvailable(), signalRange(), Conversion::toInt(), usesParameterWidth(), and ProGe::NetlistPort::widthFormula().

Referenced by writeSignalDeclarations().

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signalAssignment()

std::string ProGe::VHDLNetlistWriter::signalAssignment ( const NetlistPort &  dst, const NetlistPort &  src  )

staticprivate

Writes suitable signal assignment code of two signals.

The written code piece is "dst <= src;" with additional signal indexing in case the data types does not macth (i.e. BIT vs. BIT_VECTOR).

Definition at line 892 of file VHDLNetlistWriter.cc.

                                                    {
    using std::string;
 
    if (dst.dataType() == src.dataType()) {
        return string(portSignalName(dst)) + " <= " + portSignalName(src) +
               ";";
    } else {
        // Note assuming that one port is data type of BIT and other is
        // BIT_VECTOR of width og one.
        bool indexDst = (dst.dataType() == BIT_VECTOR);
        return string(portSignalName(dst)) +
               (indexDst ? string("(0) <= ") : string(" <= ")) +
               portSignalName(src) +
               (indexDst ? string(";") : string("(0);"));
    }
}

References ProGe::BIT_VECTOR, ProGe::NetlistPort::dataType(), and portSignalName().

Referenced by writeConnection().

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signalRange()

TCEString ProGe::VHDLNetlistWriter::signalRange ( int  high, int  low, bool  allowShort = false  )

staticprivate

Returns signal range i.e. (<high> downto <low>).

Does not -1 the high index! If high == low and allowShort is true, just (<low>) is returned

Parameters

high	MSB index
low	LSB index
allowShort	If true, skips 'downto' if high == low

Returns

Signal range string

Definition at line 859 of file VHDLNetlistWriter.cc.

                                                                 {
    if (high < low) {
        TCEString msg;
        msg << "High (" << high << ") boundary is smaller than low (" << low
            << ") boundary!";
        throw InvalidData(__FILE__, __LINE__, __func__, msg);
    }
 
    TCEString range = "(";
    if (allowShort && high == low) {
        range << low;
    } else {
        range << high << " downto " << low;
    }
    return range << ")";
}

References __func__.

Referenced by portSignalType(), writeConnection(), and writeSignalDeclarations().

usesParameterWidth()

bool ProGe::VHDLNetlistWriter::usesParameterWidth ( const NetlistPort &  port )

staticprivate

Returns true if port uses single parameter of its parent block as port width.

Definition at line 728 of file VHDLNetlistWriter.cc.

                                                             {
    const BaseNetlistBlock& parent = port.parentBlock();
    return parent.hasParameter(port.widthFormula());
}

References ProGe::BaseNetlistBlock::hasParameter(), ProGe::NetlistPort::parentBlock(), and ProGe::NetlistPort::widthFormula().

Referenced by portSignalType().

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write()

void ProGe::VHDLNetlistWriter::write ( const std::string &  dstDirectory )

virtual

Generates the VHDL files and writes them to the given directory.

Parameters

dstDirectory

The destination directory.

Exceptions

IOException	If an IO error occurs.
InvalidData	If the netlist is invalid.

Implements ProGe::NetlistWriter.

Definition at line 88 of file VHDLNetlistWriter.cc.

                                                      {
    if (targetNetlistBlock().netlist().isEmpty()) {
        string errorMsg = "Empty input netlist.";
        throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
    }
    writeNetlistParameterPackage(dstDirectory);
    writeBlock(targetNetlistBlock(), dstDirectory);
}

References __func__, ProGe::NetlistWriter::targetNetlistBlock(), writeBlock(), and writeNetlistParameterPackage().

Referenced by ProGe::BaseNetlistBlock::writeSelf().

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writeBlock()

void ProGe::VHDLNetlistWriter::writeBlock ( const BaseNetlistBlock &  block, const std::string &  dstDirectory  )

private

Writes the given block of the netlist to the given destination directory.

Parameters

block	The netlist block.
dstDirectory	The destination directory.

Exceptions

IOException

If the file cannot be created.

Definition at line 141 of file VHDLNetlistWriter.cc.

                                                                  {
    string fileName = dstDirectory + FileSystem::DIRECTORY_SEPARATOR +
        block.moduleName() + ".vhdl";
    if (!FileSystem::fileIsCreatable(fileName) && 
        !(FileSystem::fileExists(fileName) && 
          FileSystem::fileIsWritable(fileName))) {
 
        string errorMsg = "Unable to create file: " + fileName;
        throw IOException(__FILE__, __LINE__, __func__, errorMsg);
    }
 
    const string entityName = block.moduleName();
 
    ofstream outFile;
    outFile.open(fileName.c_str(), ofstream::out);
 
    outFile << "library IEEE;" << endl;
    outFile << "use IEEE.std_logic_1164.all;" << endl;
    outFile << "use IEEE.std_logic_arith.all;" << endl;
    outFile << "use work.tce_util.all;" << endl;
 
    for (size_t i = 0; i < block.packageCount(); i++) {
        outFile << "use work." << block.package(i) << ".all;" << endl;
    }
 
    if (block.netlist().parameterCount() > 0) {
        outFile << "use work." << netlistParameterPkgName() << ".all;"
                << endl;
    }
 
    outFile << endl;
 
    // create entity
    outFile << "entity " + entityName + " is" << endl;
 
    // create generics
    writeGenericDeclaration(block, 1, indentation(1), outFile);
 
    // create port declarations
    outFile << endl;
    writePortDeclaration(block, 1, indentation(1), outFile);
 
    outFile << endl << "end " << entityName << ";" << endl;
 
    // create architecture
    outFile << endl;
    string architectureName = "structural";
    outFile << "architecture " << architectureName << " of "
            << entityName << " is" << endl << endl;
 
    writeSignalDeclarations(block, outFile);
    outFile << endl;
    writeComponentDeclarations(block, outFile);
    outFile << endl;
    outFile << "begin" << endl << endl;
    writeSignalAssignments(block, outFile);
    outFile << endl;
    writePortMappings(block, outFile);
    outFile << "end " + architectureName + ";" << endl;
    outFile.close();
}

References __func__, FileSystem::DIRECTORY_SEPARATOR, FileSystem::fileExists(), FileSystem::fileIsCreatable(), FileSystem::fileIsWritable(), indentation(), ProGe::BaseNetlistBlock::moduleName(), ProGe::BaseNetlistBlock::netlist(), netlistParameterPkgName(), ProGe::BaseNetlistBlock::package(), ProGe::BaseNetlistBlock::packageCount(), ProGe::Netlist::parameterCount(), writeComponentDeclarations(), writeGenericDeclaration(), writePortDeclaration(), writePortMappings(), writeSignalAssignments(), and writeSignalDeclarations().

Referenced by write().

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writeComponentDeclarations()

void ProGe::VHDLNetlistWriter::writeComponentDeclarations ( const BaseNetlistBlock &  block, std::ofstream &  stream  ) const

private

Writes the component declarations of the given netlist block to the given stream.

Parameters

block	The netlist block.
stream	The stream to write.

Definition at line 520 of file VHDLNetlistWriter.cc.

                                                              {
    std::set<string> declaredModules;
    for (size_t i = 0; i < block.subBlockCount(); i++) {
        const BaseNetlistBlock& component = block.subBlock(i);
        if (AssocTools::containsKey(declaredModules, component.moduleName())) {
            continue;
        }
        // virtual NetlistBlocks are omitted
        if (component.isVirtual()) {
            continue;
        }
 
        declaredModules.insert(component.moduleName());
        stream << indentation(1) << "component " << component.moduleName()
               << " is" << endl;
        if (component.parameterCount() > 0) {
            stream << indentation(2) << "generic (" << endl;
            for (size_t i = 0; i < component.parameterCount(); i++) {
                Parameter param = component.parameter(i);
                stream << indentation(3) << param.name() << " : "
                       << param.type();
                if (i + 1 == component.parameterCount()) {
                    stream << ");";
                } else {
                    stream << ";";
                }
                stream << endl;
            }
        }
        stream << indentation(2) << "port (" << endl;
        for (size_t i = 0; i < component.portCount(); i++) {
            const NetlistPort& port = component.port(i);
            stream << indentation(3) << port.name() << " : "
                   << directionString(port.direction()) << " ";
            if (port.dataType() == BIT) {
                stream << "std_logic";
            } else { 
                stream << "std_logic_vector(";
                stream << port.widthFormula();
                if ((isNumber(port.widthFormula()) &&
                    (Conversion::toInt(port.widthFormula()) != 0)) ||
                        !isNumber(port.widthFormula())) {
                    stream << "-1";
                } 
                stream << " downto 0)";
            }
            if (i + 1 == component.portCount()) {
                stream << ");";
            } else {
                stream << ";";
            }
            stream << endl;
        }
        stream << indentation(1) << "end component;" << endl << endl;
    }
}

References ProGe::BIT, AssocTools::containsKey(), ProGe::NetlistPort::dataType(), ProGe::NetlistPort::direction(), directionString(), indentation(), isNumber(), ProGe::BaseNetlistBlock::isVirtual(), ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistPort::name(), ProGe::Parameter::name(), ProGe::BaseNetlistBlock::parameter(), ProGe::BaseNetlistBlock::parameterCount(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), ProGe::BaseNetlistBlock::subBlock(), ProGe::BaseNetlistBlock::subBlockCount(), Conversion::toInt(), ProGe::Parameter::type(), and ProGe::NetlistPort::widthFormula().

Referenced by writeBlock().

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writeConnection()

void ProGe::VHDLNetlistWriter::writeConnection ( const BaseNetlistBlock &  block, std::ofstream &  stream, edge_descriptor  edgeDescriptor, NetlistPort *  srcPort, NetlistPort *  dstPort  ) const

private

Definition at line 444 of file VHDLNetlistWriter.cc.

                                {
    PortConnectionProperty property = block.netlist()[edgeDescriptor];
    if (property.fullyConnected()) {
        if (&dstPort->parentBlock() == &block) {
            if (srcPort->direction() == OUT) {
                stream << indentation(1) << dstPort->name()
                       << " <= " << portSignalName(*srcPort) << ";" << endl;
            } else {
                stream << indentation(1) << portSignalName(*srcPort)
                       << " <= " << dstPort->name() << ";" << endl;
            }
        } else {
            if (srcPort->direction() == OUT) {
                stream << indentation(1)
                       << signalAssignment(*dstPort, *srcPort) << endl;
            } else {
                stream << indentation(1)
                       << signalAssignment(*srcPort, *dstPort) << endl;
            }
        }
    } else {
        string srcPortSignal;
        if (srcPort->dataType() == BIT) {
            srcPortSignal = portSignalName(*srcPort);
        } else {
            if (dstPort->dataType() == BIT) {
                srcPortSignal =
                    portSignalName(*srcPort) + "(" +
                    Conversion::toString(property.port1FirstBit()) + ")";
            } else {
                int high = property.port1FirstBit() + property.width() - 1;
                int low = property.port1FirstBit();
                srcPortSignal =
                    portSignalName(*srcPort) + signalRange(high, low, true);
            }
        }
        string dstPortSignal;
 
        if (&dstPort->parentBlock() == &block) {
            dstPortSignal = dstPort->name();
        } else {
            dstPortSignal = portSignalName(*dstPort);
        }
        if (dstPort->dataType() != BIT) {
            if (srcPort->dataType() == BIT) {
                dstPortSignal +=
                    "(" + Conversion::toString(property.port2FirstBit()) +
                    ")";
            } else {
                int high = property.port2FirstBit() + property.width() - 1;
                int low = property.port2FirstBit();
                dstPortSignal += signalRange(high, low, true);
            }
        }
 
        if (srcPort->direction() == OUT) {
            stream << indentation(1) << dstPortSignal
                   << " <= " << srcPortSignal << ";" << endl;
        } else {
            stream << indentation(1) << srcPortSignal
                   << " <= " << dstPortSignal << ";" << endl;
        }
    }
}

References ProGe::BIT, ProGe::NetlistPort::dataType(), ProGe::NetlistPort::direction(), indentation(), ProGe::NetlistPort::name(), ProGe::BaseNetlistBlock::netlist(), ProGe::OUT, ProGe::NetlistPort::parentBlock(), portSignalName(), signalAssignment(), signalRange(), and Conversion::toString().

Referenced by writeSignalAssignments().

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writeGenericDeclaration()

void ProGe::VHDLNetlistWriter::writeGenericDeclaration ( const BaseNetlistBlock &  block, unsigned int  indentationLevel, const std::string &  indentation, std::ostream &  stream  )

static

Writes the generic declarations of the given netlist block.

Parameters

block	The netlist block.
indentationLevel	The indentation level where the generic declaration is written.
indentation	The string used as indentation (one level).
stream	The stream to write.

Definition at line 214 of file VHDLNetlistWriter.cc.

                                                      {
    if (block.parameterCount() > 0) {
        stream << endl;
        stream << generateIndentation(indentationLevel, indentation)
               << "generic (" << endl;
        for (size_t i = 0; i < block.parameterCount(); i++) {
            Parameter param = block.parameter(i);
            stream << generateIndentation(indentationLevel + 1, indentation)
                   << param.name() << " : " << param.type();
            if (param.defaultValue() != "") {
                stream << " := ";
                if (param.type().lower() == PARAM_STRING) {
                    // string literal needs quot. marks
                    if (!param.defaultValue().startsWith("\""))
                        stream << "\"";
                    stream << param.value();
                    if (!param.defaultValue().endsWith("\"")) stream << "\"";
                } else {
                    stream << param.defaultValue();
                }
            }
            if (i + 1 == block.parameterCount()) {
                stream << ");";
            } else {
                stream << ";";
            }
            stream << endl;
        }
    }
}

References ProGe::Parameter::defaultValue(), TCEString::endsWith(), generateIndentation(), indentation(), TCEString::lower(), ProGe::Parameter::name(), PARAM_STRING, ProGe::BaseNetlistBlock::parameter(), ProGe::BaseNetlistBlock::parameterCount(), TCEString::startsWith(), ProGe::Parameter::type(), and ProGe::Parameter::value().

Referenced by writeBlock(), DefaultDecoderGenerator::writeInstructionDecoder(), and DefaultICGenerator::writeInterconnectionNetwork().

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writeNetlistParameterPackage()

void ProGe::VHDLNetlistWriter::writeNetlistParameterPackage ( const std::string &  dstDirectory ) const

private

Writes the package that defines parameters of the netlist.

Parameters

dstDirectory

The destination directory.

Definition at line 103 of file VHDLNetlistWriter.cc.

                                         {
 
    string fileName = dstDirectory + FileSystem::DIRECTORY_SEPARATOR + 
        netlistParameterPkgName() + "_pkg.vhdl";
    ofstream outFile;
    outFile.open(fileName.c_str(), ofstream::out);
 
    outFile << "package " << netlistParameterPkgName() << " is" << endl;
    for (size_t i = 0; i < targetNetlistBlock().netlist().parameterCount();
         i++) {
        Parameter param = targetNetlistBlock().netlist().parameter(i);
        outFile << indentation(1) << "constant " << param.name() << " : "
                << param.type() << " := " << param.value() << ";" << endl;
    }
    outFile << "end " << netlistParameterPkgName() << ";" << endl;
}

References FileSystem::DIRECTORY_SEPARATOR, indentation(), ProGe::Parameter::name(), ProGe::BaseNetlistBlock::netlist(), netlistParameterPkgName(), ProGe::Netlist::parameter(), ProGe::Netlist::parameterCount(), ProGe::NetlistWriter::targetNetlistBlock(), ProGe::Parameter::type(), and ProGe::Parameter::value().

Referenced by write().

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writePortDeclaration()

void ProGe::VHDLNetlistWriter::writePortDeclaration ( const BaseNetlistBlock &  block, unsigned int  indentationLevel, const std::string &  indentation, std::ostream &  stream  )

static

Writes the port declaration of the given netlist block.

Parameters

block	The netlist block.
indentationLevel	The indentation level where the generic declaration is written.
indentation	The string used as indentation (one level).
stream	The stream to write.

Definition at line 257 of file VHDLNetlistWriter.cc.

                                                      {
    stream << generateIndentation(indentationLevel, indentation) << "port ("
           << endl;
 
    for (size_t i = 0; i < block.portCount(); i++) {
        const NetlistPort& port = block.port(i);
        string portName = port.name();
        string direction = directionString(port.direction());
        stream << generateIndentation(indentationLevel+1, indentation)
               << portName << " : " << direction << " ";
        if (port.dataType() == BIT) {
            stream << "std_logic";
        } else {
            stream << "std_logic_vector(";
            // zero width ports as (0 downto 0)
            if (isNumber(port.widthFormula()) && 
                    Conversion::toInt(port.widthFormula()) == 0) {
                stream << "0";
            } else if (isNumber(port.widthFormula())) {
                stream << Conversion::toInt(port.widthFormula()) - 1;
            } else {
                stream << port.widthFormula() << "-1";
            }
            stream << " downto 0)";
        }
        if (i + 1 == block.portCount()) {
            stream << ");";
        } else {
            stream << ";";
        }
        stream << endl;
    }
}

References ProGe::BIT, ProGe::NetlistPort::dataType(), ProGe::NetlistPort::direction(), directionString(), generateIndentation(), indentation(), isNumber(), ProGe::NetlistPort::name(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), Conversion::toInt(), and ProGe::NetlistPort::widthFormula().

Referenced by writeBlock(), DefaultDecoderGenerator::writeInstructionDecoder(), and DefaultICGenerator::writeInterconnectionNetwork().

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writePortMappings()

void ProGe::VHDLNetlistWriter::writePortMappings ( const BaseNetlistBlock &  block, std::ofstream &  stream  ) const

private

Writes the port mappings of the given block to the given stream.

Parameters

block	The netlist block.
stream	The stream to write.

Definition at line 585 of file VHDLNetlistWriter.cc.

                                                              {
    for (size_t i = 0; i < block.subBlockCount(); i++) {
        const BaseNetlistBlock& component = block.subBlock(i);
 
        // virtual NetlistBlocks are omitted
        if (component.isVirtual()) {
            continue;
        }
 
        stream << indentation(1) << component.instanceName() << " : "
               << component.moduleName() << endl;
 
        // create generic map
        if (component.parameterCount() > 0) {
            stream << indentation(2) << "generic map (" << endl;
            for (size_t i = 0; i < component.parameterCount(); i++) {
                Parameter param = component.parameter(i);
                stream << indentation(3) << param.name() << " => ";
                if (param.type().lower() == PARAM_STRING) {
                    stream << genericMapStringValue(param.value());
                } else {
                    stream << param.value();
                }
                if (i == component.parameterCount() - 1) {
                    stream << ")" << endl;
                } else {
                    stream << "," << endl;
                }
            }
        }
 
        // create port map
        stream << indentation(2) << "port map (" << endl;
        for (size_t i = 0; i < component.portCount(); i++) {
            const NetlistPort& port = component.port(i);
            size_t vertexDescriptor = block.netlist().descriptor(port);
            std::pair<out_edge_iterator, out_edge_iterator> edges =
                boost::out_edges(vertexDescriptor, block.netlist());
 
            string srcConn = port.name();
            string dstConn = "";
            if (edges.first != edges.second) {
                edge_descriptor edgeDescriptor = *edges.first;
                vertex_descriptor dstVertex =
                    boost::target(edgeDescriptor, block.netlist());
                const NetlistPort* dstPort = block.netlist()[dstVertex];
                PortConnectionProperty property =
                    block.netlist()[edgeDescriptor];
 
                if (&dstPort->parentBlock() == &block) {
                    if (port.dataType() != dstPort->dataType()) {
                        int index = 0;
                        if (!property.fullyConnected() &&
                            dstPort->dataType() == BIT_VECTOR &&
                            port.dataType() == BIT) {
                            index = property.port2FirstBit();
                        }
 
                        if (port.dataType() == BIT) {
                            assert(dstPort->dataType() == BIT_VECTOR);
                            dstConn = dstPort->name() + "(" +
                                      Conversion::toString(index) + ")";
                        } else {
                            assert(dstPort->dataType() == BIT);
                            if (port.widthFormula() == "1") {
                                srcConn += "(0)";
                                dstConn = dstPort->name();
                            } else {
                                dstConn = portSignalName(port);
                            }
                        }
                    } else {
                        if ((!property.fullyConnected() ||
                             dstPort->direction() == OUT) &&
                            boost::out_degree(
                                vertexDescriptor, block.netlist()) > 1) {
                            dstConn = portSignalName(port);
                        } else {
                            dstConn = dstPort->name();
                        }
                    }
                } else {
                    dstConn = portSignalName(port);
                }
            } else {
                dstConn = portSignalName(port);
            }
            stream << indentation(3) << srcConn << " => " << dstConn;
            if (i+1 < component.portCount()) {
                stream << "," << endl;
            }
        }
        stream << ");" << endl << endl;
    }
}

References assert, ProGe::BIT, ProGe::BIT_VECTOR, ProGe::NetlistPort::dataType(), ProGe::Netlist::descriptor(), ProGe::NetlistPort::direction(), genericMapStringValue(), indentation(), ProGe::BaseNetlistBlock::instanceName(), ProGe::BaseNetlistBlock::isVirtual(), TCEString::lower(), ProGe::BaseNetlistBlock::moduleName(), ProGe::NetlistPort::name(), ProGe::Parameter::name(), ProGe::BaseNetlistBlock::netlist(), ProGe::OUT, PARAM_STRING, ProGe::BaseNetlistBlock::parameter(), ProGe::BaseNetlistBlock::parameterCount(), ProGe::NetlistPort::parentBlock(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), portSignalName(), ProGe::BaseNetlistBlock::subBlock(), ProGe::BaseNetlistBlock::subBlockCount(), Conversion::toString(), ProGe::Parameter::type(), ProGe::Parameter::value(), and ProGe::NetlistPort::widthFormula().

Referenced by writeBlock().

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writeSignalAssignments()

void ProGe::VHDLNetlistWriter::writeSignalAssignments ( const BaseNetlistBlock &  block, std::ofstream &  stream  ) const

private

Writes the signal assignments of the given block to the given stream.

Parameters

block	The netlist block.
stream	The stream.

Definition at line 368 of file VHDLNetlistWriter.cc.

                                                              {
    set<const BaseNetlistBlock*, NetlistBlockNameComparator> subBlocks;
    for (size_t i = 0; i < block.subBlockCount(); i++) {
        subBlocks.insert(&block.subBlock(i));
    }
 
    typedef std::vector<edge_descriptor> EdgeTable;
    EdgeTable handledEdges;
 
    for (size_t i = 0; i < block.subBlockCount(); i++) {
        const BaseNetlistBlock& subBlock = block.subBlock(i);
        for (size_t i = 0; i < subBlock.portCount(); i++) {
            const NetlistPort& port = subBlock.port(i);
            size_t vertexDescriptor = block.netlist().descriptor(port);
            std::pair<out_edge_iterator, out_edge_iterator> edges =
                boost::out_edges(vertexDescriptor, block.netlist());
 
            while (edges.first != edges.second) {
                edge_descriptor edgeDescriptor = *edges.first;
                edges.first++;
                if (!ContainerTools::containsValue(
                        handledEdges, edgeDescriptor)) {
                    vertex_descriptor srcVertex =
                        boost::source(edgeDescriptor, block.netlist());
                    vertex_descriptor dstVertex =
                        boost::target(edgeDescriptor, block.netlist());
                    NetlistPort* srcPort = block.netlist()[srcVertex];
                    NetlistPort* dstPort = block.netlist()[dstVertex];
 
                    if (&dstPort->parentBlock() == &block) {
                        if (boost::out_degree(
                                vertexDescriptor, block.netlist()) > 1) {
                            // Handle the rare case of multiple outputs
                            // through a wire signal. This isn't done normally
                            // because there would be an ugly wire signal for
                            // every clk, rstx, etc.
                            if (dstPort->direction() == OUT ||
                                srcPort->dataType() != dstPort->dataType()) {
                                writeConnection(
                                    block, stream, edgeDescriptor, srcPort,
                                    dstPort);
                            }
                        }
                        continue;
                    }
 
                    assert(srcPort == &port);
                    if (AssocTools::containsKey(
                            subBlocks, &srcPort->parentBlock()) &&
                        AssocTools::containsKey(
                            subBlocks, &dstPort->parentBlock())) {
                        handledEdges.push_back(edgeDescriptor);
                        // add the opposite edge too
                        std::pair<edge_descriptor, bool> opposite =
                            boost::edge(
                                dstVertex, srcVertex, block.netlist());
                        assert(opposite.second);
                        assert(opposite.first != edgeDescriptor);
                        handledEdges.push_back(opposite.first);
 
                        writeConnection(
                            block, stream, edgeDescriptor, srcPort, dstPort);
                    }
                }
            }
        }
    }
 
    if (groundWidth_ > 0) {
        stream << indentation(1) << GROUND_SIGNAL << " <= (others => '0');"
               << endl;
    }
}

References assert, AssocTools::containsKey(), ContainerTools::containsValue(), ProGe::NetlistPort::dataType(), ProGe::Netlist::descriptor(), ProGe::NetlistPort::direction(), GROUND_SIGNAL, groundWidth_, indentation(), ProGe::BaseNetlistBlock::netlist(), ProGe::OUT, ProGe::NetlistPort::parentBlock(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), ProGe::BaseNetlistBlock::subBlock(), ProGe::BaseNetlistBlock::subBlockCount(), and writeConnection().

Referenced by writeBlock().

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writeSignalDeclarations()

void ProGe::VHDLNetlistWriter::writeSignalDeclarations ( const BaseNetlistBlock &  block, std::ofstream &  stream  )

private

Writes the VHDL signal declarations to the given stream.

Parameters

block	The block of which the signals are written.
stream	The stream to write.

Definition at line 300 of file VHDLNetlistWriter.cc.

                                                        {
    // collect all the sub blocks to a set, lexicographical sort.
    typedef std::set<const BaseNetlistBlock*, NetlistBlockNameComparator>
        BlockSet;
    BlockSet subBlocks;
    for (size_t i = 0; i < block.subBlockCount(); i++) {
        // ports belonging to virtual blocks have static values, thus they are
        // excluded
        if (!block.subBlock(i).isVirtual()) {
            subBlocks.insert(&block.subBlock(i));
        }
    }
 
    // create a signal for each port in the sub-blocks
    for (BlockSet::const_iterator iter = subBlocks.begin();
         iter != subBlocks.end(); iter++) {
        const BaseNetlistBlock* subBlock = *iter;
 
        for (size_t i = 0; i < subBlock->portCount(); i++) {
            const NetlistPort& port = subBlock->port(i);
 
            size_t vertexDescriptor = block.netlist().descriptor(port);
            std::pair<out_edge_iterator, out_edge_iterator> edges =
                boost::out_edges(vertexDescriptor, block.netlist());
 
            if (edges.first != edges.second) {
                edge_descriptor edgeDescriptor = *edges.first;
                vertex_descriptor dstVertex =
                    boost::target(edgeDescriptor, block.netlist());
                const NetlistPort* dstPort = block.netlist()[dstVertex];
 
                if (&dstPort->parentBlock() != &block ||
                    boost::out_degree(vertexDescriptor, block.netlist()) >
                        1) {
                    stream << indentation(1) << "signal "
                           << portSignalName(port) << " : "
                           << portSignalType(port) << ";" << endl;
                }
            } else if (!port.hasStaticValue()) {
                // assume the port is connected to ground if is is
                // unconnected in the netlist
                if (port.realWidthAvailable()) {
                    groundWidth_ = 
                        std::max(port.realWidth(), groundWidth_);
                }
                stream << indentation(1) << "signal "
                       << portSignalName(port) << " : "
                       << portSignalType(port) << ";" << endl;
            }
        }
    }
    
    // create a ground signal
    if (groundWidth_ > 0) {
        stream << indentation(1) << "signal " << GROUND_SIGNAL
               << " : std_logic_vector" << signalRange(groundWidth_ - 1, 0)
               << ";" << endl;
    }
}

References ProGe::Netlist::descriptor(), GROUND_SIGNAL, groundWidth_, ProGe::NetlistPort::hasStaticValue(), indentation(), ProGe::BaseNetlistBlock::isVirtual(), ProGe::BaseNetlistBlock::netlist(), ProGe::NetlistPort::parentBlock(), ProGe::BaseNetlistBlock::port(), ProGe::BaseNetlistBlock::portCount(), portSignalName(), portSignalType(), ProGe::NetlistPort::realWidth(), ProGe::NetlistPort::realWidthAvailable(), signalRange(), ProGe::BaseNetlistBlock::subBlock(), and ProGe::BaseNetlistBlock::subBlockCount().

Referenced by writeBlock().

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Member Data Documentation

groundWidth_

int ProGe::VHDLNetlistWriter::groundWidth_

private

Width of the ground signal.

Definition at line 122 of file VHDLNetlistWriter.hh.

Referenced by writeSignalAssignments(), and writeSignalDeclarations().

---

The documentation for this class was generated from the following files:

• VHDLNetlistWriter.hh
• VHDLNetlistWriter.cc