Executes the "info proc" command.
742 {
743
744 if (!
parent().checkSimulationEnded() &&
745 !
parent().checkSimulationInitialized() &&
746 !
parent().checkSimulationStopped() &&
747 !
parent().simulatorFrontend().isSimulationRunning()) {
748
749 return false;
750 }
751
752 const int argumentCount = arguments.size() - 2;
753
754 if (!
parent().checkArgumentCount(argumentCount, 1, 1)) {
755 return false;
756 }
757
758 const std::string command =
760
761 if (command == "cycles") {
763 (boost::format("%.0f") %
764 parent().simulatorFrontend().cycleCount()).str());
765 return true;
766 } else if (command == "stats") {
767 std::stringstream result;
768
771
774
775 result
776 << std::endl
777 << "utilizations" << std::endl
778 << "------------" << std::endl;
779
780 const int COLUMN_WIDTH = 15;
783 std::set<std::string> operationsOfMachine;
784
785 result
786 << std::endl << "buses:" << std::endl << std::endl;
787
790
791 for (
int i = 0; i < busNav.
count(); ++i) {
796
797 result
798 << std::left << std::setw(COLUMN_WIDTH)
799 << bus->
name() <<
" "
800 << std::left << std::setw(COLUMN_WIDTH)
803 << std::endl;
804 }
805
806 result
807 << std::endl
808 << "sockets:" << std::endl << std::endl;
809
812 for (
int i = 0; i < socketNav.
count(); ++i) {
817
818 result
819 << std::left << std::setw(COLUMN_WIDTH)
820 << socket->
name() <<
" "
821 << std::left << std::setw(COLUMN_WIDTH)
824 << std::endl;
825 }
826
827 result
828 << std::endl
829 << "operations executed in function units:"
830 << std::endl << std::endl;
831
834 for (
int i = 0; i <= fuNav.
count(); ++i) {
836 if (i < fuNav.
count())
838 else
843
844 result
845 << fu->
name() <<
":" << std::endl;
846
850 const std::string operationUpper =
852 operationsOfMachine.insert(operationUpper);
855 fu->
name(), operationUpper);
856
857 result
858 << std::left << std::setw(COLUMN_WIDTH)
859 << operationUpper << " "
860 << std::left << std::setw(COLUMN_WIDTH)
862 executions * 100.0 / totalTriggersOfFU) +
863 "% of FU total (" +
865 << std::endl;
866 }
867
868 result
869 << std::left << std::setw(COLUMN_WIDTH)
870 << "TOTAL" << " "
871 << std::left << std::setw(COLUMN_WIDTH)
873 totalTriggersOfFU * 100.0 / totalCycles) + "% (" +
875 " triggers)" << std::endl << std::endl;
876 }
877
882 const std::string operationUpper =
884 operationsOfMachine.insert(operationUpper);
885 }
886
887 result
888 << std::endl << "operations:" << std::endl << std::endl;
889
890 for (std::set<std::string>::iterator i =
891 operationsOfMachine.begin(); i !=
892 operationsOfMachine.end(); ++i) {
895
896 result
897 << std::left << std::setw(COLUMN_WIDTH)
898 << *i << " " << std::left << std::setw(COLUMN_WIDTH)
901 << std::endl;
902 }
903
904 result
905 << std::endl
906 << "FU port guard accesses:" << std::endl;
907
910
911
912 for (UtilizationStats::FUOperationUtilizationIndex::iterator i =
913 fuGuardAccesses.begin(); i != fuGuardAccesses.end(); ++i) {
914
915 std::string fuName = i->first;
916
917 result
918 << std::endl
919 << fuName << ":"
920 << std::endl;
921
922
923 for (UtilizationStats::ComponentUtilizationIndex::iterator j =
924 i->second.begin(); j != i->second.end(); ++j) {
925 std::string fuPort = j->first;
926
929 result
930 << std::left << std::setw(COLUMN_WIDTH)
931 << fuPort << ": "
933 << std::endl;
934 }
935 }
936
937 result
938 << std::endl
939 << "register accesses:" << std::endl
940 << std::endl;
941
944 for (
int i = 0; i < rfNav.
count(); ++i) {
947
948 result
949 << rf->
name() <<
":" << std::endl;
950
951 int regsUsedInFile = 0;
952 int lastReg = 0;
953 int totalReads = 0;
954 int totalWrites = 0;
955 int totalGuards = 0;
957
958 for (int reg = 0; reg <= lastReg; ++reg) {
961 totalReads += reads;
964 totalGuards += guardReads;
967 totalWrites += writes;
968 ++regsUsedInFile;
969 result
970 << std::left << std::setw(COLUMN_WIDTH)
971 << reg << " "
972 << std::left << std::setw(COLUMN_WIDTH)
974 << std::left << std::setw(COLUMN_WIDTH + 5)
976 << std::left << std::setw(COLUMN_WIDTH)
978 << std::endl;
979 }
980
981 result
982 << std::left << std::setw(COLUMN_WIDTH)
983 << "TOTAL"
984 << std::left << std::setw(COLUMN_WIDTH)
986 << std::left << std::setw(COLUMN_WIDTH + 5)
988 << std::left << std::setw(COLUMN_WIDTH)
990 << std::endl;
991
992 result
993 << "TOTAL " << regsUsedInFile << " registers used"
994 << std::endl << std::endl;
995 }
996
997 result
998 << std::endl
999 << "immediate unit accesses:" << std::endl
1000 << std::endl;
1001
1004 for (
int i = 0; i < iuNav.
count(); ++i) {
1007
1008 result
1009 << iu->
name() <<
":" << std::endl;
1010
1011 int usedRegCount = 0;
1012 int lastReg = 0;
1014
1015 for (int reg = 0; reg <= lastReg; ++reg) {
1020 ++usedRegCount;
1021 result
1022 << std::left << std::setw(COLUMN_WIDTH)
1023 << reg << " "
1024 << std::left << std::setw(COLUMN_WIDTH)
1026 << std::left << std::setw(COLUMN_WIDTH)
1028 << std::endl;
1029 }
1030 result
1031 << "TOTAL " << usedRegCount << " registers used"
1032 << std::endl << std::endl;
1033 }
1034
1035
1036 if (
parent().simulatorFrontend().rfAccessTracing()) {
1037
1038 try {
1041
1042 result
1043 << std::endl
1044 << "register file accesses" << std::endl
1045 << "----------------------" << std::endl;
1046
1047 const int COL_WIDTH = 20;
1048
1049 result
1050 << std::left << std::setw(COL_WIDTH)
1051 << "register file"
1052 << std::left << std::setw(COL_WIDTH)
1053 << "writes"
1054 << std::left << std::setw(COL_WIDTH)
1055 << "reads"
1056 << std::left << std::setw(COL_WIDTH)
1057 << "count" << std::endl;
1058
1059 RFAccessTracker::ConcurrentRFAccessIndex::
1060 const_iterator i =
1062
1064 result
1065 << std::left << std::setw(COL_WIDTH)
1066 << (*i).first.get<0>()
1067 << std::left << std::setw(COL_WIDTH)
1068 << (*i).first.get<1>()
1069 << std::left << std::setw(COL_WIDTH)
1070 << (*i).first.get<2>()
1071 << std::left << std::setw(COL_WIDTH)
1072 << (*i).second << std::endl;
1073 }
1075 }
1076 }
1077
1079 return true;
1080
1081 } else if (command == "mapping") {
1086 for (
int i = 0; i < nav.
count(); ++i) {
1088 unsigned int sizeOfSpace = space.
end() - space.
start();
1090 << std::left << std::setw(15)
1092 << std::left
1094 << " - "
1096 << " (" << sizeOfSpace << " ";
1097 if (space.
width() == 8) {
1099 } else {
1101 <<
"words of size " << space.
width() <<
" bits";
1102 }
1104 }
1105 return true;
1106 } else {
1110 return false;
1111 }
1112 }
#define assert(condition)
CycleCount ClockCycleCount
Alias for ClockCycleCount.
static std::string toHexString(T source, std::size_t digits=0, bool include0x=true)
static std::string toString(const T &source)
ScriptInterpreter * interpreter() const
const ConcurrentRFAccessIndex & accessDataBase() const
virtual void setError(bool state)
virtual void setResult(DataObject *result)
SimulatorFrontend & simulatorFrontend()
virtual std::ostream & outputStream()
virtual SimControlLanguageCommand & parent()
const TTAMachine::Machine & machine() const
const UtilizationStats & utilizationStatistics(int core=-1)
ClockCycleCount cycleCount() const
const RFAccessTracker & rfAccessTracker() const
virtual ULongWord end() const
virtual int width() const
virtual ULongWord start() const
virtual int numberOfRegisters() const
virtual TCEString name() const
virtual HWOperation * operation(const std::string &name) const
virtual int operationCount() const
const std::string & name() const
ComponentType * item(int index) const
virtual RegisterFileNavigator registerFileNavigator() const
virtual FunctionUnitNavigator functionUnitNavigator() const
virtual SocketNavigator socketNavigator() const
virtual ImmediateUnitNavigator immediateUnitNavigator() const
virtual BusNavigator busNavigator() const
virtual AddressSpaceNavigator addressSpaceNavigator() const
virtual ControlUnit * controlUnit() const
std::map< std::string, ComponentUtilizationIndex > FUOperationUtilizationIndex
Index for connecting function unit and operations implemented in them to utilization counts.
ClockCycleCount busWrites(const std::string &busName) const
ClockCycleCount operationExecutions(const std::string &operationName) const
ClockCycleCount triggerCount(const std::string &fuName) const
ClockCycleCount guardRegisterReads(const std::string &rfName, int registerIndex) const
ClockCycleCount registerReads(const std::string &rfName, int registerIndex) const
ClockCycleCount FUGuardAccesses(const std::string &fuName, const std::string &fuPort) const
ClockCycleCount registerWrites(const std::string &rfName, int registerIndex) const
ClockCycleCount socketWrites(const std::string &socketName) const