OpenASIP 2.2
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Public Member Functions | List of all members
InfoProcCommand Class Reference
Inheritance diagram for InfoProcCommand:
Inheritance graph
Collaboration diagram for InfoProcCommand:
Collaboration graph

Public Member Functions

 InfoProcCommand (SimControlLanguageCommand &parentCommand)
 
virtual ~InfoProcCommand ()
 
virtual bool execute (const std::vector< DataObject > &arguments)
 
- Public Member Functions inherited from SimControlLanguageSubCommand
 SimControlLanguageSubCommand (SimControlLanguageCommand &parentCommand)
 
virtual ~SimControlLanguageSubCommand ()
 
virtual SimControlLanguageCommandparent ()
 

Detailed Description

Implementation of "info proc".

Definition at line 721 of file InfoCommand.cc.

Constructor & Destructor Documentation

◆ InfoProcCommand()

InfoProcCommand::InfoProcCommand ( SimControlLanguageCommand parentCommand)
inline

Constructor.

Definition at line 726 of file InfoCommand.cc.

◆ ~InfoProcCommand()

virtual InfoProcCommand::~InfoProcCommand ( )
inlinevirtual

Destructor.

Definition at line 733 of file InfoCommand.cc.

733 {
734 }

Member Function Documentation

◆ execute()

virtual bool InfoProcCommand::execute ( const std::vector< DataObject > &  arguments)
inlinevirtual

Executes the "info proc" command.

Parameters
argumentsArguments to the command, including the command.
Returns
true in case execution was successful.

Implements SimControlLanguageSubCommand.

Definition at line 742 of file InfoCommand.cc.

742 {
743
744 if (!parent().checkSimulationEnded() &&
745 !parent().checkSimulationInitialized() &&
746 !parent().checkSimulationStopped() &&
747 !parent().simulatorFrontend().isSimulationRunning()) {
748
749 return false;
750 }
751
752 const int argumentCount = arguments.size() - 2;
753
754 if (!parent().checkArgumentCount(argumentCount, 1, 1)) {
755 return false;
756 }
757
758 const std::string command =
759 StringTools::stringToLower(arguments[2].stringValue());
760
761 if (command == "cycles") {
763 (boost::format("%.0f") %
764 parent().simulatorFrontend().cycleCount()).str());
765 return true;
766 } else if (command == "stats") {
767 std::stringstream result;
768
769 const ClockCycleCount totalCycles =
771
772 const UtilizationStats& stats =
774
775 result
776 << std::endl
777 << "utilizations" << std::endl
778 << "------------" << std::endl;
779
780 const int COLUMN_WIDTH = 15;
781 const TTAMachine::Machine& mach =
783 std::set<std::string> operationsOfMachine;
784
785 result
786 << std::endl << "buses:" << std::endl << std::endl;
787
789 mach.busNavigator();
790
791 for (int i = 0; i < busNav.count(); ++i) {
792 TTAMachine::Bus* bus = busNav.item(i);
793 assert(bus != NULL);
794 const ClockCycleCount writes =
795 stats.busWrites(bus->name());
796
797 result
798 << std::left << std::setw(COLUMN_WIDTH)
799 << bus->name() << " "
800 << std::left << std::setw(COLUMN_WIDTH)
801 << Conversion::toString(writes * 100.0 / totalCycles) +
802 "% (" + Conversion::toString(writes) + " writes)"
803 << std::endl;
804 }
805
806 result
807 << std::endl
808 << "sockets:" << std::endl << std::endl;
809
810 const TTAMachine::Machine::SocketNavigator& socketNav =
811 mach.socketNavigator();
812 for (int i = 0; i < socketNav.count(); ++i) {
813 TTAMachine::Socket* socket = socketNav.item(i);
814 assert(socket != NULL);
815 const ClockCycleCount writes =
816 stats.socketWrites(socket->name());
817
818 result
819 << std::left << std::setw(COLUMN_WIDTH)
820 << socket->name() << " "
821 << std::left << std::setw(COLUMN_WIDTH)
822 << Conversion::toString(writes * 100.0 / totalCycles) +
823 "% (" + Conversion::toString(writes) + " writes)"
824 << std::endl;
825 }
826
827 result
828 << std::endl
829 << "operations executed in function units:"
830 << std::endl << std::endl;
831
834 for (int i = 0; i <= fuNav.count(); ++i) {
835 TTAMachine::FunctionUnit* fu = NULL;
836 if (i < fuNav.count())
837 fu = fuNav.item(i);
838 else
839 fu = mach.controlUnit();
840 assert(fu != NULL);
841 const ClockCycleCount totalTriggersOfFU =
842 stats.triggerCount(fu->name());
843
844 result
845 << fu->name() << ":" << std::endl;
846
847 for (int j = 0; j < fu->operationCount(); ++j) {
848 const TTAMachine::HWOperation* op = fu->operation(j);
849 assert(op != NULL);
850 const std::string operationUpper =
852 operationsOfMachine.insert(operationUpper);
853 const ClockCycleCount executions =
855 fu->name(), operationUpper);
856
857 result
858 << std::left << std::setw(COLUMN_WIDTH)
859 << operationUpper << " "
860 << std::left << std::setw(COLUMN_WIDTH)
862 executions * 100.0 / totalTriggersOfFU) +
863 "% of FU total (" +
864 Conversion::toString(executions) + " executions)"
865 << std::endl;
866 }
867
868 result
869 << std::left << std::setw(COLUMN_WIDTH)
870 << "TOTAL" << " "
871 << std::left << std::setw(COLUMN_WIDTH)
873 totalTriggersOfFU * 100.0 / totalCycles) + "% (" +
874 Conversion::toString(totalTriggersOfFU) +
875 " triggers)" << std::endl << std::endl;
876 }
877
878 const TTAMachine::FunctionUnit& gcu = *mach.controlUnit();
879 for (int j = 0; j < gcu.operationCount(); ++j) {
880 const TTAMachine::HWOperation* op = gcu.operation(j);
881 assert(op != NULL);
882 const std::string operationUpper =
884 operationsOfMachine.insert(operationUpper);
885 }
886
887 result
888 << std::endl << "operations:" << std::endl << std::endl;
889
890 for (std::set<std::string>::iterator i =
891 operationsOfMachine.begin(); i !=
892 operationsOfMachine.end(); ++i) {
893 const ClockCycleCount executions =
894 stats.operationExecutions(*i);
895
896 result
897 << std::left << std::setw(COLUMN_WIDTH)
898 << *i << " " << std::left << std::setw(COLUMN_WIDTH)
899 << Conversion::toString(executions * 100.0 / totalCycles) +
900 "% (" + Conversion::toString(executions) + " executions)"
901 << std::endl;
902 }
903
904 result
905 << std::endl
906 << "FU port guard accesses:" << std::endl;
907
909 stats.FUGuardAccesses();
910
911 // loop each FU
912 for (UtilizationStats::FUOperationUtilizationIndex::iterator i =
913 fuGuardAccesses.begin(); i != fuGuardAccesses.end(); ++i) {
914
915 std::string fuName = i->first;
916
917 result
918 << std::endl
919 << fuName << ":"
920 << std::endl;
921
922 // loop each FU port in the utilization list
923 for (UtilizationStats::ComponentUtilizationIndex::iterator j =
924 i->second.begin(); j != i->second.end(); ++j) {
925 std::string fuPort = j->first;
926
927 ClockCycleCount count =
928 stats.FUGuardAccesses(fuName, fuPort);
929 result
930 << std::left << std::setw(COLUMN_WIDTH)
931 << fuPort << ": "
932 << Conversion::toString(count) << " reads"
933 << std::endl;
934 }
935 }
936
937 result
938 << std::endl
939 << "register accesses:" << std::endl
940 << std::endl;
941
944 for (int i = 0; i < rfNav.count(); ++i) {
945 TTAMachine::RegisterFile* rf = rfNav.item(i);
946 assert(rf != NULL);
947
948 result
949 << rf->name() << ":" << std::endl;
950
951 int regsUsedInFile = 0;
952 int lastReg = 0;
953 int totalReads = 0;
954 int totalWrites = 0;
955 int totalGuards = 0;
956 lastReg = rf->numberOfRegisters() - 1;
957
958 for (int reg = 0; reg <= lastReg; ++reg) {
959 ClockCycleCount reads =
960 stats.registerReads(rf->name(), reg);
961 totalReads += reads;
962 ClockCycleCount guardReads =
963 stats.guardRegisterReads(rf->name(), reg);
964 totalGuards += guardReads;
965 ClockCycleCount writes =
966 stats.registerWrites(rf->name(), reg);
967 totalWrites += writes;
968 ++regsUsedInFile;
969 result
970 << std::left << std::setw(COLUMN_WIDTH)
971 << reg << " "
972 << std::left << std::setw(COLUMN_WIDTH)
973 << Conversion::toString(reads) + " reads, "
974 << std::left << std::setw(COLUMN_WIDTH + 5)
975 << Conversion::toString(guardReads) + " guard reads, "
976 << std::left << std::setw(COLUMN_WIDTH)
977 << Conversion::toString(writes) + " writes"
978 << std::endl;
979 }
980
981 result
982 << std::left << std::setw(COLUMN_WIDTH)
983 << "TOTAL"
984 << std::left << std::setw(COLUMN_WIDTH)
985 << Conversion::toString(totalReads) + " reads, "
986 << std::left << std::setw(COLUMN_WIDTH + 5)
987 << Conversion::toString(totalGuards) + " guard reads, "
988 << std::left << std::setw(COLUMN_WIDTH)
989 << Conversion::toString(totalWrites) + " writes"
990 << std::endl;
991
992 result
993 << "TOTAL " << regsUsedInFile << " registers used"
994 << std::endl << std::endl;
995 }
996
997 result
998 << std::endl
999 << "immediate unit accesses:" << std::endl
1000 << std::endl;
1001
1004 for (int i = 0; i < iuNav.count(); ++i) {
1005 TTAMachine::ImmediateUnit* iu = iuNav.item(i);
1006 assert(iu != NULL);
1007
1008 result
1009 << iu->name() << ":" << std::endl;
1010
1011 int usedRegCount = 0;
1012 int lastReg = 0;
1013 lastReg = iu->numberOfRegisters() - 1;
1014
1015 for (int reg = 0; reg <= lastReg; ++reg) {
1016 ClockCycleCount reads =
1017 stats.registerReads(iu->name(), reg);
1018 ClockCycleCount writes =
1019 stats.registerWrites(iu->name(), reg);
1020 ++usedRegCount;
1021 result
1022 << std::left << std::setw(COLUMN_WIDTH)
1023 << reg << " "
1024 << std::left << std::setw(COLUMN_WIDTH)
1025 << Conversion::toString(reads) + " reads, "
1026 << std::left << std::setw(COLUMN_WIDTH)
1027 << Conversion::toString(writes) + " writes"
1028 << std::endl;
1029 }
1030 result
1031 << "TOTAL " << usedRegCount << " registers used"
1032 << std::endl << std::endl;
1033 }
1034
1035
1036 if (parent().simulatorFrontend().rfAccessTracing()) {
1037
1038 try {
1039 const RFAccessTracker& rfAccessTracker =
1041
1042 result
1043 << std::endl
1044 << "register file accesses" << std::endl
1045 << "----------------------" << std::endl;
1046
1047 const int COL_WIDTH = 20;
1048
1049 result
1050 << std::left << std::setw(COL_WIDTH)
1051 << "register file"
1052 << std::left << std::setw(COL_WIDTH)
1053 << "writes"
1054 << std::left << std::setw(COL_WIDTH)
1055 << "reads"
1056 << std::left << std::setw(COL_WIDTH)
1057 << "count" << std::endl;
1058
1059 RFAccessTracker::ConcurrentRFAccessIndex::
1060 const_iterator i =
1061 rfAccessTracker.accessDataBase().begin();
1062
1063 for (; i != rfAccessTracker.accessDataBase().end(); ++i) {
1064 result
1065 << std::left << std::setw(COL_WIDTH)
1066 << (*i).first.get<0>()
1067 << std::left << std::setw(COL_WIDTH)
1068 << (*i).first.get<1>()
1069 << std::left << std::setw(COL_WIDTH)
1070 << (*i).first.get<2>()
1071 << std::left << std::setw(COL_WIDTH)
1072 << (*i).second << std::endl;
1073 }
1074 } catch (const InstanceNotFound&) {
1075 }
1076 }
1077
1078 parent().interpreter()->setResult(result.str());
1079 return true;
1080
1081 } else if (command == "mapping") {
1082 const TTAMachine::Machine& mach =
1085 mach.addressSpaceNavigator();
1086 for (int i = 0; i < nav.count(); ++i) {
1087 TTAMachine::AddressSpace& space = *nav.item(i);
1088 unsigned int sizeOfSpace = space.end() - space.start();
1090 << std::left << std::setw(15)
1091 << space.name()
1092 << std::left
1093 << Conversion::toHexString(space.start(), 8)
1094 << " - "
1095 << Conversion::toHexString(space.end(), 8)
1096 << " (" << sizeOfSpace << " ";
1097 if (space.width() == 8) {
1098 parent().outputStream() << "bytes";
1099 } else {
1101 << "words of size " << space.width() << " bits";
1102 }
1103 parent().outputStream() << ")" << std::endl;
1104 }
1105 return true;
1106 } else {
1110 return false;
1111 }
1112 }
#define assert(condition)
CycleCount ClockCycleCount
Alias for ClockCycleCount.
static std::string toHexString(T source, std::size_t digits=0, bool include0x=true)
static std::string toString(const T &source)
ScriptInterpreter * interpreter() const
const ConcurrentRFAccessIndex & accessDataBase() const
virtual void setError(bool state)
virtual void setResult(DataObject *result)
virtual std::ostream & outputStream()
virtual SimControlLanguageCommand & parent()
const TTAMachine::Machine & machine() const
const UtilizationStats & utilizationStatistics(int core=-1)
ClockCycleCount cycleCount() const
const RFAccessTracker & rfAccessTracker() const
static SimulatorTextGenerator & textGenerator()
static std::string stringToUpper(const std::string &source)
static std::string stringToLower(const std::string &source)
virtual ULongWord end() const
virtual int width() const
virtual ULongWord start() const
virtual int numberOfRegisters() const
virtual TCEString name() const
virtual HWOperation * operation(const std::string &name) const
virtual int operationCount() const
const std::string & name() const
ComponentType * item(int index) const
virtual RegisterFileNavigator registerFileNavigator() const
Definition Machine.cc:450
virtual FunctionUnitNavigator functionUnitNavigator() const
Definition Machine.cc:380
virtual SocketNavigator socketNavigator() const
Definition Machine.cc:368
virtual ImmediateUnitNavigator immediateUnitNavigator() const
Definition Machine.cc:416
virtual BusNavigator busNavigator() const
Definition Machine.cc:356
virtual AddressSpaceNavigator addressSpaceNavigator() const
Definition Machine.cc:392
virtual ControlUnit * controlUnit() const
Definition Machine.cc:345
std::map< std::string, ComponentUtilizationIndex > FUOperationUtilizationIndex
Index for connecting function unit and operations implemented in them to utilization counts.
ClockCycleCount busWrites(const std::string &busName) const
ClockCycleCount operationExecutions(const std::string &operationName) const
ClockCycleCount triggerCount(const std::string &fuName) const
ClockCycleCount guardRegisterReads(const std::string &rfName, int registerIndex) const
ClockCycleCount registerReads(const std::string &rfName, int registerIndex) const
ClockCycleCount FUGuardAccesses(const std::string &fuName, const std::string &fuPort) const
ClockCycleCount registerWrites(const std::string &rfName, int registerIndex) const
ClockCycleCount socketWrites(const std::string &socketName) const
@ TXT_UNKNOWN_SUBCOMMAND

References RFAccessTracker::accessDataBase(), TTAMachine::Machine::addressSpaceNavigator(), assert, TTAMachine::Machine::busNavigator(), UtilizationStats::busWrites(), TTAMachine::Machine::controlUnit(), TTAMachine::Machine::Navigator< ComponentType >::count(), SimulatorFrontend::cycleCount(), TTAMachine::AddressSpace::end(), UtilizationStats::FUGuardAccesses(), TTAMachine::Machine::functionUnitNavigator(), UtilizationStats::guardRegisterReads(), TTAMachine::Machine::immediateUnitNavigator(), CustomCommand::interpreter(), TTAMachine::Machine::Navigator< ComponentType >::item(), SimulatorFrontend::machine(), TTAMachine::HWOperation::name(), TTAMachine::Component::name(), TTAMachine::BaseRegisterFile::numberOfRegisters(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), UtilizationStats::operationExecutions(), SimControlLanguageCommand::outputStream(), SimControlLanguageSubCommand::parent(), TTAMachine::Machine::registerFileNavigator(), UtilizationStats::registerReads(), UtilizationStats::registerWrites(), SimulatorFrontend::rfAccessTracker(), ScriptInterpreter::setError(), ScriptInterpreter::setResult(), SimControlLanguageCommand::simulatorFrontend(), TTAMachine::Machine::socketNavigator(), UtilizationStats::socketWrites(), TTAMachine::AddressSpace::start(), StringTools::stringToLower(), StringTools::stringToUpper(), SimulatorToolbox::textGenerator(), Conversion::toHexString(), Conversion::toString(), UtilizationStats::triggerCount(), Texts::TXT_UNKNOWN_SUBCOMMAND, SimulatorFrontend::utilizationStatistics(), and TTAMachine::AddressSpace::width().

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The documentation for this class was generated from the following file: