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42 "altera_onchip_rom_comp.vhd";
50 std::ostream& warningStream,
51 std::ostream& errorStream):
53 integrator, warningStream, errorStream) {
55 bool noInvert =
false;
66 new HDLPort(
"q",
"IMEMWIDTHINMAUS*IMEMMAUWIDTH",
86 std::vector<TCEString>
100 TCEString addrwGeneric =
"IMEMADDRWIDTH";
101 TCEString datawGeneric =
"IMEMWIDTHINMAUS*IMEMMAUWIDTH";
102 addGenerics(integratorBlock, addrwGeneric, datawGeneric, memIndex);
@ GND
All port signals set to low.
void addPort(const TCEString &name, HDLPort *port)
@ BIT_VECTOR
Several bits.
TCEString ttaCoreName() const
TCEString memoryIndexString(int coreId, int memIndex) const
virtual std::vector< TCEString > generateComponentFile(TCEString outputPath)
virtual void addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
virtual bool generatesComponentHdlFile() const
virtual ~AlteraOnchipRomGenerator()
static const TCEString COMPONENT_FILE
virtual TCEString moduleName() const
virtual TCEString instanceName(int coreId, int memIndex) const
virtual void addGenerics(ProGe::NetlistBlock &topBlock, const TCEString &addrWidth, const TCEString &dataWidth, int memIndex)
AlteraOnchipRomGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
std::vector< TCEString > instantiateAlteraTemplate(const TCEString &templateFile, const TCEString &outputPath) const
void setToStatic(ProGe::StaticSignal value)
virtual void addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)