OpenASIP  2.0
AlteraOnchipRomGenerator.cc
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1 /*
2  Copyright (c) 2002-2010 Tampere University.
3 
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24 /**
25  * @file AlteraOnchipRomGenerator.cc
26  *
27  * Implementation of AlteraOnchipRomGenerator class.
28  *
29  * @author Otto Esko 2010 (otto.esko-no.spam-tut.fi)
30  * @note rating: red
31  */
32 
33 #include <iostream>
34 #include <vector>
36 #include "PlatformIntegrator.hh"
37 #include "HDLPort.hh"
38 using std::endl;
40 
42  "altera_onchip_rom_comp.vhd";
43 
45  int memMauWidth,
46  int widthInMaus,
47  int addrWidth,
48  TCEString initFile,
49  const PlatformIntegrator* integrator,
50  std::ostream& warningStream,
51  std::ostream& errorStream):
52  AlteraMemGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
53  integrator, warningStream, errorStream) {
54 
55  bool noInvert = false;
56  bool inverted = true;
57 
58  addPort("clk",
59  new HDLPort("clock", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
60  addPort("imem_addr",
61  new HDLPort("address", "IMEMADDRWIDTH", ProGe::BIT_VECTOR,
62  ProGe::IN, noInvert));
63  addPort("imem_en_x",
64  new HDLPort("clken", "1", ProGe::BIT, ProGe::IN, inverted, 1));
65  addPort("imem_data",
66  new HDLPort("q", "IMEMWIDTHINMAUS*IMEMMAUWIDTH",
67  ProGe::BIT_VECTOR, ProGe::OUT, noInvert));
68 
69  // these signals are not driven by the imem component, connect to zero
70  HDLPort* busyToGnd =
71  new HDLPort("wait", "1", ProGe::BIT, ProGe::OUT, noInvert, 1);
73  addPort("busy", busyToGnd);
74 }
75 
76 
78 }
79 
80 bool
82  return true;
83 }
84 
85 
86 std::vector<TCEString>
88 
89  return instantiateAlteraTemplate(COMPONENT_FILE, outputPath);
90 }
91 
92 void
94  const ProGe::NetlistBlock& ttaCore,
95  ProGe::NetlistBlock& integratorBlock,
96  int memIndex,
97  int coreId) {
98 
99  // Add generics as string constants!
100  TCEString addrwGeneric = "IMEMADDRWIDTH";
101  TCEString datawGeneric = "IMEMWIDTHINMAUS*IMEMMAUWIDTH";
102  addGenerics(integratorBlock, addrwGeneric, datawGeneric, memIndex);
103 
104  MemoryGenerator::addMemory(ttaCore, integratorBlock, memIndex, coreId);
105 }
106 
107 TCEString
109 
110  return ttaCoreName() + "_altera_onchip_rom_comp";
111 }
112 
113 
114 TCEString
115 AlteraOnchipRomGenerator::instanceName(int coreId, int memIndex) const {
116 
117  TCEString iname("onchip_imem_");
118  return iname << memoryIndexString(coreId, memIndex);
119 }
ProGe::StaticSignal::GND
@ GND
All port signals set to low.
Definition: NetlistPort.hh:50
AlteraMemGenerator
Definition: AlteraMemGenerator.hh:43
ProGe::NetlistBlock
Definition: NetlistBlock.hh:61
MemoryGenerator::addPort
void addPort(const TCEString &name, HDLPort *port)
Definition: MemoryGenerator.cc:294
HDLPort
Definition: PlatformIntegrator/HDLPort.hh:48
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
MemoryGenerator::ttaCoreName
TCEString ttaCoreName() const
Definition: MemoryGenerator.cc:319
MemoryGenerator::memoryIndexString
TCEString memoryIndexString(int coreId, int memIndex) const
Definition: MemoryGenerator.cc:383
AlteraOnchipRomGenerator::generateComponentFile
virtual std::vector< TCEString > generateComponentFile(TCEString outputPath)
Definition: AlteraOnchipRomGenerator.cc:87
MemoryGenerator::addMemory
virtual void addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
Definition: MemoryGenerator.cc:119
AlteraOnchipRomGenerator::generatesComponentHdlFile
virtual bool generatesComponentHdlFile() const
Definition: AlteraOnchipRomGenerator.cc:81
AlteraOnchipRomGenerator::~AlteraOnchipRomGenerator
virtual ~AlteraOnchipRomGenerator()
Definition: AlteraOnchipRomGenerator.cc:77
AlteraOnchipRomGenerator::COMPONENT_FILE
static const TCEString COMPONENT_FILE
Definition: AlteraOnchipRomGenerator.hh:76
ProGe::StaticSignal
Definition: NetlistPort.hh:47
AlteraOnchipRomGenerator::moduleName
virtual TCEString moduleName() const
Definition: AlteraOnchipRomGenerator.cc:108
HDLPort.hh
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
AlteraOnchipRomGenerator::instanceName
virtual TCEString instanceName(int coreId, int memIndex) const
Definition: AlteraOnchipRomGenerator.cc:115
AlteraMemGenerator::addGenerics
virtual void addGenerics(ProGe::NetlistBlock &topBlock, const TCEString &addrWidth, const TCEString &dataWidth, int memIndex)
Definition: AlteraMemGenerator.cc:96
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
AlteraOnchipRomGenerator::AlteraOnchipRomGenerator
AlteraOnchipRomGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
Definition: AlteraOnchipRomGenerator.cc:44
AlteraMemGenerator::instantiateAlteraTemplate
std::vector< TCEString > instantiateAlteraTemplate(const TCEString &templateFile, const TCEString &outputPath) const
Definition: AlteraMemGenerator.cc:62
HDLPort::setToStatic
void setToStatic(ProGe::StaticSignal value)
Definition: HDLPort.cc:145
AlteraOnchipRomGenerator::addMemory
virtual void addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
Definition: AlteraOnchipRomGenerator.cc:93
TCEString
Definition: TCEString.hh:53
PlatformIntegrator.hh
PlatformIntegrator
Definition: PlatformIntegrator.hh:65
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53
AlteraOnchipRomGenerator.hh