OpenASIP  2.0
Public Member Functions | Protected Member Functions | Static Private Attributes | List of all members
AlteraOnchipRomGenerator Class Reference

#include <AlteraOnchipRomGenerator.hh>

Inheritance diagram for AlteraOnchipRomGenerator:
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Collaboration diagram for AlteraOnchipRomGenerator:
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Public Member Functions

 AlteraOnchipRomGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
 
virtual ~AlteraOnchipRomGenerator ()
 
virtual bool generatesComponentHdlFile () const
 
virtual std::vector< TCEStringgenerateComponentFile (TCEString outputPath)
 
virtual void addMemory (const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
 
- Public Member Functions inherited from AlteraMemGenerator
 AlteraMemGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
 
virtual ~AlteraMemGenerator ()
 
- Public Member Functions inherited from MemoryGenerator
 MemoryGenerator (int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
 
virtual ~MemoryGenerator ()
 
virtual bool isCompatible (const ProGe::NetlistBlock &ttaCore, int coreId, std::vector< TCEString > &reasons) const
 
int memoryTotalWidth () const
 
int memoryMauSize () const
 
int memoryWidthInMaus () const
 
int memoryAddrWidth () const
 
TCEString initializationFile () const
 
void addLsu (TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)
 

Protected Member Functions

virtual TCEString moduleName () const
 
virtual TCEString instanceName (int coreId, int memIndex) const
 
- Protected Member Functions inherited from AlteraMemGenerator
std::vector< TCEStringinstantiateAlteraTemplate (const TCEString &templateFile, const TCEString &outputPath) const
 
virtual void addGenerics (ProGe::NetlistBlock &topBlock, const TCEString &addrWidth, const TCEString &dataWidth, int memIndex)
 
- Protected Member Functions inherited from MemoryGenerator
virtual bool checkFuPort (const std::string fuPort, std::vector< TCEString > &reasons) const
 
virtual void connectPorts (ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)
 
virtual MemoryGenerator::BlockPair createMemoryNetlistBlock (ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
 
const PlatformIntegratorplatformIntegrator () const
 
std::ostream & warningStream ()
 
std::ostream & errorStream ()
 
int portCount () const
 
const HDLPortport (int index) const
 
const HDLPortportByKeyName (TCEString name) const
 
TCEString portKeyName (const HDLPort *port) const
 
void addPort (const TCEString &name, HDLPort *port)
 
int parameterCount () const
 
const ProGe::Parameterparameter (int index) const
 
void addParameter (const ProGe::Parameter &add)
 
TCEString ttaCoreName () const
 
TCEString memoryIndexString (int coreId, int memIndex) const
 
TCEString templatePath () const
 
void instantiateTemplate (const TCEString &inFile, const TCEString &outFile, const TCEString &entity) const
 
bool hasLSUArchitecture () const
 
const TTAMachine::FunctionUnitlsuArchitecture () const
 
TCEString corePortName (const TCEString &portBaseName, int coreId) const
 

Static Private Attributes

static const TCEString COMPONENT_FILE
 

Additional Inherited Members

- Protected Types inherited from MemoryGenerator
typedef std::multimap< TCEString, HDLPort * > PortMap
 
typedef std::pair< ProGe::NetlistBlock *, ProGe::VirtualNetlistBlock * > BlockPair
 
- Static Protected Attributes inherited from AlteraMemGenerator
static const TCEString INIT_FILE_G = "init_file_g"
 
static const TCEString DEV_FAMILY_G = "dev_family_g"
 
static const TCEString ADDRW_G = "addrw_g"
 
static const TCEString DATAW_G = "dataw_g"
 

Detailed Description

Definition at line 43 of file AlteraOnchipRomGenerator.hh.

Constructor & Destructor Documentation

◆ AlteraOnchipRomGenerator()

AlteraOnchipRomGenerator::AlteraOnchipRomGenerator ( int  memMauWidth,
int  widthInMaus,
int  addrWidth,
TCEString  initFile,
const PlatformIntegrator integrator,
std::ostream &  warningStream,
std::ostream &  errorStream 
)

Definition at line 44 of file AlteraOnchipRomGenerator.cc.

51  :
52  AlteraMemGenerator(memMauWidth, widthInMaus, addrWidth, initFile,
53  integrator, warningStream, errorStream) {
54 
55  bool noInvert = false;
56  bool inverted = true;
57 
58  addPort("clk",
59  new HDLPort("clock", "1", ProGe::BIT, ProGe::IN, noInvert, 1));
60  addPort("imem_addr",
61  new HDLPort("address", "IMEMADDRWIDTH", ProGe::BIT_VECTOR,
62  ProGe::IN, noInvert));
63  addPort("imem_en_x",
64  new HDLPort("clken", "1", ProGe::BIT, ProGe::IN, inverted, 1));
65  addPort("imem_data",
66  new HDLPort("q", "IMEMWIDTHINMAUS*IMEMMAUWIDTH",
67  ProGe::BIT_VECTOR, ProGe::OUT, noInvert));
68 
69  // these signals are not driven by the imem component, connect to zero
70  HDLPort* busyToGnd =
71  new HDLPort("wait", "1", ProGe::BIT, ProGe::OUT, noInvert, 1);
73  addPort("busy", busyToGnd);
74 }

References MemoryGenerator::addPort(), ProGe::BIT, ProGe::BIT_VECTOR, ProGe::StaticSignal::GND, ProGe::IN, ProGe::OUT, and HDLPort::setToStatic().

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◆ ~AlteraOnchipRomGenerator()

AlteraOnchipRomGenerator::~AlteraOnchipRomGenerator ( )
virtual

Definition at line 77 of file AlteraOnchipRomGenerator.cc.

77  {
78 }

Member Function Documentation

◆ addMemory()

void AlteraOnchipRomGenerator::addMemory ( const ProGe::NetlistBlock ttaCore,
ProGe::NetlistBlock integratorBlock,
int  memIndex,
int  coreId 
)
virtual

Reimplemented from AlteraMemGenerator.

Definition at line 93 of file AlteraOnchipRomGenerator.cc.

97  {
98 
99  // Add generics as string constants!
100  TCEString addrwGeneric = "IMEMADDRWIDTH";
101  TCEString datawGeneric = "IMEMWIDTHINMAUS*IMEMMAUWIDTH";
102  addGenerics(integratorBlock, addrwGeneric, datawGeneric, memIndex);
103 
104  MemoryGenerator::addMemory(ttaCore, integratorBlock, memIndex, coreId);
105 }

References AlteraMemGenerator::addGenerics(), and MemoryGenerator::addMemory().

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◆ generateComponentFile()

std::vector< TCEString > AlteraOnchipRomGenerator::generateComponentFile ( TCEString  outputPath)
virtual

Implements MemoryGenerator.

Definition at line 87 of file AlteraOnchipRomGenerator.cc.

87  {
88 
89  return instantiateAlteraTemplate(COMPONENT_FILE, outputPath);
90 }

References COMPONENT_FILE, and AlteraMemGenerator::instantiateAlteraTemplate().

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◆ generatesComponentHdlFile()

bool AlteraOnchipRomGenerator::generatesComponentHdlFile ( ) const
virtual

Implements MemoryGenerator.

Definition at line 81 of file AlteraOnchipRomGenerator.cc.

81  {
82  return true;
83 }

◆ instanceName()

TCEString AlteraOnchipRomGenerator::instanceName ( int  coreId,
int  memIndex 
) const
protectedvirtual

Implements MemoryGenerator.

Definition at line 115 of file AlteraOnchipRomGenerator.cc.

115  {
116 
117  TCEString iname("onchip_imem_");
118  return iname << memoryIndexString(coreId, memIndex);
119 }

References MemoryGenerator::memoryIndexString().

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◆ moduleName()

TCEString AlteraOnchipRomGenerator::moduleName ( ) const
protectedvirtual

Implements MemoryGenerator.

Definition at line 108 of file AlteraOnchipRomGenerator.cc.

108  {
109 
110  return ttaCoreName() + "_altera_onchip_rom_comp";
111 }

References MemoryGenerator::ttaCoreName().

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Member Data Documentation

◆ COMPONENT_FILE

const TCEString AlteraOnchipRomGenerator::COMPONENT_FILE
staticprivate
Initial value:
=
"altera_onchip_rom_comp.vhd"

Definition at line 76 of file AlteraOnchipRomGenerator.hh.

Referenced by generateComponentFile().


The documentation for this class was generated from the following files:
ProGe::StaticSignal::GND
@ GND
All port signals set to low.
Definition: NetlistPort.hh:50
MemoryGenerator::addPort
void addPort(const TCEString &name, HDLPort *port)
Definition: MemoryGenerator.cc:294
HDLPort
Definition: PlatformIntegrator/HDLPort.hh:48
ProGe::BIT_VECTOR
@ BIT_VECTOR
Several bits.
Definition: ProGeTypes.hh:48
MemoryGenerator::ttaCoreName
TCEString ttaCoreName() const
Definition: MemoryGenerator.cc:319
MemoryGenerator::memoryIndexString
TCEString memoryIndexString(int coreId, int memIndex) const
Definition: MemoryGenerator.cc:383
MemoryGenerator::addMemory
virtual void addMemory(const ProGe::NetlistBlock &ttaCore, ProGe::NetlistBlock &integratorBlock, int memIndex, int coreId)
Definition: MemoryGenerator.cc:119
AlteraOnchipRomGenerator::COMPONENT_FILE
static const TCEString COMPONENT_FILE
Definition: AlteraOnchipRomGenerator.hh:76
ProGe::BIT
@ BIT
One bit.
Definition: ProGeTypes.hh:47
MemoryGenerator::warningStream
std::ostream & warningStream()
Definition: MemoryGenerator.cc:231
AlteraMemGenerator::AlteraMemGenerator
AlteraMemGenerator(int memMauWidth, int widthInMaus, int addrWidth, TCEString initFile, const PlatformIntegrator *integrator, std::ostream &warningStream, std::ostream &errorStream)
Definition: AlteraMemGenerator.cc:45
AlteraMemGenerator::addGenerics
virtual void addGenerics(ProGe::NetlistBlock &topBlock, const TCEString &addrWidth, const TCEString &dataWidth, int memIndex)
Definition: AlteraMemGenerator.cc:96
ProGe::OUT
@ OUT
Output port.
Definition: ProGeTypes.hh:54
AlteraMemGenerator::instantiateAlteraTemplate
std::vector< TCEString > instantiateAlteraTemplate(const TCEString &templateFile, const TCEString &outputPath) const
Definition: AlteraMemGenerator.cc:62
HDLPort::setToStatic
void setToStatic(ProGe::StaticSignal value)
Definition: HDLPort.cc:145
TCEString
Definition: TCEString.hh:53
MemoryGenerator::errorStream
std::ostream & errorStream()
Definition: MemoryGenerator.cc:237
ProGe::IN
@ IN
Input port.
Definition: ProGeTypes.hh:53