#include <HDLGenerator.hh>

Inheritance diagram for HDLGenerator::Module:

Collaboration diagram for HDLGenerator::Module:

Public Member Functions
	Module (std::string name)

	Module (ipxact::ModuleInfo info, int id)

void	set_header ()

void	set_prefix (std::string prefix)

Module &	operator<< (Behaviour &rhs)

Module &	operator<< (Behaviour &&rhs)

Module &	operator<< (Port &&port)

Module &	operator<< (Parameter &&param)

Module &	operator<< (IntegerConstant &&constant)

Module &	operator<< (BinaryConstant &&constant)

Module &	operator<< (Wire &&wire)

Module &	operator<< (Register &&reg)

Module &	operator<< (Register &reg)

Module &	operator<< (Option &&opt)

Module &	operator<< (Module &&rhs)

Module &	operator<< (Module &rhs)

void	build () final

void	appendToHeader (const std::string &line)

virtual bool	isRegister (const std::string &name) final

virtual bool	isConstant (const std::string &name) final

virtual bool	isVariable (const std::string &name) final

void	registerVariable (const std::shared_ptr< Variable > var)

Width	width (const std::string &name) final

WireType	wireType (const std::string &name) final

void	reads (const std::string &var) final

void	writes (const std::string &var) final

void	declare (std::ostream &stream, Language lang, int level)

void	instantiate (std::ostream &stream, Language lang, int level)

void	implement (std::ostream &stream, Language lang, int level=0)

bool	hasOption (const std::string &var) final

Register &	getRegister (const std::string &var) final

Public Member Functions inherited from HDLGenerator::Generatable
	Generatable (std::string name)

virtual	~Generatable ()=default

virtual void	reads (const LHSValue &var)

int	integerWidth (const std::string &name)

virtual Width	width ()

virtual WireType	wireType () const

virtual void	hdl (std::ostream &stream, Language lang, int indent)

virtual void	hdl (std::ostream &stream, Language lang)

virtual void	implementAll (std::ostream &stream, Language lang)

virtual void	implementAll (std::ostream &stream, Language lang, int indent)

template<typename Func >
void	forAll (Func func)

template<typename Type , typename Func >
void	forAll (Func func)

template<class Type >
bool	parentIs ()

template<class Type >
Type *	parentType ()

void	pushComponent (std::shared_ptr< Generatable > c)

template<class Component >
void	addComponent (Component c)

const std::string &	name () const noexcept

void	setParent (Generatable *parent) noexcept

Generatable *	parent () const noexcept

Private Member Functions
void	clear ()

Private Attributes
int	id_ = 0

std::string	prefix_

std::unordered_set< std::string >	options_

std::vector< std::string >	headerComment_

std::vector< Parameter >	parameters_

std::vector< Port >	ports_

std::vector< IntegerConstant >	constants_

std::vector< BinaryConstant >	binaryConstants_

std::vector< std::shared_ptr< Wire > >	wires_

std::vector< Register >	registers_

std::vector< std::shared_ptr< Variable > >	variables_

std::vector< std::shared_ptr< Behaviour > >	behaviours_

std::vector< Module >	modules_

Detailed Description

Entity/module.

Definition at line 1163 of file HDLGenerator.hh.

Constructor & Destructor Documentation

◆ Module() [1/2]

HDLGenerator::Module::Module ( std::string name )

inline

Definition at line 1165 of file HDLGenerator.hh.

                                : Generatable(name), prefix_(name) {
             set_header();
         }

References set_header().

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◆ Module() [2/2]

HDLGenerator::Module::Module	(	ipxact::ModuleInfo	info,
		int	id
	)

inline

Definition at line 1169 of file HDLGenerator.hh.

                                               : Generatable(info.name),
             prefix_(info.name) {
             set_header();
             id_ = id;
             for (auto&& p : info.parameters) {
                 parameters_.emplace_back(Parameter{p.name, p.value});
             }
             for (auto&& p : info.ports) {
                 Direction dir = p.direction == "in" ?
                                 Direction::In : Direction::Out;
                 if (p.vector) {
                     *this << Port(p.name, dir, p.left + "+1");
                 } else {
                     *this << Port(p.name, dir);
                 }
             }
         }

References id_, HDLGenerator::In, HDLGenerator::Generatable::name(), HDLGenerator::Out, ipxact::ModuleInfo::parameters, parameters_, ipxact::ModuleInfo::ports, and set_header().

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Member Function Documentation

◆ appendToHeader()

void HDLGenerator::Module::appendToHeader ( const std::string & line )

inline

Definition at line 1273 of file HDLGenerator.hh.

                                                    {
             headerComment_.emplace_back(line);
         }

References headerComment_.

◆ build()

void HDLGenerator::Module::build ( )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1266 of file HDLGenerator.hh.

                            {
             for (auto&& b : behaviours_) {
                 b->setParent(this);
                 b->build();
             }
         }

References behaviours_.

Referenced by implement().

◆ clear()

void HDLGenerator::Module::clear ( )

inlineprivate

Definition at line 1669 of file HDLGenerator.hh.

                      {
             // clear variables.
             variables_.clear();
             // Remove duplicate registers.
             registers_.erase(std::unique(registers_.begin(), registers_.end(),
                                  [](Register l, Register r) {
                                      return l.name() == r.name();
                                  }),
                 registers_.end());
         }

References registers_, and variables_.

Referenced by implement().

◆ declare()

void HDLGenerator::Module::declare	(	std::ostream &	stream,
		Language	lang,
		int	level
	)

inline

Definition at line 1378 of file HDLGenerator.hh.

                                                                    {
             if (lang == Language::VHDL) {
                 stream << StringTools::indent(level) << "component "
                        << name() << " is\n";
                 // - Generics
                 if (!parameters_.empty()) {
                     std::string separator = "";
                     stream << StringTools::indent(level + 1) << "generic (\n";
                     for (auto&& parameter : parameters_) {
                         stream << separator << StringTools::indent(level + 2);
                         parameter.declare(stream, lang);
                         separator = ";\n";
                     }
                     stream << ");\n";
                 }
                 // - Ports
                 if (!ports_.empty()) {
                     std::string separator = "";
                     stream << StringTools::indent(level + 1) << "port (\n";
                     for (auto&& port : ports_) {
                         stream << separator << StringTools::indent(level + 2);
                         port.declare(stream, lang);
                         separator = ";\n";
                     }
                     stream << ");\n";
                 }
                 stream << StringTools::indent(level) << "end component "
                        << name() << ";\n";
             } else if (lang == Language::Verilog) {
                 // no declaration for verilog.
             } else {
                 throw std::runtime_error(__PRETTY_FUNCTION__);
             }
         }

References StringTools::indent(), HDLGenerator::Generatable::name(), parameters_, ports_, HDLGenerator::Verilog, and HDLGenerator::VHDL.

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◆ getRegister()

Register& HDLGenerator::Module::getRegister ( const std::string & var )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1659 of file HDLGenerator.hh.

                                                           {
             for (auto&& r : registers_) {
                 if (r.name() == var) {
                     return r;
                 }
             }
             throw std::runtime_error("Couldn't find register '" + var + "'");
         }

References registers_.

◆ hasOption()

bool HDLGenerator::Module::hasOption ( const std::string & var )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1654 of file HDLGenerator.hh.

                                                    {
             return std::find(options_.begin(), options_.end(), var) !=
                    options_.end();
         }

References options_.

◆ implement()

void HDLGenerator::Module::implement	(	std::ostream &	stream,
		Language	lang,
		int	level = `0`
	)

inline

Definition at line 1476 of file HDLGenerator.hh.

                                                                          {
             clear();
             build();
             if (lang == Language::VHDL) {
                 std::string ident = StringTools::indent(level);
                 // Header comment
                 for (auto&& line : headerComment_) {
                     stream << ident <<  "-- " << line << "\n";
                 }
                 // Libraries
                 stream << ident << "\n"
                        << ident << "library ieee;\n"
                        << ident << "use ieee.std_logic_1164.all;\n"
                        << ident << "use ieee.numeric_std.all;\n"
                        << ident << "use ieee.std_logic_misc.all;\n"
                 // Entity
                        << ident << "\n"
                        << ident << "entity " << name() << " is\n";
                 // - Generics
                 if (!parameters_.empty()) {
                     std::string separator = "";
                     stream << StringTools::indent(level + 1) << "generic (\n";
                     for (auto&& parameter : parameters_) {
                         stream << separator;
                         parameter.declare(stream, lang, level + 2);
                         separator = ";\n";
                     }
                     stream << ");\n";
                 }
                 // - Ports
                 if (!ports_.empty()) {
                     std::string separator = "";
                     stream << StringTools::indent(level + 1) <<  "port (\n";
                     for (auto&& port : ports_) {
                         stream << separator;
                         port.declare(stream, lang, level + 2);
                         separator = ";\n";
                     }
                     stream << ");\n";
                 }
                 stream << ident << "end entity " << name() << ";\n"
                 // Architecture
                        << ident << "\n"
                        << ident << "architecture rtl of "
                                         << name() << " is\n";
                 // constants
                 if (!constants_.empty() || !binaryConstants_.empty()) {
                     stream << "\n";
                 }
                 for (auto&& c : constants_) {
                     c.declare(stream, lang, level + 1);
                 }
                 for (auto&& c : binaryConstants_) {
                     c.declare(stream, lang, level + 1);
                 }
                 // wires
                 if (!wires_.empty()) {
                     stream << "\n";
                 }
                 for (auto&& w : wires_) {
                     w->declare(stream, lang, level + 1);
                 }
                 // registers
                 if (!registers_.empty()) {
                     stream << "\n";
                 }
                 for (auto&& r : registers_) {
                     r.declare(stream, lang, level + 1);
                 }
                 // declare components
                 std::vector<std::string> declared;
                 for (auto&& m : modules_) {
                     if (std::find(declared.begin(), declared.end(),
                             m.name()) != declared.end()) {
                         continue;
                     }
                     stream << "\n";
                     m.declare(stream, lang, level + 1);
                     declared.emplace_back(m.name());
                 }
                 stream << StringTools::indent(level) << "\nbegin\n\n";
                 // instantiate components
                 for (auto&& m : modules_) {
                     m.instantiate(stream, lang, level + 1);
                     stream << "\n";
                 }
                 // actual behavioural code
                 for (auto&& b : behaviours_) {
                     b->behaviour(stream, lang, level + 1);
                 }
                 stream << "\n";
                 stream << StringTools::indent(level)
                        << "end architecture rtl;\n\n";
  
             } else if (lang == Language::Verilog) {
                 // Header comment
                 stream << StringTools::indent(level) << "/*\n";
                 for (auto&& line : headerComment_) {
                     stream << StringTools::indent(level)
                            << " * " << line << "\n";
                 }
                 stream << StringTools::indent(level) << " */\n";
                 // Module
                 stream << StringTools::indent(level) << "\n";
                 stream << StringTools::indent(level) << "module " << name();
                 // - Parameters
                 if (!parameters_.empty()) {
                     std::string separator = "";
                     stream << " #(\n";
                     for (auto&& parameter : parameters_) {
                         stream << separator;
                         parameter.declare(stream, lang, level + 2);
                         separator = ",\n";
                     }
                     stream << ")";
                 }
                 // - Ports
                 if (!ports_.empty()) {
                     std::string separator = "";
                     stream << " (\n";
                     for (auto&& port : ports_) {
                         stream << separator;
                         port.declare(stream, lang, level + 2);
                         separator = ",\n";
                     }
                     stream << ")";
                 }
                 // end module interface
                 stream << ";\n";
                 // constants
                 if (!constants_.empty() || !binaryConstants_.empty()) {
                     stream << "\n";
                 }
                 for (auto&& c : constants_) {
                     c.declare(stream, lang, level + 1);
                 }
                 for (auto&& c : binaryConstants_) {
                     c.declare(stream, lang, level + 1);
                 }
                 // wires
                 if (!wires_.empty()) {
                     stream << "\n";
                 }
                 for (auto&& w : wires_) {
                     w->declare(stream, lang, level + 1);
                 }
                 // variables
                 if (!variables_.empty()) {
                     stream << "\n";
                     for (auto&& v : variables_) {
                         v->declare(stream, lang, level + 1);
                     }
                 }
                 // registers
                 if (!registers_.empty()) {
                     stream << "\n";
                 }
                 for (auto&& r : registers_) {
                     r.declare(stream, lang, level + 1);
                 }
                 // instantiate stuff
                 for (auto&& m : modules_) {
                     stream << "\n";
                     m.instantiate(stream, lang, level + 1);
                 }
                 // actual code
                 stream << "\n";
                 for (auto&& b : behaviours_) {
                     b->behaviour(stream, lang, level + 1);
                 }
                 // end module
                 stream << "\n";
                 stream << StringTools::indent(level) << "endmodule\n\n";
             } else {
                 throw std::runtime_error(__PRETTY_FUNCTION__);
             }
         }

References behaviours_, binaryConstants_, build(), clear(), constants_, headerComment_, StringTools::indent(), modules_, HDLGenerator::Generatable::name(), parameters_, ports_, registers_, variables_, HDLGenerator::Verilog, HDLGenerator::VHDL, and wires_.

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◆ instantiate()

void HDLGenerator::Module::instantiate	(	std::ostream &	stream,
		Language	lang,
		int	level
	)

inline

Definition at line 1413 of file HDLGenerator.hh.

                                                                        {
             std::string instance = prefix_ + "_" + std::to_string(id_);
             if (lang == Language::VHDL) {
                 stream << StringTools::indent(level)
                        << instance << " : " << name() << "\n";
                 if (parameters_.size() > 0) {
                     stream << StringTools::indent(level + 1) << "generic map (\n";
  
                     std::string separator = "";
                     for (auto&& p : parameters_) {
                         stream << separator
                                << StringTools::indent(level + 2)
                                << p.name() << " => " << p.strValue();
                         separator = ",\n";
                     }
                     stream << ")\n";
                 }
                 std::string separator = "";
                 stream << StringTools::indent(level + 1) << "port map (\n";
                 for (auto&& p : ports_) {
                     stream << separator << StringTools::indent(level + 2)
                            << p.name() << " => ";
                     if (p.name() == "clk" || p.name() == "rstx" ||
                         p.name() == "glock_in") {
                         stream << p.name();
                     } else {
                         stream << instance << "_" <<  p.name();
                     }
                     separator = ",\n";
                 }
                 stream << ");\n";
             } else if (lang == Language::Verilog) {
                 stream << StringTools::indent(level) << name() << " ";
                 if (parameters_.size() > 0) {
                     stream << "#(";
                     std::string separator = "";
                     for (auto&& p : parameters_) {
                         stream << separator;
                         stream << "." << p.name() << "(" << p.strValue() << ")";
                         separator = ", ";
                     }
                     stream << ") ";
                 }
                 std::string separator = "";
                 stream << instance << " (\n";
                 for (auto&& p : ports_) {
                     stream << separator;
                     stream << StringTools::indent(level + 2) << "." << p.name()
                            << "(";
                     if (p.name() == "clk" || p.name() == "rstx" ||
                         p.name() == "glock_in") {
                         stream << p.name() << ")";
                     } else {
                         stream << instance << "_" << name() << ")";
                     }
                     separator = ",\n";
                 }
                 stream << ");\n";
             } else {
                 throw std::runtime_error(__PRETTY_FUNCTION__);
             }
         }

References id_, StringTools::indent(), HDLGenerator::Generatable::name(), parameters_, ports_, prefix_, HDLGenerator::Verilog, and HDLGenerator::VHDL.

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◆ isConstant()

virtual bool HDLGenerator::Module::isConstant ( const std::string & name )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1286 of file HDLGenerator.hh.

                                                              {
             for (auto&& r : constants_) {
                 if (r.name() == name) {
                     return true;
                 }
             }
             for (auto&& r : binaryConstants_) {
                 if (r.name() == name) {
                     return true;
                 }
             }
             return false;
         }

References binaryConstants_, constants_, and HDLGenerator::Generatable::name().

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◆ isRegister()

virtual bool HDLGenerator::Module::isRegister ( const std::string & name )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1277 of file HDLGenerator.hh.

                                                              {
             for (auto&& r : registers_) {
                 if (r.name() == name) {
                     return true;
                 }
             }
             return false;
         }

References HDLGenerator::Generatable::name(), and registers_.

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◆ isVariable()

virtual bool HDLGenerator::Module::isVariable ( const std::string & name )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1300 of file HDLGenerator.hh.

                                                              {
             for (auto&& v : variables_) {
                 if (v->name() == name) {
                     return true;
                 }
             }
             return false;
         }

References HDLGenerator::Generatable::name(), and variables_.

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◆ operator<<() [1/12]

Module& HDLGenerator::Module::operator<< ( Behaviour && rhs )

inline

Definition at line 1211 of file HDLGenerator.hh.

                                             {
             behaviours_.emplace_back(new Behaviour(rhs));
             return *this;
         }

References behaviours_.

◆ operator<<() [2/12]

Module& HDLGenerator::Module::operator<< ( Behaviour & rhs )

inline

Definition at line 1206 of file HDLGenerator.hh.

                                            {
             behaviours_.emplace_back(new Behaviour(rhs));
             return *this;
         }

References behaviours_.

◆ operator<<() [3/12]

Module& HDLGenerator::Module::operator<< ( BinaryConstant && constant )

inline

Definition at line 1231 of file HDLGenerator.hh.

                                                       {
             binaryConstants_.emplace_back(constant);
             return *this;
         }

References binaryConstants_.

◆ operator<<() [4/12]

Module& HDLGenerator::Module::operator<< ( IntegerConstant && constant )

inline

Definition at line 1226 of file HDLGenerator.hh.

                                                        {
             constants_.emplace_back(constant);
             return *this;
         }

References constants_.

◆ operator<<() [5/12]

Module& HDLGenerator::Module::operator<< ( Module && rhs )

inline

Definition at line 1256 of file HDLGenerator.hh.

                                          {
             modules_.emplace_back(rhs);
             return *this;
         }

References modules_.

◆ operator<<() [6/12]

Module& HDLGenerator::Module::operator<< ( Module & rhs )

inline

Definition at line 1261 of file HDLGenerator.hh.

                                         {
             modules_.emplace_back(rhs);
             return *this;
         }

References modules_.

◆ operator<<() [7/12]

Module& HDLGenerator::Module::operator<< ( Option && opt )

inline

Definition at line 1251 of file HDLGenerator.hh.

                                          {
             options_.emplace(opt.name());
             return *this;
         }

References options_.

◆ operator<<() [8/12]

Module& HDLGenerator::Module::operator<< ( Parameter && param )

inline

Definition at line 1221 of file HDLGenerator.hh.

                                               {
             parameters_.emplace_back(param);
             return *this;
         }

References parameters_.

◆ operator<<() [9/12]

Module& HDLGenerator::Module::operator<< ( Port && port )

inline

Definition at line 1216 of file HDLGenerator.hh.

                                         {
             ports_.push_back(port);
             return *this;
         }

References ports_.

◆ operator<<() [10/12]

Module& HDLGenerator::Module::operator<< ( Register && reg )

inline

Definition at line 1241 of file HDLGenerator.hh.

                                            {
             registers_.emplace_back(reg);
             return *this;
         }

References registers_.

◆ operator<<() [11/12]

Module& HDLGenerator::Module::operator<< ( Register & reg )

inline

Definition at line 1246 of file HDLGenerator.hh.

                                           {
             registers_.emplace_back(reg);
             return *this;
         }

References registers_.

◆ operator<<() [12/12]

Module& HDLGenerator::Module::operator<< ( Wire && wire )

inline

Definition at line 1236 of file HDLGenerator.hh.

                                         {
             wires_.emplace_back(new Wire(wire));
             return *this;
         }

References wires_.

◆ reads()

void HDLGenerator::Module::reads ( const std::string & var )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1374 of file HDLGenerator.hh.

1374 { (void)var; }

◆ registerVariable()

void HDLGenerator::Module::registerVariable ( const std::shared_ptr< Variable > var )

inline

Definition at line 1309 of file HDLGenerator.hh.

                                                                  {
             for (auto&& v : variables_) {
                 if (v->name() == var->name()) {
                     throw std::runtime_error("tried to register variable " +
                                              var->name() + " multiple times");
                 }
             }
             variables_.push_back(var);
         }

References variables_.

◆ set_header()

void HDLGenerator::Module::set_header ( )

inline

Definition at line 1187 of file HDLGenerator.hh.

                           {
             auto now = std::chrono::system_clock::now();
             auto now_c = std::chrono::system_clock::to_time_t(now);
             char buffer[31];
             std::stringstream ss;
             std::strftime(buffer, 30, "%c", std::localtime(&now_c));
             ss << buffer; // std::put_time(std::localtime(&now_c), "%c");
             headerComment_.emplace_back(
                 "Module generated by TTA Codesign Environment");
             headerComment_.emplace_back("");
             headerComment_.emplace_back(
                 std::string("Generated on ") + ss.str());
             headerComment_.emplace_back("");
         }

References headerComment_.

Referenced by Module().

◆ set_prefix()

void HDLGenerator::Module::set_prefix ( std::string prefix )

inline

Definition at line 1202 of file HDLGenerator.hh.

                                           {
             prefix_ = prefix;
         }

References prefix_.

Referenced by FUGen::createOperationResources().

◆ width()

Width HDLGenerator::Module::width ( const std::string & name )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1319 of file HDLGenerator.hh.

                                                  {
             for (auto&& v : parameters_) {
                 if (v.name() == name) {
                     return v.width();
                 }
             }
             for (auto&& v : constants_) {
                 if (v.name() == name) {
                     return v.width();
                 }
             }
             for (auto&& v : registers_) {
                 if (v.name() == name) {
                     return v.width();
                 }
             }
             for (auto&& v : wires_) {
                 if (v->name() == name) {
                     return v->width();
                 }
             }
             for (auto&& v : variables_) {
                 if (v->name() == name) {
                     return v->width();
                 }
             }
             for (auto&& v : ports_) {
                 if (v.name() == name) {
                     return v.width();
                 }
             }
             // not finding a thing is an error.
             throw std::runtime_error("Couldn't find width for " + name);
         }

References constants_, HDLGenerator::Generatable::name(), parameters_, ports_, registers_, variables_, and wires_.

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◆ wireType()

WireType HDLGenerator::Module::wireType ( const std::string & name )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1354 of file HDLGenerator.hh.

                                                        {
             for (auto&& v : ports_) {
                 if (v.name() == name) {
                     return v.wireType();
                 }
             }
             for (auto&& v : wires_) {
                 if (v->name() == name) {
                     return v->wireType();
                 }
             }
             for (auto&& v : variables_) {
                 if (v->name() == name) {
                     return v->wireType();
                 }
             }
             // not finding a thing is an error.
             throw std::runtime_error("Couldn't find wire type for " + name);
         }

References HDLGenerator::Generatable::name(), ports_, variables_, and wires_.

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◆ writes()

void HDLGenerator::Module::writes ( const std::string & var )

inlinefinalvirtual

Reimplemented from HDLGenerator::Generatable.

Definition at line 1376 of file HDLGenerator.hh.

1376 { (void)var; }

Member Data Documentation

◆ behaviours_

std::vector<std::shared_ptr<Behaviour> > HDLGenerator::Module::behaviours_

private

Definition at line 1690 of file HDLGenerator.hh.

Referenced by build(), implement(), and operator<<().

◆ binaryConstants_

std::vector<BinaryConstant> HDLGenerator::Module::binaryConstants_

private

Definition at line 1686 of file HDLGenerator.hh.

Referenced by implement(), isConstant(), and operator<<().

◆ constants_

std::vector<IntegerConstant> HDLGenerator::Module::constants_

private

Definition at line 1685 of file HDLGenerator.hh.

Referenced by implement(), isConstant(), operator<<(), and width().

◆ headerComment_

std::vector<std::string> HDLGenerator::Module::headerComment_

private

Definition at line 1682 of file HDLGenerator.hh.

Referenced by appendToHeader(), implement(), and set_header().

◆ id_

int HDLGenerator::Module::id_ = 0

private

Definition at line 1679 of file HDLGenerator.hh.

Referenced by instantiate(), and Module().

◆ modules_

std::vector<Module> HDLGenerator::Module::modules_

private

Definition at line 1691 of file HDLGenerator.hh.

Referenced by implement(), and operator<<().

◆ options_

std::unordered_set<std::string> HDLGenerator::Module::options_

private

Definition at line 1681 of file HDLGenerator.hh.

Referenced by hasOption(), and operator<<().

◆ parameters_

std::vector<Parameter> HDLGenerator::Module::parameters_

private

Definition at line 1683 of file HDLGenerator.hh.

Referenced by declare(), implement(), instantiate(), Module(), operator<<(), and width().

◆ ports_

std::vector<Port> HDLGenerator::Module::ports_

private

Definition at line 1684 of file HDLGenerator.hh.

Referenced by declare(), implement(), instantiate(), operator<<(), width(), and wireType().

◆ prefix_

std::string HDLGenerator::Module::prefix_

private

Definition at line 1680 of file HDLGenerator.hh.

Referenced by instantiate(), and set_prefix().

◆ registers_

std::vector<Register> HDLGenerator::Module::registers_

private

Definition at line 1688 of file HDLGenerator.hh.

Referenced by clear(), getRegister(), implement(), isRegister(), operator<<(), and width().

◆ variables_

std::vector<std::shared_ptr<Variable> > HDLGenerator::Module::variables_

private

Definition at line 1689 of file HDLGenerator.hh.

Referenced by clear(), implement(), isVariable(), registerVariable(), width(), and wireType().

◆ wires_

std::vector<std::shared_ptr<Wire> > HDLGenerator::Module::wires_

private

Definition at line 1687 of file HDLGenerator.hh.

Referenced by implement(), operator<<(), width(), and wireType().

The documentation for this class was generated from the following file:

HDLGenerator.hh

Public Member Functions

Private Member Functions

Private Attributes

Detailed Description

Constructor & Destructor Documentation

◆ Module() [1/2]

◆ Module() [2/2]

Member Function Documentation

◆ appendToHeader()

◆ build()

◆ clear()

◆ declare()

◆ getRegister()

◆ hasOption()

◆ implement()

◆ instantiate()

◆ isConstant()

◆ isRegister()

◆ isVariable()

◆ operator<<() [1/12]

◆ operator<<() [2/12]

◆ operator<<() [3/12]

◆ operator<<() [4/12]

◆ operator<<() [5/12]

◆ operator<<() [6/12]

◆ operator<<() [7/12]

◆ operator<<() [8/12]

◆ operator<<() [9/12]

◆ operator<<() [10/12]

◆ operator<<() [11/12]

◆ operator<<() [12/12]

◆ reads()

◆ registerVariable()

◆ set_header()

◆ set_prefix()

◆ width()

◆ wireType()

◆ writes()

Member Data Documentation

◆ behaviours_

◆ binaryConstants_

◆ constants_

◆ headerComment_

◆ id_

◆ modules_

◆ options_

◆ parameters_

◆ ports_

◆ prefix_

◆ registers_

◆ variables_

◆ wires_