HDLGenerator

Basic idea of HDLGenerator is to construct objects (modules, ports,
behavioral code constructs, etc), assign them to the object wich they
logically belong to, and finally call implement for the module.
Calling implement builds the code, does some limited validity checks,
and spits either Verilog or VHDL.

Only a limited subset of code constructs are present as not all were
relevant for efficient hdl.

Some options can be used to guide the generation:
"asynchronous reset" - Self-explanatory.
"synchronous reset" - Self-explanatory.
"reset everything" - Without this only registers with
                     ResetOption::Mandatory will be assigned a value
                     in reset.

What can be assigned to:
  Module << Register / Wire / InPort / OutPort / Parameter / Option
  Module << (std::string comment) / BinaryConstant / IntegerConstant
  Module << Behaviour / Module
  Behaviour << Assign / Asynchronous / Synchronous
  Asynchronous / Synchronous << SequentialStatement / Variable
  If <<  Else / SequentialStatement
  Switch << Case / DefaultCase
  Case / DefaultCase << HDLOperation / Assign / If

Case clauses:
  Case / DefaultCase << BinaryLiteral / (int) / (std::string)