33#ifndef TTA_ALTERA_HIBI_DP_RAM_GENERATOR_HH
34#define TTA_ALTERA_HIBI_DP_RAM_GENERATOR_HH
59 virtual std::vector<TCEString>
65 const std::string fuPort,
66 std::vector<TCEString>& reasons)
const;
virtual TCEString moduleName() const
virtual ~AlteraHibiDpRamGenerator()
virtual TCEString instanceName(int coreId, int memIndex) const
virtual std::vector< TCEString > generateComponentFile(TCEString outputPath)
virtual bool generatesComponentHdlFile() const
virtual void connectPorts(ProGe::NetlistBlock &netlistBlock, const ProGe::NetlistPort &memPort, const ProGe::NetlistPort &corePort, bool inverted, int coreId)
virtual bool checkFuPort(const std::string fuPort, std::vector< TCEString > &reasons) const
static const TCEString COMPONENT_FILE
std::ostream & warningStream()
std::ostream & errorStream()