OpenASIP 2.2
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BFScheduleExact.cc
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1/*
2 Copyright (c) 2002-2014 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24
25/**
26 * @file BFScheduleExact.cc
27 *
28 * Declaration of BFScheduleExact class
29 *
30 * Tries to schedule a move to an exact cycle (no order).
31 *
32 * @author Heikki Kultala 2014-2020(heikki.kultala-no.spam-tuni.fi)
33 * @note rating: red
34 */
35
36#include "BFScheduleExact.hh"
37#include "BFRegCopyBefore.hh"
38#include "BFRegCopyAfter.hh"
40#include "MoveNode.hh"
42#include "Move.hh"
43#include "Machine.hh"
44#include "ControlUnit.hh"
45#include "TerminalImmediate.hh"
46#include "BF2Scheduler.hh"
47#include "BFScheduleBU.hh"
48#include "BFEarlyGuardBypass.hh"
49#include "MoveGuard.hh"
50#include "Guard.hh"
51
52bool
54
55#ifdef DEBUG_BUBBLEFISH_SCHEDULER
56 std::cerr << "\t\tScheduling to exact cycle: " << mn_.toString()
57 << " to cycle: " << c_ << std::endl;
58#endif
59 BFRegCopy* regCopyBefore = NULL;
60 //BFRegCopy* regCopyAfter = NULL;
61 BFRegCopy* regCopy = NULL;
62
63 if (!mn_.move().isUnconditional() &&
64 mn_.move().guard().guard().parentBus() == nullptr) {
66 std::cerr << "Early guard bypass failed!" << std::endl;
67 return false;
68 }
69 }
71 if (mn_.isSourceOperation()) {
72 // assumes the result read is wanted to the exact cycle.
73 // reg cpy after both splits the move and schedules the copy.
74 // TODO: should it be scheudled TD instead of BU then?
75 regCopy = new BFRegCopyAfter(sched_,mn_, INT_MAX);
76 } else {
77 // this only splits the move. scheduled later.
78 regCopyBefore = regCopy = new BFRegCopyBefore(sched_,mn_, INT_MAX);
79 }
80
81 if (!runPreChild(regCopy)) {
82 return false;
83 }
84 }
85 int ddglc = ddg().latestCycle(mn_, ii(), false, false);
86 int ddgec = ddg().earliestCycle(mn_, ii(), false, false);
87#ifdef DEBUG_BUBBLEFISH_SCHEDULER
88 std::cerr << "\t\t\tddg lc: " << ddglc << std::endl;
89 std::cerr << "\t\t\tddg ec: " << ddgec << std::endl;
90#endif
91 if (ddglc >= c_ && ddgec <= c_ && canAssign(c_, mn_, nullptr, srcFU_)) {
92 createdCopy_ = assign(c_, mn_, nullptr, srcFU_);
93 if (regCopyBefore != NULL) {
94 MoveNode* regCopy = regCopyBefore->getRegCopy();
95 BFScheduleBU* regCopySched =
96 new BFScheduleBU(sched_, *regCopy, c_-1, false, false, false);
97 if (!runPostChild(regCopySched)) {
98 undo();
99 return false;
100 }
101 }
102 return true;
103 } else {
105 return false;
106 }
107}
108
109void
unsigned int ii() const
BF2Scheduler & sched_
virtual bool canAssign(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGWN=false)
DataDependenceGraph & ddg()
virtual void unassign(MoveNode &mn, bool disposePrologCopy=true)
bool canBeScheduled(const MoveNode &mn)
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
MoveNode * getRegCopy()
Definition BFRegCopy.hh:52
virtual bool operator()()
virtual void undoOnlyMe()
TTAProgram::Move * jumpLimitMove_
const TTAMachine::FunctionUnit * srcFU_
int latestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegAntideps=false, bool ignoreUnscheduledSuccessors=true, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false) const
int earliestCycle(const MoveNode &moveNode, unsigned int ii=UINT_MAX, bool ignoreRegWaRs=false, bool ignoreRegWaWs=false, bool ignoreGuards=false, bool ignoreFUDeps=false, bool ignoreSameOperationEdges=false, bool assumeBypassing=false) const
std::string toString() const
Definition MoveNode.cc:576
TTAProgram::Move & move()
bool isSourceOperation() const
Definition MoveNode.cc:168
bool runPostChild(Reversible *preChild)
virtual void undo()
Definition Reversible.cc:69
void undoAndRemovePreChildren()
Definition Reversible.cc:80
bool runPreChild(Reversible *preChild)
virtual Bus * parentBus() const
const TTAMachine::Guard & guard() const
Definition MoveGuard.cc:86
void setSource(Terminal *src)
Definition Move.cc:312
MoveGuard & guard() const
Definition Move.cc:345
bool isUnconditional() const
Definition Move.cc:154