OpenASIP 2.2
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BFScheduleTD.cc
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1/*
2 Copyright (c) 2002-2014 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24
25/**
26 * @file BFScheduleTD.cc
27 *
28 * Definition of BFScheduleTD class
29 *
30 * Tries to schedule a move in top-down order.
31 *
32 * @author Heikki Kultala 2014-2020(heikki.kultala-no.spam-tuni.fi)
33 * @note rating: red
34 */
35
36#include "BFScheduleTD.hh"
37#include "BFRegCopyAfter.hh"
38#include "BFRegCopyBefore.hh"
40#include "MoveNode.hh"
42
43#include "BFLateBypasses.hh"
44#include "BF2Scheduler.hh"
45
46#include "UniversalMachine.hh"
47
48#include "Move.hh"
49#include "Bus.hh"
50
51#include <climits>
52
53//#define DEBUG_BUBBLEFISH_SCHEDULER
54
55bool
57#ifdef DEBUG_BUBBLEFISH_SCHEDULER
58 std::cerr << "\tPerforming BFSchduleTD for: " << mn_.toString() <<
59 " ec limit: " << ec_ << std::endl;
60#endif
63 mn_.move().setBus(UniversalMachine::instance().universalBus());
64 }
65
68 if (runPreChild(lbp)) {
69 if (lbp->removedSource()) {
70 return true;
71 }
72 }
73 }
74
75
76 BFRegCopy* regCopyBefore = NULL;
77 BFRegCopy* regCopyAfter = NULL;
78 if (!canBeScheduled(mn_)) {
79 if (/*isRegCopyAfter_ || */ mn_.isSourceOperation()) {
80 regCopyAfter = new BFRegCopyAfter(sched_,mn_, INT_MAX);
81 } else {
82 regCopyBefore = new BFRegCopyBefore(sched_,mn_, INT_MAX);
83 if (!runPreChild(regCopyBefore)) {
84 return false;
85 }
86 }
87 }
88
89 int ddglc = std::min(sched_.maximumAllowedCycle(),
90 ddg().latestCycle(mn_, ii(), false, false));
91 int ddgec = std::max(ec_,
92 ddg().earliestCycle(mn_, ii(), false, false));
93 int rmec = rmEC(ddgec, mn_);
94#ifdef DEBUG_BUBBLEFISH_SCHEDULER
95 std::cerr << "\t\tDDG lc: " << ddglc << std::endl;
96 std::cerr << "\t\tDDG ec: " << ddgec << std::endl;
97 std::cerr << "\t\tRM ec: " << rmec << std::endl;
98#endif
99 if (rmec != -1 && ddglc >= rmec) {
100 createdCopy_ = assign(rmec, mn_);
101 if (regCopyAfter != NULL) {
102 if (!runPostChild(regCopyAfter)) {
104 return false;
105 }
106 }
107#ifdef DEBUG_BUBBLEFISH_SCHEDULER
108 std::cerr << "\t\tTD Assigned ok:" << mn_.toString()
109 << " bus: " << mn_.move().bus().name() << std::endl;
110#endif
111 return true;
112 } else {
114 return false;
115 }
116}
117
118void
120#ifdef DEBUG_BUBBLEFISH_SCHEDULER
121 std::cerr << "unassign td: " << mn_.toString() << std::endl;
122#endif
123 if (mn_.isScheduled()) {
125 }
127 mn_.move().setBus(UniversalMachine::instance().universalBus());
128 }
129}
#define assert(condition)
int maximumAllowedCycle() const
unsigned int ii() const
BF2Scheduler & sched_
DataDependenceGraph & ddg()
virtual void unassign(MoveNode &mn, bool disposePrologCopy=true)
bool canBeScheduled(const MoveNode &mn)
virtual int rmEC(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1)
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
bool allowLateBypass_
virtual void undoOnlyMe()
virtual bool operator()()
std::string toString() const
Definition MoveNode.cc:576
TTAProgram::Move & move()
bool isSourceOperation() const
Definition MoveNode.cc:168
bool isScheduled() const
Definition MoveNode.cc:409
bool isDestinationVariable() const
Definition MoveNode.cc:264
bool runPostChild(Reversible *preChild)
void undoAndRemovePreChildren()
Definition Reversible.cc:80
bool runPreChild(Reversible *preChild)
virtual TCEString name() const
void setBus(const TTAMachine::Bus &bus)
Definition Move.cc:383
const TTAMachine::Bus & bus() const
Definition Move.cc:373
static UniversalMachine & instance()
TTAMachine::Bus & universalBus() const