OpenASIP 2.2
Loading...
Searching...
No Matches
BFUnscheduleMove.cc
Go to the documentation of this file.
1/*
2 Copyright (c) 2002-2014 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24
25/**
26 * @file BFUnscheduleMove.cc
27 *
28 * Definition of BFUnscheduleMove class
29 *
30 * Unschedules a move.
31 *
32 * @author Heikki Kultala 2014-2020(heikki.kultala-no.spam-tuni.fi)
33 * @note rating: red
34 */
35
36#include "BFUnscheduleMove.hh"
37#include "Move.hh"
39#include "Bus.hh"
40#include "POMDisassembler.hh"
42#include "Instruction.hh"
43#include "MoveNodeDuplicator.hh"
44#include "Terminal.hh"
45#include "BF2Scheduler.hh"
46
49 oldBus_ = &mn_.move().bus();
50
51 if (mn_.isSourceOperation()) {
53 }
54
57 }
58
63 }
64
65 MoveNode* prologMN = ii() ? duplicator().getMoveNode(mn_) : NULL;
66 if (prologMN != NULL) {
67 prologBus_ = &prologMN->move().bus();
68
69 if (prologMN->move().source().isImmediateRegister()) {
71 }
72
73#ifdef DEBUG_BUBBLEFISH_SCHEDULER
74 std::cerr << "\t\t\t\tProlog move: " << prologMN->toString() << std::endl;
75 std::cerr << "\t\t\t\tBFUnscheduleMove Saving prolog bus: " << prologBus_->name() << " cycle: " << oldCycle_ << std::endl;
76#endif
77 }
78#ifdef DEBUG_BUBBLEFISH_SCHEDULER
79 for (int i = 0; i < recurseCounter_*2; i++)
80 std::cerr << "\t";
81
82 std::cerr << "\t\tUnscheduling original: " << mn_.toString() << " bus: " << oldBus_->name() << std::endl;
83#endif
84 unassign(mn_, false);
85#ifdef DEBUG_BUBBLEFISH_SCHEDULER
88 for (int i = 0; i < recurseCounter_*2; i++)
89 std::cerr << "\t";
90
91 std::cerr << "\t\tCannot assign to old cycle: " << mn_.toString()
92 << " old cycle: " << oldCycle_ << std::endl;
93 ddg().writeToDotFile("cannot_assign_old_cycle.dot");
94 if (mn_.isSourceOperation()) {
95 std::cerr << "\t\twhole src PO: " << mn_.sourceOperation().toString()
96 << std::endl;
97 }
99 std::cerr << "\t\twhole dst PO: " << mn_.destinationOperation().toString()
100 << std::endl;
101 }
102 assert(false);
103 }
104#endif
105}
106
108#ifdef DEBUG_BUBBLEFISH_SCHEDULER
109 for (int i = 0; i < recurseCounter_*2; i++)
110 std::cerr << "\t";
111
112 std::cerr << "\t\treturning original: " << mn_.toString() << " current bus: "
113 << mn_.move().bus().name() << " old bus: " << oldBus_->name()
114 << " cycle: " << oldCycle_ << std::endl;
115#endif
116
117#ifdef DEBUG_BUBBLEFISH_SCHEDULER
120 immRegIndex_, true)) {
121 std::cerr << "Cannot return to old cycle: " << mn_.toString() << " cycle: " << oldCycle_ << std::endl;
123 std::cerr << "dstPO: " << mn_.destinationOperation().toString() << std::endl;
124 }
125 if (mn_.isSourceOperation()) {
126 std::cerr << "srcPO: " << mn_.sourceOperation().toString() << std::endl;
127 }
128 std::cerr << "Original bus: " << oldBus_->name() << std::endl;
129 ddg().writeToDotFile("cannot_return_old_cycle.dot");
131 for (int i = 0; i < ins->moveCount(); i++) {
132 std::cerr << "\t" << POMDisassembler::disassemble(ins->move(i))
133 << " bus: " << ins->move(i).bus().name()
134 << std::endl;
135 }
136 std::cerr << "ins contains " << ins->immediateCount() << " immediates." << std::endl;
137 assert(false);
138 }
139#endif
142}
143
145#ifdef DEBUG_BUBBLEFISH_SCHEDULER
146 std::cerr << "BFUnscheudleMove undo" << std::endl;
147#endif
149}
150
151bool
154 return true;
155}
156
#define assert(condition)
unsigned int ii() const
virtual bool canAssign(int cycle, MoveNode &mn, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGWN=false)
SimpleResourceManager * prologRM() const
DataDependenceGraph & ddg()
virtual void unassign(MoveNode &mn, bool disposePrologCopy=true)
MoveNodeDuplicator & duplicator() const
SimpleResourceManager & rm() const
virtual bool assign(int cycle, MoveNode &, const TTAMachine::Bus *bus=nullptr, const TTAMachine::FunctionUnit *srcFU_=nullptr, const TTAMachine::FunctionUnit *dstFU=nullptr, const TTAMachine::Bus *prologBus=nullptr, int immWriteCycle=-1, int prologImmWriteCycle=-1, const TTAMachine::ImmediateUnit *immu=nullptr, int immRegIndex=-1, bool ignoreGuardWriteCycle=false)
const TTAMachine::Bus * prologBus_
static int recurseCounter_
const TTAMachine::ImmediateUnit * immu_
const TTAMachine::FunctionUnit * srcFU_
const TTAMachine::Bus * oldBus_
const TTAMachine::FunctionUnit * dstFU_
virtual void writeToDotFile(const TCEString &fileName) const
MoveNode * getMoveNode(MoveNode &mn)
int cycle() const
Definition MoveNode.cc:421
ProgramOperation & sourceOperation() const
Definition MoveNode.cc:453
bool isDestinationOperation() const
std::string toString() const
Definition MoveNode.cc:576
TTAProgram::Move & move()
bool isSourceOperation() const
Definition MoveNode.cc:168
ProgramOperation & destinationOperation(unsigned int index=0) const
static std::string disassemble(const TTAProgram::Move &move)
std::string toString() const
virtual TTAProgram::Instruction * instruction(int cycle) const override
virtual int immediateWriteCycle(const MoveNode &) const
virtual TCEString name() const
Move & move(int i) const
Terminal & source() const
Definition Move.cc:302
Terminal & destination() const
Definition Move.cc:323
const TTAMachine::Bus & bus() const
Definition Move.cc:373
virtual const TTAMachine::FunctionUnit & functionUnit() const
Definition Terminal.cc:251
virtual int index() const
Definition Terminal.cc:274
virtual bool isImmediateRegister() const
Definition Terminal.cc:97
virtual const TTAMachine::ImmediateUnit & immediateUnit() const
Definition Terminal.cc:240