57 const std::string& addressWidth,
const std::string& dataWidth,
58 const std::string& memInitFile,
bool isForSimulation)
65 Parameter(
"ACCESSTRACEFILENAME",
"string",
"\"access_trace\""));
106 std::string tempFile = (targetLang ==
VHDL)
107 ? std::string(
"synch_sram.vhdl")
108 : std::string(
"synch_sram.v");
109 std::string targetDir =
111 : ((targetLang ==
VHDL) ? std::string(
"vhdl")
112 : std::string(
"verilog"));
114 (progeDataDir / std::string(
"tb") / tempFile).
string(),
115 (targetBaseDir / targetDir / tempFile).
string());
#define assert(condition)
static std::string dataDirPath(const std::string &prog)
void instantiateTemplateFile(const std::string &templateFile, const std::string &dstFile)
NetlistPort * addPort(NetlistPort *port)
void addParameter(const Parameter ¶m)
void addPortGroup(NetlistPortGroup *portGroup)
void setParameter(const Parameter ¶m)
friend class NetlistPortGroup
Convenience class for input bit ports.
Convenience class for input ports.
Convenience class for output ports.
static NetlistPort * clockPort(Direction direction=IN)
virtual ~SinglePortSSRAMBlock()
const NetlistPortGroup & memoryPort() const
SinglePortSSRAMBlock()=delete
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const override
NetlistPortGroup * memoryPortGroup_
void setAccessTraceFile(const std::string filename)
@ BIT_VECTOR
Several bits.
@ BITMASKED_SRAM_PORT
Signal group type for one port SRAM having read and write capability and bitmask for writing.
@ ADDRESS
Signal holds address.
@ READ_WRITE_REQUEST
Signal to make either read or write request.
@ WRITEMODE
Signal to choose mode for READ_WRITE_REQUEST or similar.
HDL
HDLs supported by ProGe.