OpenASIP 2.2
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SinglePortSSRAMBlock.cc
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1/*
2 Copyright (c) 2002-2015 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * @file SinglePortSSRAMBlock.cc
26 *
27 * Implementation of SinglePortSSRAMBlock class.
28 *
29 * Created on: 8.9.2015
30 * @author Henry Linjamäki 2015 (henry.linjamaki-no.spam-tut.fi)
31 * @note rating: red
32 */
33
35
36#include "NetlistPort.hh"
37#include "NetlistPortGroup.hh"
38#include "Parameter.hh"
39#include "NetlistFactories.hh"
41
42#include "FileSystem.hh"
43
44namespace ProGe {
45
46/**
47 * Constructs Single port synchronous SRAM block.
48 *
49 * @param addressWidth The width of the address port.
50 * @param dataWidth The width of the data port.
51 * @param memInitFile Name of the memory initialization file loaded during
52 * RTL-simulation.
53 * @param isForSimulation Tells if the block is used in RTL simulation.
54 * Affects placement of the HDL source.
55 */
57 const std::string& addressWidth, const std::string& dataWidth,
58 const std::string& memInitFile, bool isForSimulation)
59 : BaseNetlistBlock("synch_sram", ""), isForSimulation_(isForSimulation) {
60 addParameter(Parameter("DATAW", "integer", dataWidth));
61 addParameter(Parameter("ADDRW", "integer", addressWidth));
62 addParameter(Parameter("INITFILENAME", "string", memInitFile));
63 addParameter(Parameter("access_trace", "boolean", "false"));
65 Parameter("ACCESSTRACEFILENAME", "string", "\"access_trace\""));
66
68
69 // todo add memory ports via PortFactory
73 new InPort("d", "DATAW", BIT_VECTOR, SignalType::WRITE_DATA),
74 new InPort("addr", "ADDRW", BIT_VECTOR, SignalType::ADDRESS),
75 new InBitPort(
76 "en_x",
78 new InBitPort(
80 new InPort(
81 "bit_wr_x", "DATAW", BIT_VECTOR, SignalType::WRITE_BITMASK),
82 new OutPort("q", "DATAW", BIT_VECTOR, SignalType::READ_DATA)));
83}
84
86
87/**
88 * Sets a file name where memory access trace is dumped for this memory.
89 */
90void
91SinglePortSSRAMBlock::setAccessTraceFile(const std::string filename) {
92 this->setParameter(Parameter("access_trace", "boolean", "true"));
93 this->setParameter(Parameter("ACCESSTRACEFILENAME", "string", filename));
94}
95
101
102void
103SinglePortSSRAMBlock::write(const Path& targetBaseDir, HDL targetLang) const {
104 Path progeDataDir(Environment::dataDirPath("ProGe"));
105
106 std::string tempFile = (targetLang == VHDL)
107 ? std::string("synch_sram.vhdl")
108 : std::string("synch_sram.v");
109 std::string targetDir =
110 (isForSimulation_) ? std::string("tb")
111 : ((targetLang == VHDL) ? std::string("vhdl")
112 : std::string("verilog"));
114 (progeDataDir / std::string("tb") / tempFile).string(),
115 (targetBaseDir / targetDir / tempFile).string());
116}
117
118} /* namespace ProGe */
#define assert(condition)
static std::string dataDirPath(const std::string &prog)
void instantiateTemplateFile(const std::string &templateFile, const std::string &dstFile)
NetlistPort * addPort(NetlistPort *port)
void addParameter(const Parameter &param)
void addPortGroup(NetlistPortGroup *portGroup)
void setParameter(const Parameter &param)
Convenience class for input bit ports.
Convenience class for input ports.
Convenience class for output ports.
static NetlistPort * clockPort(Direction direction=IN)
const NetlistPortGroup & memoryPort() const
virtual void write(const Path &targetBaseDir, HDL targetLang=VHDL) const override
void setAccessTraceFile(const std::string filename)
Definition FUGen.hh:54
@ BIT_VECTOR
Several bits.
Definition ProGeTypes.hh:48
@ BITMASKED_SRAM_PORT
Signal group type for one port SRAM having read and write capability and bitmask for writing.
@ ADDRESS
Signal holds address.
@ READ_WRITE_REQUEST
Signal to make either read or write request.
@ WRITEMODE
Signal to choose mode for READ_WRITE_REQUEST or similar.
HDL
HDLs supported by ProGe.
Definition ProGeTypes.hh:40
@ VHDL
VHDL.
Definition ProGeTypes.hh:41