FUTestbenchGenerator Class Reference

#include <FUTestbenchGenerator.hh>

Inheritance diagram for FUTestbenchGenerator:

Collaboration diagram for FUTestbenchGenerator:

Public Member Functions
	FUTestbenchGenerator (HDB::FUEntry *fu)
virtual	~FUTestbenchGenerator ()
virtual void	generateTestbench (std::ofstream &file)
Public Member Functions inherited from TestbenchGenerator
	TestbenchGenerator ()
virtual	~TestbenchGenerator ()

Private Member Functions
void	parseFuPorts ()
void	createMachineState ()
void	createTbInstantiation ()
void	createStimulus ()
void	createTbCode ()
void	writeInputPortStimulus (PortDataArray &inputs, const std::string &operation, const std::string &portName, uint32_t stimulus)
void	readValuesFromOutPorts (PortDataArray &outputs)
void	createStimulusArrays (PortDataArray &inputStimulus, std::vector< uint32_t > &loadStimulus, std::vector< std::string > &operations, PortDataArray &outputStimulus)
bool	isShiftOrRotOp (const std::string &operation) const
uint32_t	truncateStimulus (uint32_t operand, int nBits) const

Private Attributes
HDB::FUEntry *	fuEntry_
HDB::FUImplementation *	fuImpl_
HDB::FUArchitecture *	fuArch_
MachineState *	msm_
std::vector< std::string >	inputPorts_
std::vector< std::string >	outputPorts_
std::string	opcodePort_
TTAMachine::Machine *	machine_
MemorySystem *	memSystem_

Additional Inherited Members
Protected Types inherited from TestbenchGenerator
typedef std::map< std::string, std::vector< uint32_t > >	PortDataArray
Protected Member Functions inherited from TestbenchGenerator
virtual void	writeStimulusArray (std::ostringstream &stream, std::vector< uint32_t > &dataArray, std::string portName, int portWidth)
void	writeTbConstants (int totalCycles, int outputIgnoreCycles)
void	writeTestbench (std::ofstream &file, HDB::HWBlockImplementation *impl)
std::ostringstream &	declarationStream ()
std::ostringstream &	bindingStream ()
std::ostringstream &	signalStream ()
std::ostringstream &	instantiationStream ()
std::ostringstream &	inputArrayStream ()
std::ostringstream &	opcodeArrayStream ()
std::ostringstream &	loadArrayStream ()
std::ostringstream &	outputArrayStream ()
std::ostringstream &	tbCodeStream ()

Detailed Description

Definition at line 54 of file FUTestbenchGenerator.hh.

Constructor & Destructor Documentation

FUTestbenchGenerator()

FUTestbenchGenerator::FUTestbenchGenerator

(

HDB::FUEntry *

fu

)

Definition at line 67 of file FUTestbenchGenerator.cc.

                                                        : 
    fuEntry_(fu), fuImpl_(NULL), fuArch_(NULL), msm_(NULL), inputPorts_(),
    outputPorts_(), opcodePort_(), machine_(NULL), memSystem_(NULL) {
}

~FUTestbenchGenerator()

FUTestbenchGenerator::~FUTestbenchGenerator ( )

virtual

Definition at line 72 of file FUTestbenchGenerator.cc.

                                            {
 
    if (msm_) {
        delete(msm_);
    }
    if (machine_) {
        delete(machine_);
    }
    if (memSystem_) {
        delete(memSystem_);
    }
}

References machine_, memSystem_, and msm_.

Member Function Documentation

createMachineState()

void FUTestbenchGenerator::createMachineState ( )

private

Create a machine architecture object model with the tested FU in it

Definition at line 104 of file FUTestbenchGenerator.cc.

                                         {
 
    machine_ = new TTAMachine::Machine();
    machine_->addFunctionUnit(fuArch_->architecture());
 
    MachineStateBuilder msmBuilder;
    
    memSystem_ = new MemorySystem(*machine_);
 
    msm_ = msmBuilder.build(*machine_, *memSystem_);
}

References TTAMachine::Machine::addFunctionUnit(), HDB::FUArchitecture::architecture(), MachineStateBuilder::build(), fuArch_, machine_, memSystem_, and msm_.

Referenced by generateTestbench().

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createStimulus()

void FUTestbenchGenerator::createStimulus ( )

private

Creates input and output data tables

Creates input and output data tables and control signals for the testbench. Every operation is tested STIMULUS_PER_OP times and command execution is pipelined. Only fully pipelined FUs are supported.

Definition at line 268 of file FUTestbenchGenerator.cc.

                                     {
 
    FUState& simFU = msm_->fuState(fuArch_->architecture().name());
    assert(&simFU != &NullFUState::instance());
 
    // stimulus for each port in each clock cycle
    PortDataArray inputStimulus;
 
    // stimulus for load ports. Notice that all load ports get the same
    // signal!
    // TODO: Exploit this when supporting non-fully pipelined operations
    //       (if latency(op N) > latency(op N+1) there needs to be no-load
    //       cycles when switching operations)
    vector<uint32_t> loadStimulus;
 
    // operations started in each clock cycle (names)
    vector<string> startedOperations;
 
    // expected output for each port in each clock cycle
    PortDataArray outputs;
 
    // initialize a random number generator for the stimuli
    boost::uniform_int<> distribution(INT_MIN, INT_MAX);
    boost::mt19937 rng;
    rng.seed(time(NULL));
    boost::variate_generator<boost::mt19937&, boost::uniform_int<> >
        randomNumber(rng, distribution);
 
    const int cyclesToSimulate = STIMULUS_PER_OP;
    for (int opIndex = 0; opIndex < fuArch_->architecture().operationCount(); 
         ++opIndex) {
        const string operation = 
            fuArch_->architecture().operation(opIndex)->name();
 
        for (int i = 0; i < cyclesToSimulate; i++) {
            startedOperations.push_back(operation);
 
            // generate stimulus for each port
            for (std::size_t i = 0; i < inputPorts_.size(); ++i) {
                const string portName = inputPorts_.at(i);
                writeInputPortStimulus(
                    inputStimulus, 
                    operation, portName, (uint32_t)randomNumber());
            }
            
            // load signal stimulus
            uint32_t loadOnThisCycle = 1;
            loadStimulus.push_back(loadOnThisCycle);
 
            readValuesFromOutPorts(outputs);
            // advance the simulation clock
            simFU.endClock();
            simFU.advanceClock();
        }
    }
    // flush the pipeline
    int lastOpIndex = fuArch_->architecture().operationCount()-1;
    int pipelineClearCycles =
        fuArch_->architecture().operation(lastOpIndex)->latency();
    for (int i = 0; i < pipelineClearCycles; i++) {
        if (fuArch_->architecture().operationCount() > 1) {
            // insert dummy values for opcode port
            const string operation = 
                fuArch_->architecture().operation(lastOpIndex)->name();
            startedOperations.push_back(operation);
        }
        for (std::size_t j = 0; j < inputPorts_.size(); ++j) {
            const string portName = inputPorts_.at(j);
            // operation does not matter
            const string operation = 
                fuArch_->architecture().operation(lastOpIndex)->name();
            uint32_t inputStim = 0;
            writeInputPortStimulus(
                inputStimulus, operation, portName, inputStim);
        }
        // no load on these cycles
        uint32_t loadStim = 0;
        loadStimulus.push_back(loadStim);
        
        readValuesFromOutPorts(outputs);
        // advance the simulation clock
        simFU.endClock();
        simFU.advanceClock();
    }
    createStimulusArrays(
        inputStimulus, loadStimulus, startedOperations, outputs);
    
    int waitCycles = 
        fuArch_->architecture().operation(startedOperations.at(0))->latency();
    // TODO: change this when supporting different pipelines
    int opCount = fuArch_->architecture().operationCount();
    int latencyOfLastOp =
        fuArch_->architecture().operation(opCount-1)->latency();
    int totalCycles = 
        STIMULUS_PER_OP * opCount + latencyOfLastOp;
    writeTbConstants(totalCycles, waitCycles);
}

References FUState::advanceClock(), HDB::FUArchitecture::architecture(), assert, createStimulusArrays(), FUState::endClock(), fuArch_, MachineState::fuState(), inputPorts_, NullFUState::instance(), TTAMachine::HWOperation::latency(), msm_, TTAMachine::HWOperation::name(), TTAMachine::Component::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), readValuesFromOutPorts(), STIMULUS_PER_OP, writeInputPortStimulus(), and TestbenchGenerator::writeTbConstants().

Referenced by generateTestbench().

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createStimulusArrays()

void FUTestbenchGenerator::createStimulusArrays ( PortDataArray &  inputStimulus, std::vector< uint32_t > &  loadStimulus, std::vector< std::string > &  operations, PortDataArray &  outputStimulus  )

private

Writes input, output and control signal data to output streams

Parameters

inputStimulus	Input port data
loadStimulus	Load port data
operations	Triggered operations
outputStimulus	Output port data

Definition at line 499 of file FUTestbenchGenerator.cc.

                                                                     {
 
    // input array(s)
    for (PortDataArray::iterator i = inputStimulus.begin();
         i != inputStimulus.end(); i++) {
        HDB::FUPortImplementation* port = 
            &fuImpl_->portImplementationByArchitectureName((*i).first);
        const string hwPortName = port->name();
        const int hwPortWidth = 
            fuArch_->architecture().port((*i).first)->width();
        vector<uint32_t> data = i->second;
        writeStimulusArray(inputArrayStream(), data, hwPortName, hwPortWidth);
 
        const string loadPortName = port->loadPort();
        if (!loadPortName.empty()) {
            int loadPortWidth = 1;
            writeStimulusArray(loadArrayStream(), loadStimulus, loadPortName,
                               loadPortWidth);
        }
    }
    
    // opcode arrays
    // Special case so we can print the operation names to the testbench
    const int operationsInFU = fuArch_->architecture().operationCount(); 
    if (operationsInFU > 1) {
        const string hwPortName = fuImpl_->opcodePort();
        const int hwPortWidth = fuImpl_->maxOpcodeWidth();
        opcodeArrayStream()
            << INDENT INDENT
            << "type " << hwPortName << "_data_array is array "
            << "(natural range <>) of"  << std::endl << INDENT INDENT INDENT
            << "std_logic_vector(" << hwPortWidth - 1 << " downto 0);" 
            << std::endl << std::endl
            << INDENT INDENT
            << "constant "<< hwPortName << "_data : " << hwPortName 
            << "_data_array :=" << std::endl;
        
        for (std::size_t i = 0; i < operations.size(); ++i) {
            uint32_t input = fuImpl_->opcode(operations.at(i));
            std::string inputAsBinaryLiteral = 
                Conversion::toBinary(input, hwPortWidth);
            opcodeArrayStream() << INDENT INDENT;
            if (i == 0) {
                opcodeArrayStream() << "(";
            } else {
                opcodeArrayStream() << " ";
            }
            opcodeArrayStream() << "\"" << inputAsBinaryLiteral << "\"";
            if (i == operations.size() - 1) {
                opcodeArrayStream() << ");";
            } else {
                opcodeArrayStream() << ",";
            }
            opcodeArrayStream()
                << "\t -- @" << i << " = " << input << " (" 
                << operations.at(i) << ")" << std::endl;
        }
    }
    
    // output arrays
    for (PortDataArray::iterator i = outputStimulus.begin();
         i != outputStimulus.end(); ++i) {
        const std::string hwPortName = 
            fuImpl_->portImplementationByArchitectureName((*i).first).name();
        const int hwPortWidth = 
            fuArch_->architecture().port((*i).first)->width();
        vector<uint32_t> data = i->second;
        writeStimulusArray(outputArrayStream(), data, hwPortName, 
                           hwPortWidth);
    }
}

References HDB::FUArchitecture::architecture(), fuArch_, fuImpl_, INDENT, TestbenchGenerator::inputArrayStream(), TestbenchGenerator::loadArrayStream(), HDB::PortImplementation::loadPort(), HDB::FUImplementation::maxOpcodeWidth(), HDB::PortImplementation::name(), HDB::FUImplementation::opcode(), TestbenchGenerator::opcodeArrayStream(), HDB::FUImplementation::opcodePort(), TTAMachine::FunctionUnit::operationCount(), TestbenchGenerator::outputArrayStream(), TTAMachine::FunctionUnit::port(), HDB::FUImplementation::portImplementationByArchitectureName(), Conversion::toBinary(), TTAMachine::BaseFUPort::width(), and TestbenchGenerator::writeStimulusArray().

Referenced by createStimulus().

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createTbCode()

void FUTestbenchGenerator::createTbCode ( )

private

Writes the testbench main process code

Definition at line 371 of file FUTestbenchGenerator.cc.

                                   {
 
    for (std::size_t i = 0; i < inputPorts_.size(); ++i) {
        const std::string portName = inputPorts_.at(i);
        const std::string hwDataPortName = 
            fuImpl_->portImplementationByArchitectureName(portName).name();
        const std::string hwLoadPortName = 
            fuImpl_->
            portImplementationByArchitectureName(portName).loadPort();
        tbCodeStream()
            << INDENT INDENT 
            << hwDataPortName << " <= " << hwDataPortName << "_data("
            << "current_cycle);" << std::endl
            << INDENT INDENT << hwLoadPortName << " <= " 
            << hwLoadPortName << "_data(current_cycle);" << std::endl;        
    }
    
    if (fuArch_->architecture().operationCount() > 1) {
        tbCodeStream() 
            << INDENT INDENT 
            << fuImpl_->opcodePort() 
            << " <= " << fuImpl_->opcodePort() << "_data(current_cycle); ";
    }
 
    tbCodeStream()
        << std::endl << std::endl
        << INDENT INDENT 
        << "if current_cycle >= IGNORE_OUTPUT_COUNT then" << std::endl;
 
    for (std::size_t i = 0; i < outputPorts_.size(); ++i) {
        const std::string portName = outputPorts_.at(i);
        const std::string hwDataPortName = 
            fuImpl_->portImplementationByArchitectureName(portName).name();
        tbCodeStream() 
            << INDENT INDENT INDENT 
            << "assert " << hwDataPortName << " = " << hwDataPortName 
            << "_data(current_cycle)" << std::endl
            << INDENT INDENT INDENT INDENT 
            << "report lf & \"TCE Assert: Verification failed at cycle \" "
            << "& integer'image(current_cycle) & \" for output " << i << "\"" << std::endl
            << INDENT INDENT INDENT INDENT <<"& \" actual: \" "
            << "& to_hstring(" << hwDataPortName << ")" 
            << std::endl
            << INDENT INDENT INDENT INDENT << "& " 
            << "\" expected: \" & to_hstring(" << hwDataPortName
            << "_data(current_cycle))  severity error;" 
            << std::endl << std::endl;
    }
 
    tbCodeStream()
        << INDENT INDENT 
        << "end if;" << std::endl;
}

References HDB::FUArchitecture::architecture(), fuArch_, fuImpl_, INDENT, inputPorts_, HDB::PortImplementation::name(), HDB::FUImplementation::opcodePort(), TTAMachine::FunctionUnit::operationCount(), outputPorts_, HDB::FUImplementation::portImplementationByArchitectureName(), and TestbenchGenerator::tbCodeStream().

Referenced by generateTestbench().

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createTbInstantiation()

void FUTestbenchGenerator::createTbInstantiation ( )

private

Creates component declaration, connection signals and connects FU component to testbench

Definition at line 150 of file FUTestbenchGenerator.cc.

                                            {
 
    bindingStream() 
        << INDENT << "for tested_fu_0 : fu_under_test use entity work.";
    bindingStream() << fuImpl_->moduleName() << ";" << std::endl;
    
    declarationStream()
        << INDENT << "component fu_under_test" << std::endl
        << INDENT INDENT << "port(" << std::endl;
    
    instantiationStream()
        << INDENT << "tested_fu_0\t:\tfu_under_test " << std::endl
        << INDENT INDENT << "port map (" << std::endl;
 
    for (int i = 0; i < fuImpl_->architecturePortCount(); ++i) {
        HDB::FUPortImplementation& port = fuImpl_->architecturePort(i);
        // this might not always work..
        const int portWidth = fuArch_->architecture().port(i)->width();
        const bool isInput = 
            ContainerTools::containsValue(
                inputPorts_, port.architecturePort());
        declarationStream() 
            << INDENT INDENT << port.name() << "\t: ";
        signalStream()
            << INDENT << "signal " << port.name() << "\t: ";
        instantiationStream()
            << INDENT INDENT INDENT << port.name() << " => " << port.name();
 
        if (isInput)
            declarationStream() << "in";
        else
            declarationStream() << "out";
 
        declarationStream()
            << " std_logic_vector("
            << portWidth - 1 << " downto 0);" << std::endl;
 
        signalStream()
            << "std_logic_vector("
            << portWidth - 1 << " downto 0);" << std::endl;
 
        if (isInput) {
            declarationStream()
                << INDENT INDENT << port.loadPort() 
                << "\t: in  std_logic;" << std::endl;
 
            signalStream()
                << INDENT << "signal " << port.loadPort() 
                << "\t: std_logic_vector(1-1 downto 0);" << std::endl;
 
            instantiationStream()
                << "," << std::endl
                << INDENT INDENT INDENT << port.loadPort() << " => " 
                << port.loadPort() << "(0)";
        }
        if (i < fuImpl_->architecturePortCount() - 1) {
            instantiationStream() << "," << std::endl;
        } else {
            if (fuImpl_->opcodePort() != "") {
                declarationStream()
                    << INDENT INDENT << fuImpl_->opcodePort() << "\t: "
                    << "in" << " std_logic_vector("
                    << fuImpl_->maxOpcodeWidth() - 1 << " downto 0);"
                    << std::endl;
                instantiationStream()
                    << "," << std::endl
                    << INDENT INDENT INDENT 
                    << fuImpl_->opcodePort() 
                    << " => " << fuImpl_->opcodePort();
                signalStream()
                    << INDENT << "signal " << fuImpl_->opcodePort() << "\t: ";
                signalStream()
                    << "std_logic_vector("
                    << fuImpl_->maxOpcodeWidth() - 1 
                    << " downto 0);" << std::endl;
            }
        }
    }
    instantiationStream() 
        << "," << std::endl
        << INDENT INDENT INDENT
        << fuImpl_->clkPort() << " => " << fuImpl_->clkPort() 
        << "," << std::endl
        << INDENT INDENT INDENT
        << fuImpl_->rstPort() << " => " << fuImpl_->rstPort() 
        << "," << std::endl
        << INDENT INDENT INDENT
        << fuImpl_->glockPort() << " => " << fuImpl_->glockPort() 
        << ");";
 
    declarationStream()
        << INDENT INDENT << fuImpl_->glockPort() << "\t: in  std_logic;" 
        << std::endl
        << INDENT INDENT << fuImpl_->rstPort()   << "\t: in  std_logic;" 
        << std::endl
        << INDENT INDENT << fuImpl_->clkPort()   << "\t: in  std_logic);" 
        << std::endl
        << INDENT << "end component;" 
        << std::endl;
 
    signalStream()
        << INDENT << "signal " << fuImpl_->glockPort() << "\t: std_logic;" 
        << std::endl
        << INDENT << "signal " << fuImpl_->rstPort() << "\t: std_logic;" 
        << std::endl
        << INDENT << "signal " << fuImpl_->clkPort() << "\t: std_logic;"
        << std::endl;
}

References HDB::FUArchitecture::architecture(), HDB::FUPortImplementation::architecturePort(), HDB::FUImplementation::architecturePort(), HDB::FUImplementation::architecturePortCount(), TestbenchGenerator::bindingStream(), HDB::HWBlockImplementation::clkPort(), ContainerTools::containsValue(), TestbenchGenerator::declarationStream(), fuArch_, fuImpl_, HDB::HWBlockImplementation::glockPort(), INDENT, inputPorts_, TestbenchGenerator::instantiationStream(), HDB::PortImplementation::loadPort(), HDB::FUImplementation::maxOpcodeWidth(), HDB::HWBlockImplementation::moduleName(), HDB::PortImplementation::name(), HDB::FUImplementation::opcodePort(), TTAMachine::FunctionUnit::port(), HDB::HWBlockImplementation::rstPort(), TestbenchGenerator::signalStream(), and TTAMachine::BaseFUPort::width().

Referenced by generateTestbench().

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generateTestbench()

void FUTestbenchGenerator::generateTestbench ( std::ofstream &  file )

virtual

Implements TestbenchGenerator.

Definition at line 87 of file FUTestbenchGenerator.cc.

                                                         {
 
    fuImpl_ = &fuEntry_->implementation();
    fuArch_ = &fuEntry_->architecture();
    
    createMachineState();
    parseFuPorts();
    createTbInstantiation();
    createStimulus();
    createTbCode();
    writeTestbench(file, fuImpl_);
}

References HDB::FUEntry::architecture(), createMachineState(), createStimulus(), createTbCode(), createTbInstantiation(), fuArch_, fuEntry_, fuImpl_, HDB::FUEntry::implementation(), parseFuPorts(), and TestbenchGenerator::writeTestbench().

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isShiftOrRotOp()

bool FUTestbenchGenerator::isShiftOrRotOp ( const std::string &  operation ) const

private

Test if operation is shift or rotation operation

Parameters

operation

Name of the operation

Returns

Is operation shift or rotate

Definition at line 582 of file FUTestbenchGenerator.cc.

                                                                     {
 
    string opName = StringTools::stringToLower(operation);
    
    if (opName == "shl" || opName == "shr" || opName == "shru") {
        return true;
    } else if (opName == "rotl" || opName == "rotr") {
        return true;
    }
    return false;
}

References StringTools::stringToLower().

Referenced by writeInputPortStimulus().

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parseFuPorts()

void FUTestbenchGenerator::parseFuPorts ( )

private

Definition at line 118 of file FUTestbenchGenerator.cc.

                                   {
 
    // divide ports into input and output ports
    for (int i = 0; i < fuArch_->architecture().portCount(); i++) {
        const std::string portName = fuArch_->architecture().port(i)->name();
        PortState& simulatedPort = 
            msm_->portState(portName, fuArch_->architecture().name());
 
        if (fuArch_->architecture().port(i)->isOpcodeSetting())
            opcodePort_ = portName;
 
        if (dynamic_cast<OutputPortState*>(&simulatedPort)) {
            outputPorts_.push_back(portName);
        } else if (dynamic_cast<InputPortState*>(&simulatedPort)) {
            inputPorts_.push_back(portName);
        } else if (&simulatedPort == &NullPortState::instance()) {
            InvalidData e(__FILE__, __LINE__, "ImplementationTester",
                          "Port not found in state");
            throw e;
        } else {
            InvalidData e(__FILE__, __LINE__, "ImplementationTester",
                          "Port " + portName + " has unknown direction.");
            throw e;
        }
    }
}

References HDB::FUArchitecture::architecture(), fuArch_, inputPorts_, NullPortState::instance(), TTAMachine::BaseFUPort::isOpcodeSetting(), msm_, TTAMachine::Component::name(), TTAMachine::Port::name(), opcodePort_, outputPorts_, TTAMachine::FunctionUnit::port(), and MachineState::portState().

Referenced by generateTestbench().

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readValuesFromOutPorts()

void FUTestbenchGenerator::readValuesFromOutPorts ( PortDataArray &  outputs )

private

Reads data from output ports and saves the values to an array

Parameters

outputs

PortDataArray containing the output ports

Definition at line 476 of file FUTestbenchGenerator.cc.

                                                                   {
 
    for (std::size_t i = 0; i < outputPorts_.size(); ++i) {
        const string portName = outputPorts_.at(i);
 
        PortState* simulatedPort = NULL;
        simulatedPort = &msm_->portState(
            portName, fuArch_->architecture().name());
 
        outputs[portName].push_back(
            simulatedPort->value().intValue());
    }
}

References HDB::FUArchitecture::architecture(), fuArch_, SimValue::intValue(), msm_, TTAMachine::Component::name(), outputPorts_, MachineState::portState(), and RegisterState::value().

Referenced by createStimulus().

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truncateStimulus()

uint32_t FUTestbenchGenerator::truncateStimulus ( uint32_t  operand, int  nBits  ) const

private

Truncates shift operand to log2(32) bits

Parameters

operand

Operand to be truncated

Returns

Truncated operand

Definition at line 601 of file FUTestbenchGenerator.cc.

                                                                        {
    
    if (nBits < 0) {
        InvalidData exc(__FILE__, __LINE__, "ImplementationTester",
                        "Negative amount f wanted bits");
        throw exc;
    }
 
    unsigned int dataWidth = 32;
    uint32_t truncated =
        (operand << (dataWidth - nBits) >> (dataWidth - nBits));
    return truncated;
}

Referenced by writeInputPortStimulus().

writeInputPortStimulus()

void FUTestbenchGenerator::writeInputPortStimulus ( PortDataArray &  inputs, const std::string &  operation, const std::string &  portName, uint32_t  stimulus  )

private

Writes input data to the given port and saves the input value to an array

Parameters

inputs	PortDataArray containing input ports
operation	Name of the triggered operation
portName	Name of the port where data is written to
stimulus	Input data

Definition at line 434 of file FUTestbenchGenerator.cc.

                                                  {
 
    string operationString = "";
    PortState* simulatedPort = NULL;
    bool isOpcodePort = false;
    // fetch the virtual opcode setting port for the triggered operation
    if (portName == opcodePort_) {
        operationString = 
            StringTools::stringToLower(
                std::string(".") + operation);
        isOpcodePort = true;
    }
 
    simulatedPort = &msm_->portState(
        portName + operationString,
        fuArch_->architecture().name());
    
    const int inputWidth = simulatedPort->value().width();
    SimValue value(inputWidth);
 
    int wantedBits = inputWidth;
    if (isShiftOrRotOp(operation) && isOpcodePort
        && inputWidth > 5) {
        // log2(32) = 5 bits needed to express max shift
        wantedBits = 5;
    }
    stimulus = truncateStimulus(stimulus, wantedBits);
 
    inputs[portName].push_back(stimulus);
    value = stimulus;
    simulatedPort->setValue(value);
}

References HDB::FUArchitecture::architecture(), fuArch_, isShiftOrRotOp(), msm_, TTAMachine::Component::name(), opcodePort_, MachineState::portState(), RegisterState::setValue(), StringTools::stringToLower(), truncateStimulus(), RegisterState::value(), and SimValue::width().

Referenced by createStimulus().

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Member Data Documentation

fuArch_

HDB::FUArchitecture* FUTestbenchGenerator::fuArch_

private

Definition at line 94 of file FUTestbenchGenerator.hh.

Referenced by createMachineState(), createStimulus(), createStimulusArrays(), createTbCode(), createTbInstantiation(), generateTestbench(), parseFuPorts(), readValuesFromOutPorts(), and writeInputPortStimulus().

fuEntry_

HDB::FUEntry* FUTestbenchGenerator::fuEntry_

private

Definition at line 92 of file FUTestbenchGenerator.hh.

Referenced by generateTestbench().

fuImpl_

HDB::FUImplementation* FUTestbenchGenerator::fuImpl_

private

Definition at line 93 of file FUTestbenchGenerator.hh.

Referenced by createStimulusArrays(), createTbCode(), createTbInstantiation(), and generateTestbench().

inputPorts_

std::vector<std::string> FUTestbenchGenerator::inputPorts_

private

Definition at line 97 of file FUTestbenchGenerator.hh.

Referenced by createStimulus(), createTbCode(), createTbInstantiation(), and parseFuPorts().

machine_

TTAMachine::Machine* FUTestbenchGenerator::machine_

private

Definition at line 101 of file FUTestbenchGenerator.hh.

Referenced by createMachineState(), and ~FUTestbenchGenerator().

memSystem_

MemorySystem* FUTestbenchGenerator::memSystem_

private

Definition at line 102 of file FUTestbenchGenerator.hh.

Referenced by createMachineState(), and ~FUTestbenchGenerator().

msm_

MachineState* FUTestbenchGenerator::msm_

private

Definition at line 96 of file FUTestbenchGenerator.hh.

Referenced by createMachineState(), createStimulus(), parseFuPorts(), readValuesFromOutPorts(), writeInputPortStimulus(), and ~FUTestbenchGenerator().

opcodePort_

std::string FUTestbenchGenerator::opcodePort_

private

Definition at line 99 of file FUTestbenchGenerator.hh.

Referenced by parseFuPorts(), and writeInputPortStimulus().

outputPorts_

std::vector<std::string> FUTestbenchGenerator::outputPorts_

private

Definition at line 98 of file FUTestbenchGenerator.hh.

Referenced by createTbCode(), parseFuPorts(), and readValuesFromOutPorts().

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The documentation for this class was generated from the following files:

• FUTestbenchGenerator.hh
• FUTestbenchGenerator.cc