OpenASIP 2.2
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MachineStateBuilder.cc
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1/*
2 Copyright (c) 2002-2010 Tampere University.
3
4 This file is part of TTA-Based Codesign Environment (TCE).
5
6 Permission is hereby granted, free of charge, to any person obtaining a
7 copy of this software and associated documentation files (the "Software"),
8 to deal in the Software without restriction, including without limitation
9 the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 and/or sell copies of the Software, and to permit persons to whom the
11 Software is furnished to do so, subject to the following conditions:
12
13 The above copyright notice and this permission notice shall be included in
14 all copies or substantial portions of the Software.
15
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 DEALINGS IN THE SOFTWARE.
23 */
24/**
25 * @file MachineStateBuilder.cc
26 *
27 * Definition of MachineStateBuilder class.
28 *
29 * @author Jussi Nykänen 2004 (nykanen-no.spam-cs.tut.fi)
30 * @author Pekka Jääskeläinen 2005,2010 (pjaaskel-no.spam-cs.tut.fi)
31 * @author Viljami Korhonen 2007 (viljami.korhonen-no.spam-tut.fi)
32 * @author Pekka Jääskeläinen 2005-2009 (pjaaskel-no.spam-cs.tut.fi)
33 * @note rating: red
34 */
35
36#include <typeinfo>
37#include <string>
38
40#include "MachineState.hh"
41#include "Machine.hh"
42#include "FunctionUnit.hh"
43#include "FUState.hh"
45#include "RegisterFileState.hh"
46#include "FUPort.hh"
47#include "OperationPool.hh"
48#include "BusState.hh"
50#include "InputPortState.hh"
52#include "HWOperation.hh"
53#include "OutputPortState.hh"
54#include "OperationContext.hh"
58#include "GCUState.hh"
59#include "ControlUnit.hh"
60#include "Operation.hh"
61#include "SimulatorToolbox.hh"
62#include "Memory.hh"
63#include "MemorySystem.hh"
65#include "StateLocator.hh"
66#include "TransportPipeline.hh"
67#include "StringTools.hh"
69#include "SimValue.hh"
70#include "PortState.hh"
71#include "ExecutionPipeline.hh"
72#include "GuardState.hh"
73#include "Guard.hh"
74#include "AddressSpaceCheck.hh"
75#include "TCEString.hh"
77
78using namespace TTAMachine;
79using std::string;
80
81/**
82 * Constructor.
83 */
84MachineStateBuilder::MachineStateBuilder(bool detailedSimulationModel) :
85 throwWhenConflict_(true),
86 detailedSimulationModel_(detailedSimulationModel) {
87}
88
89/**
90 * Destructor.
91 */
94
95/**
96 * Builds machine state from given machine.
97 *
98 * @param machine The machine of which machine state is built from.
99 * @param memSys Memory system instance.
100 * @return The created machine state.
101 * @exception IllegalMachine If machine state building fails.
102 */
105 const Machine& machine,
106 MemorySystem& memSys) {
107
108 StateLocator locator;
109 detectors_ = NULL;
110 return buildMachineState(machine, memSys, locator);
111}
112
113/**
114 * Builds machine state from given machine.
115 *
116 * This method allows giving an index of FU resource conflict detectors to
117 * create a model that detects FU resource conflicts.
118 *
119 * @param machine The machine of which machine state is built from.
120 * @param memSys Memory system instance.
121 * @param detectors The FU resource conflict detectors.
122 * @param throwWhenConflict Builds a model that throws an exception in case of
123 * resource conflict is detected.
124 * @return The created machine state.
125 * @exception IllegalMachine If machine state building fails.
126 */
129 const Machine& machine,
130 MemorySystem& memSys,
131 FUConflictDetectorIndex& detectors,
132 bool throwWhenConflict) {
133
134 StateLocator locator;
135 detectors_ = &detectors;
136 throwWhenConflict_ = throwWhenConflict;
137 return buildMachineState(machine, memSys, locator);
138}
139
140/**
141 * Builds machine state from given machine.
142 *
143 * @param machine Machine of which machine state is build from.
144 * @param memSys Memory system.
145 * @param locator Indexes states with components as keys.
146 * @return The created machine state instance.
147 * @exception IllegalMachine If machine state building fails.
148 */
151 const Machine& machine,
152 MemorySystem& memSys,
153 StateLocator& locator) {
154 detectors_ = NULL;
155 return buildMachineState(machine, memSys, locator);
156}
157
158/**
159 * Builds MachineState from given Machine.
160 *
161 * @param machine Machine.
162 * @param memSys Memory system.
163 * @param locator State locator.
164 * @return The created MachineState.
165 * @exception IllegalMachine If machine state building fails.
166 */
169 const Machine& machine,
170 MemorySystem& memSys,
171 StateLocator& locator) {
172
173 MachineState* machineState = new MachineState();
174
175 int controlUnitGuardLatency = 0;
176 if (machine.controlUnit() != NULL) {
177 ControlUnit* controlUnit = machine.controlUnit();
178 /// @todo This assumes that natural word width of GCU is 4 MAUs!
179 int WordWidthInMAUs = 1;
180
181 GCUState* gcu = new GCUState(
182 (controlUnit->delaySlots() + 1), 4, controlUnit->delaySlots(),
183 WordWidthInMAUs);
184 machineState->addGCUState(gcu);
185 controlUnitGuardLatency = controlUnit->globalGuardLatency();
186
187 for (int i = 0; i < controlUnit->portCount(); i++) {
188 BaseFUPort* port = controlUnit->port(i);
189 if (controlUnit->hasReturnAddressPort() &&
190 dynamic_cast<SpecialRegisterPort*>(port) ==
191 controlUnit->returnAddressPort()) {
192 // return address port shares a register with the RA register
193 // which resides inside the GCU
195 machineState, port, gcu, controlUnit, locator,
196 gcu->returnAddressRegister());
197 } else {
198 addPortToFU(machineState, port, gcu, controlUnit, locator);
199 }
200 }
201 addVirtualOpcodeSettingPortsToFU(*machineState, *gcu, *controlUnit);
202 }
203
205
207 AddressSpaceCheck addressSpaceCheck(pool);
208 MachineCheckResults results;
209 if (!addressSpaceCheck.check(machine, results)) {
210 string msg = "Problems while building machine state: " +
211 results.error(0).second;
212 throw IllegalMachine(__FILE__, __LINE__, __func__, msg) ;
213 }
214
215 for (int i = 0; i < FUs.count(); i++) {
216 FunctionUnit* unit = FUs.item(i);
217 FUState* state = NULL;
218 if (unit->addressSpace() != NULL) {
219 try {
220 MemorySystem::MemoryPtr memory = memSys.memory(*unit->addressSpace());
221 state = new MemoryAccessingFUState(unit->name(), *memory.get());
222 } catch (const Exception& i) {
223 string msg = "Problems building machine state: " +
224 i.errorMessage();
225 throw IllegalMachine(__FILE__, __LINE__, __func__, msg);
226 }
227 } else {
228 state = new FUState(unit->name());
229 }
230 machineState->addFUState(state, unit->name());
231
232 for (int k = 0; k < unit->portCount(); k++) {
233 BaseFUPort* port = unit->port(k);
234 addPortToFU(machineState, port, state, unit, locator);
235 }
236
237 addVirtualOpcodeSettingPortsToFU(*machineState, *state, *unit);
238 }
239
240 Machine::ImmediateUnitNavigator immediateUnits =
242 for (int i = 0; i < immediateUnits.count(); i++) {
243 LongImmediateUnitState* state =
245 immediateUnits.item(i)->numberOfRegisters(),
246 immediateUnits.item(i)->latency(),
247 immediateUnits.item(i)->name(),
248 immediateUnits.item(i)->width(),
249 immediateUnits.item(i)->extensionMode() ==
251
252 machineState->addLongImmediateUnitState(
253 state, immediateUnits.item(i)->name());
254 }
255
257 for (int i = 0; i < registers.count(); i++) {
258 RegisterFile* regFile = registers.item(i);
259 RegisterFileState* state = NULL;
260 state = new RegisterFileState(
261 regFile->numberOfRegisters(), regFile->width(),
262 regFile->zeroRegister());
263 machineState->addRegisterFileState(state, regFile->name());
264 }
265
267 for (int b = 0; b < busses.count(); ++b) {
268 Bus* bus = busses.item(b);
269 BusState* state = new BusState(bus->width());
270 machineState->addBusState(state, bus->name());
271 locator.addState(*bus, *state);
272
273 for (int i = 0; i < bus->guardCount(); ++i) {
274 const Guard* guard = bus->guard(i);
275 assert(guard != NULL);
276
277 const PortGuard* portGuard =
278 dynamic_cast<const PortGuard*>(guard);
279 const RegisterGuard* registerGuard =
280 dynamic_cast<const RegisterGuard*>(guard);
281 const UnconditionalGuard* uncondGuard =
282 dynamic_cast<const UnconditionalGuard*>(guard);
283
284 int guardLatency = controlUnitGuardLatency;
285 ReadableState* targetRegister = NULL;
286 if (portGuard != NULL) {
287
288 const BaseFUPort* thePort =
289 dynamic_cast<const BaseFUPort*>(portGuard->port());
290
291 assert(thePort != NULL);
292
293 PortState& port =
294 machineState->portState(
295 thePort->name(), thePort->parentUnit()->name());
296
297 if (&port == &NullPortState::instance()) {
298 throw IllegalMachine(
299 __FILE__, __LINE__, __func__,
302 str());
303 }
304 targetRegister = &port;
305
306 // 0-cycle guard latency means reading the value directly
307 // from the port.
308 if (guardLatency == 0) {
309 GuardState* guardState =
310 new DirectGuardState(*targetRegister);
311 machineState->addGuardState(guardState, *guard);
312 continue;
313 }
314 } else if (registerGuard != NULL) {
315
316 RegisterFileState& unit =
317 machineState->registerFileState(
318 registerGuard->registerFile()->name());
319
320 if (&unit == &NullRegisterFileState::instance()) {
321 throw IllegalMachine(
322 __FILE__, __LINE__, __func__,
325 ).str());
326 }
327 guardLatency += registerGuard->registerFile()->guardLatency();
328
329 targetRegister =
330 &unit.registerState(registerGuard->registerIndex());
331
332 // Values of registers are written later than guard are evaluated,
333 // so in case of 1-cycle register guard, can use direct guard
334 // without any pipeline.
335 if (guardLatency == 1) {
336 GuardState* guardState =
337 new DirectGuardState(*targetRegister);
338 machineState->addGuardState(guardState, *guard);
339 continue;
340 }
341 } else if (uncondGuard != NULL) {
342 // do not create a state object for unconditional guards,
343 // it makes no sense
344 continue;
345 } else {
346 abortWithError("Unknown guard type.");
347 }
348
349 GuardState* guardState =
350 new GuardState(*targetRegister, guardLatency);
351 machineState->addGuardState(guardState, *guard);
352 }
353 }
354
355 return machineState;
356}
357
358/**
359 * Adds the virtual opcode-setting ports to the FU.
360 *
361 * Expects that the FU is otherwise completely built.
362 *
363 * @param machineState The machine state to use.
364 * @param state The FUState to add the ports.
365 * @param unit The static function unit data from MOM.
366 */
367void
369 MachineState& machineState,
370 FUState& state,
371 FunctionUnit& unit) {
372 for (int i = 0; i < unit.portCount(); i++) {
373 BaseFUPort& port = *unit.port(i);
374
375 if (port.isOpcodeSetting()) {
376
377 PortState* p = &machineState.portState(port.name(), unit.name());
379
380 TriggeringInputPortState* triggerPort =
381 dynamic_cast<TriggeringInputPortState*>(p);
382
383 if (triggerPort == NULL) {
384 throw IllegalMachine(
385 __FILE__, __LINE__, __func__,
386 std::string("The opcode setting port ") + port.name() +
387 " is not triggering.");
388 }
389
390 // create a virtual port for all the opcodes that can be set
391 // through the port
392 for (int j = 0; j < unit.operationCount(); j++) {
393
394 HWOperation& hwOp = *unit.operation(j);
396 Operation* operation = NULL;
397 try {
398 operation = &pool.operation(hwOp.name().c_str());
399 } catch (const DynamicLibraryException& e) {
400 throw IllegalMachine(
401 __FILE__, __LINE__, __func__, e.errorMessage());
402 }
403
404 if (operation->isNull()) {
405 throw IllegalMachine(
406 __FILE__, __LINE__, __func__,
407 (boost::format(
408 "Operation '%s' not found in OSAL.") %
409 hwOp.name()).str());
410 }
411
412 // add executor for the operation
413 OperationExecutor* executor = NULL;
414 GCUState* gcu = dynamic_cast<GCUState*>(&state);
415 if (gcu != NULL) {
416 executor = new TransportPipeline(*gcu);
417 } else {
418 if (hwOp.latency() == 0) {
419 throw IllegalMachine(
420 __FILE__, __LINE__, __func__,
421 std::string("Operation ") + hwOp.name() + " in " +
422 unit.name() + " has latency of 0, which is not " +
423 "supported by TCE.");
424 }
425
426 bool conflictDetection = false;
427 if (detectors_ != NULL && unit.needsConflictDetection()) {
428 FUConflictDetectorIndex::iterator detectorI =
429 detectors_->find(unit.name());
430
431 if (detectorI != detectors_->end()) {
432 conflictDetection = true;
433
435 *(*detectorI).second;
436 // the FU has conflict detection enabled, always
437 // create a new ConflictDetectingOperationExecutor
438 // for all opcodes.
440 detector, detector.operationID(hwOp.name()),
441 state, hwOp, throwWhenConflict_);
442 }
443 }
444
445 if (!conflictDetection) {
446 bool multiLatencyOp = false;
447 const int totalLatency = hwOp.latency();
448 for (int i = operation->numberOfInputs() + 1;
449 i <= operation->numberOfInputs() +
450 operation->numberOfOutputs(); ++i) {
451 if (hwOp.latency(i) < totalLatency) {
452 multiLatencyOp = true;
453 break;
454 }
455 }
456
457 if (multiLatencyOp || detailedSimulationModel_) {
458 executor = new MultiLatencyOperationExecutor(
459 state, hwOp);
460 } else if (totalLatency == 1) {
461 executor = new OneCycleOperationExecutor(state);
462 } else {
463 executor =
465 totalLatency, state);
466 }
467 }
468 }
469
471 *executor, hwOp, machineState, state, unit);
472
473 state.addOperationExecutor(*executor, *operation);
474 machineState.addOperationExecutor(executor);
475
476 // virtual ports are put to the index with names like
477 // p1.add
478 /// @todo Improve this and change the naming to alu.add.p1,
479 /// or save the virtual ports to different index!
480 string name =
481 port.name() + "." +
482 StringTools::stringToLower(operation->name());
483 OperationExecutor* finalExecutor =
484 state.executor(*operation);
485 assert(executor != NULL);
488 *operation, *finalExecutor, state, *triggerPort);
489 state.addInputPortState(*opcodePort);
490 machineState.addPortState(
491 opcodePort, name, port.parentUnit()->name());
492 }
493 }
494 }
495}
496
497/**
498 * Adds a port that shares a register to FU.
499 *
500 * @param machineState Machine state which is built.
501 * @param port Port to be added.
502 * @param state FUState in which port is added.
503 * @param fu FU of which FUState is build from.
504 * @param locator StateLocator.
505 * @param sharedRegister The register the FUPort shares, if any. If this is
506 * set to NullSimValue then a new register (SimValue)
507 * is created for the FUPort.
508 */
509void
511 MachineState* machineState,
512 BaseFUPort* port,
513 FUState* state,
515 StateLocator& locator,
516 SimValue& sharedRegister) {
517
518 bool inputPort = false;
519 // a shortcut for figuring whether the port shares a register (in practice,
520 // connected to the return address register)
521 const bool sharesRegister = (&sharedRegister != &NullSimValue::instance());
522
523 // figure out the direction of the port
524 if (port->inputSocket() != NULL) {
525 inputPort = true;
526 } else if (port->outputSocket() != NULL) {
527 inputPort = false;
528 } else {
529 // Find out the direction of the port using operation<->port
530 // connections. This way we can simulate also individual function
531 // units which are not connected to any socket.
532 const TTAMachine::FunctionUnit& parentFU = *port->parentUnit();
533
534 // find out an operation that is connected to this port
535 bool operationBindingFound = false;
536 const TTAMachine::FUPort* fuPort =
537 dynamic_cast<TTAMachine::FUPort*>(port);
538 for (int i = 0; fuPort != NULL && !operationBindingFound &&
539 i < parentFU.operationCount(); ++i) {
540 const TTAMachine::HWOperation& operation = *parentFU.operation(i);
541 if (!operation.isBound(*fuPort))
542 continue;
543
544 const TTAMachine::ExecutionPipeline* pipe = operation.pipeline();
545
546 if (pipe == NULL)
547 continue;
548 // find out if there's a R/W pipeline component connected to
549 // the port
550 for (int cycle = 0; cycle < pipe->latency(); ++cycle) {
551 if (pipe->isPortRead(*fuPort, cycle)) {
552 inputPort = true;
553 operationBindingFound = true;
554 break;
555 } else if (pipe->isPortWritten(*fuPort, cycle)) {
556 inputPort = false;
557 operationBindingFound = true;
558 break;
559 } else {
560 // no pipeline connection to this port at this cycle
561 continue;
562 }
563 }
564 }
565
566 if (!operationBindingFound) {
568 << "warning: Cannot determine the direction of port "
569 << port->parentUnit()->name() + "." + port->name()
570 << ", omitting it from the simulation model."
571 << std::endl;
572 return;
573 }
574 }
575
576 if (inputPort) {
577 if (port->isOpcodeSetting()) {
578
579 TriggeringInputPortState* triggerPort = NULL;
580 if (sharesRegister) {
581 triggerPort =
582 new TriggeringInputPortState(*state, sharedRegister);
583 } else {
584 triggerPort =
585 new TriggeringInputPortState(*state, port->width());
586 }
587
588 state->addInputPortState(*triggerPort);
589 machineState->addPortState(
590 triggerPort, port->name(), port->parentUnit()->name());
591 locator.addState(*port, *triggerPort);
592
593 } else if (port->isTriggering()) {
594
595 TriggeringInputPortState* input = NULL;
596 if (sharesRegister) {
597 input = new TriggeringInputPortState(*state, sharedRegister);
598 } else {
599 input = new TriggeringInputPortState(*state, port->width());
600 }
601
602 machineState->addPortState(
603 input, port->name(), port->parentUnit()->name());
604 state->addInputPortState(*input);
605 locator.addState(*port, *input);
606 } else {
607 InputPortState* input = NULL;
608 if (sharesRegister) {
609 input = new InputPortState(*state, sharedRegister);
610 } else {
611 input = new InputPortState(*state, port->width());
612 }
613 machineState->addPortState(
614 input, port->name(), port->parentUnit()->name());
615 state->addInputPortState(*input);
616 locator.addState(*port, *input);
617 }
618 } else {
619 // port is an output port
620
621 OutputPortState* output = NULL;
622 if (sharesRegister) {
623 output = new OutputPortState(*state, sharedRegister);
624 } else {
625 output = new OutputPortState(*state, port->width());
626 }
627 machineState->addPortState(
628 output, port->name(), port->parentUnit()->name());
629 state->addOutputPortState(*output);
630 locator.addState(*port, *output);
631 }
632}
633
634/**
635 * Adds a port that does not share a register to FU.
636 *
637 * @param machineState Machine state which is built.
638 * @param port Port to be added.
639 * @param state FUState in which port is added.
640 * @param fu FU of which FUState is build from.
641 * @param locator StateLocator.
642 */
643void
645 MachineState* machineState,
646 BaseFUPort* port,
647 FUState* state,
648 FunctionUnit* unit,
649 StateLocator& locator) {
651 machineState, port, state, unit, locator, NullSimValue::instance());
652}
653
654/**
655 * Binds ports to operands.
656 *
657 * Operands are bound for OperationExecutor which is not yet inserted to
658 * the machine.
659 *
660 * @param executor OperationExecutor to bind the ports for.
661 * @param machineState MachineState to be built.
662 * @param state FUState of which ports are bound.
663 * @param unit FunctionUnit that owns the ports that are bound.
664 * @exception IllegalMachine If binding fails.
665 */
666void
668 OperationExecutor& executor, HWOperation& hwOperation,
669 MachineState& machineState, FUState&, FunctionUnit& unit) {
671 Operation& op = pool.operation(hwOperation.name().c_str());
672
673 if (&op == &NullOperation::instance()) {
674 const string msg =
676 Texts::TXT_OPERATION_X_NOT_FOUND) % hwOperation.name()).str();
677 throw IllegalMachine(__FILE__, __LINE__, __func__, msg);
678 }
679
680 const int operandCount = op.numberOfInputs() + op.numberOfOutputs();
681 for (int j = 1; j <= operandCount; j++) {
682
683 FUPort* port = hwOperation.port(j);
684 if (port == NULL) {
685 // unused operand
686 continue;
687 }
688 PortState& portState =
689 machineState.portState(port->name(), unit.name());
690 try {
691 executor.addBinding(j, portState);
692 } catch (const Exception& e) {
693 string msg = "Problems while building machine state: " +
694 e.errorMessage();
695 throw IllegalMachine(__FILE__, __LINE__, __func__, msg);
696 }
697 }
698}
#define __func__
#define abortWithError(message)
#define assert(condition)
TTAMachine::Machine * machine
the architecture definition of the estimated processor
std::map< std::string, FUResourceConflictDetector * > FUConflictDetectorIndex
virtual bool check(const TTAMachine::Machine &mach, MachineCheckResults &results) const
static std::ostream & warningStream()
std::string errorMessage() const
Definition Exception.cc:123
virtual OperationID operationID(const TCEString &operationName) const
virtual void addOutputPortState(PortState &port)
Definition FUState.cc:221
virtual void addInputPortState(PortState &port)
Definition FUState.cc:211
virtual void addOperationExecutor(OperationExecutor &opExec, Operation &op)
Definition FUState.cc:232
virtual OperationExecutor * executor(Operation &op)
Definition FUState.cc:358
SimValue & returnAddressRegister()
Error error(int index) const
MachineState * buildMachineState(const TTAMachine::Machine &machine, MemorySystem &memSys, StateLocator &locator)
MachineState * build(const TTAMachine::Machine &machine, MemorySystem &memSys)
void addPortToFU(MachineState *machineState, TTAMachine::BaseFUPort *port, FUState *state, TTAMachine::FunctionUnit *fu, StateLocator &locator)
bool detailedSimulationModel_
Set to true in case should build a detailed model which simulates FU stages, possibly with an externa...
FUConflictDetectorIndex * detectors_
The FU resource conflict detectors. They are needed while building the machine state model.
void bindPortsToOperands(OperationExecutor &executor, TTAMachine::HWOperation &hwOperation, MachineState &machineState, FUState &state, TTAMachine::FunctionUnit &unit)
MachineStateBuilder(bool detailedSimulationModel=false)
void addVirtualOpcodeSettingPortsToFU(MachineState &machineState, FUState &state, TTAMachine::FunctionUnit &unit)
bool throwWhenConflict_
True in case the built model should throw an exception in case of a resource conflict.
void addRegisterFileState(RegisterFileState *state, const std::string &name)
PortState & portState(const std::string &portName, const std::string &fuName)
void addBusState(BusState *state, const std::string &name)
void addFUState(FUState *state, const std::string &name)
void addGuardState(GuardState *state, const TTAMachine::Guard &guard)
RegisterFileState & registerFileState(const std::string &name)
void addOperationExecutor(OperationExecutor *executor)
void addPortState(PortState *state, const std::string &name, const std::string &fuName)
void addGCUState(GCUState *state)
void addLongImmediateUnitState(LongImmediateUnitState *state, const std::string &name)
MemoryPtr memory(const TTAMachine::AddressSpace &as)
boost::shared_ptr< Memory > MemoryPtr
static NullOperation & instance()
static NullPortState & instance()
Definition PortState.cc:96
static NullRegisterFileState & instance()
static SimValue & instance()
Definition SimValue.cc:1642
void addBinding(int io, PortState &port)
virtual TCEString name() const
Definition Operation.cc:93
bool isNull() const
virtual int numberOfInputs() const
Definition Operation.cc:192
virtual int numberOfOutputs() const
Definition Operation.cc:202
virtual RegisterState & registerState(int index)
static OperationPool & operationPool()
static SimulatorTextGenerator & textGenerator()
void addState(const TTAMachine::MachinePart &momComponent, StateData &state)
static std::string stringToLower(const std::string &source)
FunctionUnit * parentUnit() const
Definition BaseFUPort.cc:96
virtual int width() const
virtual bool isOpcodeSetting() const =0
virtual bool isTriggering() const =0
virtual int numberOfRegisters() const
virtual int width() const
int width() const
Definition Bus.cc:149
Guard * guard(int index) const
Definition Bus.cc:456
int guardCount() const
Definition Bus.cc:441
virtual TCEString name() const
SpecialRegisterPort * returnAddressPort() const
bool hasReturnAddressPort() const
int globalGuardLatency() const
bool isPortWritten(const FUPort &port, int cycle) const
bool isPortRead(const FUPort &port, int cycle) const
virtual AddressSpace * addressSpace() const
virtual HWOperation * operation(const std::string &name) const
virtual int operationCount() const
bool needsConflictDetection() const
virtual BaseFUPort * port(const std::string &name) const
ExecutionPipeline * pipeline() const
virtual FUPort * port(int operand) const
const std::string & name() const
bool isBound(const FUPort &port) const
ComponentType * item(int index) const
virtual RegisterFileNavigator registerFileNavigator() const
Definition Machine.cc:450
virtual FunctionUnitNavigator functionUnitNavigator() const
Definition Machine.cc:380
virtual ImmediateUnitNavigator immediateUnitNavigator() const
Definition Machine.cc:416
virtual BusNavigator busNavigator() const
Definition Machine.cc:356
virtual ControlUnit * controlUnit() const
Definition Machine.cc:345
@ SIGN
Sign extension.
Definition Machine.hh:82
FUPort * port() const
virtual Socket * outputSocket() const
Definition Port.cc:281
virtual Socket * inputSocket() const
Definition Port.cc:261
virtual std::string name() const
Definition Port.cc:141
virtual bool zeroRegister() const
virtual int guardLatency() const
const RegisterFile * registerFile() const
virtual int portCount() const
Definition Unit.cc:135
virtual boost::format text(int textId)
@ TXT_ILLEGAL_PROGRAM_PORT_STATE_NOT_FOUND
Text of the exception thrown when FUPortState could not be found and there is instruction referring t...
@ TXT_ILLEGAL_PROGRAM_RF_STATE_NOT_FOUND
Text of the exception thrown when RegisterFileState could not be found and there is instruction refer...