#include <RISCVTDGen.hh>

Inheritance diagram for RISCVTDGen:

Collaboration diagram for RISCVTDGen:

Public Member Functions
	RISCVTDGen (const TTAMachine::Machine &mach)

virtual	~RISCVTDGen ()=default

virtual void	generateBackend (const std::string &path) const

virtual std::string	generateBackend () const

Public Member Functions inherited from TDGen
	TDGen (const TTAMachine::Machine &mach, bool initialize=true)

virtual	~TDGen ()

Protected Member Functions
virtual void	initializeBackendContents ()

InstructionFormat *	findFormat (const std::string name) const

void	findCustomOps ()

void	writeInstructionDeclarations (std::ostream &o) const

void	writePatternDefinition (std::ostream &o, Operation &op)

void	writePatternDefinitions (std::ostream &o)

void	writeInstructionDeclaration (std::ostream &o, const std::string &name, const int encoding) const

std::string	transformTCEPattern (std::string pattern, const unsigned numIns) const

void	dumpClassDefinitions (std::ostream &) const

std::string	getFormatType (const std::string &opName) const

std::string	decimalsToHex (const std::string &pattern) const

Protected Member Functions inherited from TDGen
bool	writeRegisterInfo (std::ostream &o)

void	writeStartOfRegisterInfo (std::ostream &o)

void	writeOperandDefs (std::ostream &o)

void	writeIntegerImmediateDefs (std::ostream &o, const ImmInfo &iivis)

void	writeMoveImmediateDefs (std::ostream &o)

void	writeInstrInfo (std::ostream &o)

void	writeBackendCode (std::ostream &o)

void	writeTopLevelTD (std::ostream &o)

void	writeInstrFormats (std::ostream &o)

bool	checkRequiredRegisters ()

void	analyzeRegisters ()

void	analyzeRegisterFileClasses ()

void	analyzeRegisters (RegsToProcess regsToProcess)

void	gatherAllMachineOperations ()

void	analyzeMachineVectorRegisterClasses ()

void	analyzeMachineRegisters ()

void	associateRegistersWithVectorRegisterClasses ()

void	orderEqualWidthRegistersToRoundRobin ()

void	verbose (const TCEString &msg) const

bool	isVectorLoadOperation (const Operation &op) const

bool	isVectorStoreOperation (const Operation &op) const

bool	isWrongEndianessVectorOp (const Operation &op) const

bool	isVectorBitwiseOperation (const Operation &op) const

bool	hasRawOperands (const Operation &op) const

int	subwordWidthOfRawData (const Operation &op) const

bool	hasRegisterClassSupport (const Operation &op) const

bool	hasRegisterClassSupport (const TDGenerator::ValueType &vt) const

TCEString	associatedVectorRegisterClass (const Operand &operand) const

void	writePatternReplacement (std::ostream &o, const TCEString &origPat, const TCEString &replacerPat) const

void	writeOperationDefUsingGivenOperandTypes (std::ostream &o, Operation &op, bool skipPattern, std::vector< TDGenerator::ValueType > inputs, std::vector< TDGenerator::ValueType > outputs, TCEString instrSuffix="")

void	writeRegisterDef (std::ostream &o, const RegInfo &reg, const std::string regName, const std::string regTemplate, const std::string aliases, RegType type)

void	write64bitRegisterInfo (std::ostream &o)

void	write32bitRegisterInfo (std::ostream &o)

void	write16bitRegisterInfo (std::ostream &o)

void	write8bitRegisterInfo (std::ostream &o)

void	write1bitRegisterInfo (std::ostream &o)

void	writeRARegisterInfo (std::ostream &o)

void	writeGuardRegisterClassInfo (std::ostream &o)

void	writeVectorRegisterBaseClasses (std::ostream &o) const

void	writeVectorRegisterNames (std::ostream &o)

void	writeVectorRegisterClasses (std::ostream &o) const

void	writeVectorOperationDefs (std::ostream &o, Operation &op, bool skipPattern)

void	writeVectorOperationDef (std::ostream &o, Operation &op, TCEString valueTypes, const TCEString &attributes, bool skipPattern)

void	saveAdditionalVectorOperationInfo (const Operation &op, const TCEString &valueTypes, bool isRegisterOp)

void	writeVectorMemoryOperationDefs (std::ostream &o, Operation &op, bool skipPattern)

void	writeVectorBitwiseOperationDefs (std::ostream &o, Operation &op, bool skipPattern)

void	writeVectorRegisterMoveDefs (std::ostream &o)

void	writeVectorTruncStoreDefs (std::ostream &o) const

void	writeScalarToVectorDefs (std::ostream &o) const

void	writeVectorBitConversions (std::ostream &o) const

void	writeScalarOperationExploitations (std::ostream &o)

void	writeVectorLoadStoreOperationExploitations (std::ostream &o)

void	writeWiderVectorOperationExploitations (std::ostream &o)

void	genGeneratedTCEPlugin_getStore (std::ostream &o) const

void	genGeneratedTCEPlugin_getLoad (std::ostream &o) const

void	genGeneratedTCEPlugin_isVectorRegisterMove (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorValueType (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorBroadcastOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorPackOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorSelectOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorShuffle1Opcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorShuffle2Opcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getConstantVectorShuffleOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getExtractElemOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorShlSameOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorShrSameOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorShruSameOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorAndSameOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorIorSameOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorXorSameOpcode (std::ostream &o) const

void	genTCETargetLoweringSIMD_addVectorRegisterClasses (std::ostream &o) const

void	genTCETargetLoweringSIMD_associatedVectorRegClass (std::ostream &o) const

void	genTCETargetLoweringSIMD_getSetCCResultVT (std::ostream &o) const

void	genTCEInstrInfoSIMD_copyPhysVectorReg (std::ostream &o) const

void	genGeneratedTCEPlugin_getVectorImmediateOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getGatherOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getLoadOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getAddOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getShlOpcode (std::ostream &o) const

void	genGeneratedTCEPlugin_getIorOpcode (std::ostream &o) const

void	writeVectorImmediateWriteDefs (std::ostream &instrInfoTD)

void	createMinMaxDef (const TCEString &opName, const TCEString &valueName, std::ostream &os)

void	createVectorMinMaxDef (const TCEString &opName, int bits, char llvmTypeChar, const TCEString &postFix, std::ostream &os)

void	writeOperationDefs (std::ostream &o, Operation &op, bool skipPattern)

void	writeOperationDef (std::ostream &o, Operation &op, const std::string &operandTypes, const std::string &attrs, bool skipPattern, std::string backendPrefix="")

std::string	emulatingOpNodeLLVMName (const Operation &op, const OperationDAG &dag, const OperationNode &node, const std::string &operandTypes)

void	writeEmulationPattern (std::ostream &o, const Operation &op, const OperationDAG &dag)

void	write64bitMoveDefs (std::ostream &o)

void	writeControlFlowInstrDefs (std::ostream &os)

void	writeCondBranchDefs (std::ostream &os)

void	writeCallDef (std::ostream &o)

void	writeHWLoopDef (std::ostream &o)

virtual void	writeCallDefRegs (std::ostream &o)

void	writeRegisterClasses (std::ostream &o)

virtual TCEString	llvmOperationPattern (const Operation &op, char operandType=' ') const

virtual TCEString	llvmOperationName (const TCEString &opName) const

bool	operationCanBeMatched (const Operation &op, std::set< std::string > *recursionCycleCheck=NULL, bool recursionHasStore=false)

bool	operationDAGCanBeMatched (const OperationDAG &op, std::set< std::string > *recursionCycleCheck=NULL, bool recursionHasStore=false)

const OperationDAG *	getMatchableOperationDAG (const Operation &op)

const std::vector< OperationDAG * >	getMatchableOperationDAGs (const Operation &op)

std::string	tceOperationPattern (const Operation &op)

std::string	patOutputs (const Operation &op, const std::string &oprTypes)

std::string	patInputs (const Operation &op, const std::string &oprTypes)

virtual std::string	operandToString (const Operand &operand, bool match, char operandType, const std::string &immDefName="")

std::string	operationNodeToString (const Operation &op, const OperationDAG &dag, const OperationNode &node, bool emulationPattern, const std::string &operandTypes)

std::string	constantNodeString (const Operation &op, const OperationDAG &dag, const ConstantNode &node, const std::string &operandTypes, const OperationDAGNode *successor=nullptr)

std::string	dagNodeToString (const Operation &op, const OperationDAG &dag, const OperationDAGNode &node, bool emulationPattern, const std::string &operandTypes, const Operation emulatingOp=nullptr, const OperationDAGNode successor=nullptr)

std::string	operationPattern (const Operation &op, const OperationDAG &dag, const std::string &operandTypes)

virtual char	operandChar (Operand &operand)

std::string	createDefaultOperandTypeString (const Operation &op)

void	writeVectorStoreDefs (std::ostream &o, const TCEString &opName, const TCEString &opNameSuffix, bool addrImm, const TCEString &dataType, bool writePredicatedVersions)

void	genTCEInstrInfo_copyPhys64bitReg (std::ostream &o) const

void	writeArgRegsArray (std::ostream &os)

virtual void	createSelectPatterns (std::ostream &os)

void	writeAddressingModeDefs (std::ostream &o)

void	createByteExtLoadPatterns (std::ostream &os)

void	createShortExtLoadPatterns (std::ostream &os)

void	create32BitExtLoadPatterns (std::ostream &os)

void	createEndiannesQuery (std::ostream &os)

void	createConstantMaterializationQuery (std::ostream &os)

void	createConstShiftPatterns (std::ostream &os)

void	writeOperationDefs (std::ostream &o, Operation &op, const std::string &operandTypes, const std::string &attrs, bool skipPattern, std::string backendPrefix="")

void	writeVectorStoreDefs (std::ostream &o, Operation &op, int vectorLen)

void	writeVectorTruncStoreDefs (std::ostream &o, Operation &op, int bitsize, int vectorLen)

void	createGetMaxMemoryAlignment (std::ostream &os) const

void	writeVectorAnyextPattern (std::ostream &o, Operation &op, const TCEString &loadPatternName, int vectorLen)

void	writeVectorLoadDefs (std::ostream &o, const TCEString &opName, const TCEString &opNameSuffix, bool addrImm, const TCEString &resultType, const TCEString &loadPatternName, bool writePredicatedVersions)

virtual void	writeImmediateDef (std::ostream &o, const std::string &defName, const std::string &operandType, const std::string &predicate)

void	writeInstrDef (std::ostream &o, const std::string &instrDefName, const std::string &outs, const std::string &ins, const std::string &asmString, const std::string &pattern)

void	writeVectorLoadDefs (std::ostream &o, Operation &op, const TCEString &loadPatternName, int vectorLen)

void	writeBooleanStorePatterns (std::ostream &os)

std::string	immediatePredicate (int64_t lowerBoundInclusive, uint64_t upperBoundInclusive)

std::string	immediateOperandNameForEmulatedOperation (const OperationDAG &, const Operand &operand)

bool	areImmediateOperandsLegal (const Operation &operation, const std::string &operandTypes) const

void	writeBroadcastDefs (std::ostream &o, Operation &op, int vectorLen)

bool	writePortGuardedJumpDefPair (std::ostream &os, const TCEString &tceop1, const TCEString &tceop2, bool fp=false)

std::string	subPattern (const Operation &op, const OperationDAG &dag)

OperationDAG *	createTrivialDAG (Operation &op)

bool	canBeImmediate (const OperationDAG &dag, const TerminalNode &node)

virtual void	createMinMaxGenerator (std::ostream &os)

void	writeCallSeqStart (std::ostream &os)

void	writeMiscPatterns (std::ostream &o)

void	generateLoadStoreCopyGenerator (std::ostream &os)

void	createParamDRegNums (std::ostream &os)

virtual void	createVectorRVDRegNums (std::ostream &os)

void	writeCallingConv (std::ostream &os)

void	writeCallingConvLicenceText (std::ostream &os)

void	writeConstShiftPat (std::ostream &os, const TCEString &nodeName, const TCEString &opNameBase, int i)

void	createBoolAndHalfLoadPatterns (std::ostream &os)

virtual void	createConstantMaterializationPatterns (std::ostream &os)

void	createBranchAnalysis (std::ostream &os)

void	genTCERegisterInfo_setReservedVectorRegs (std::ostream &os) const

void	writeGetPointerAdjustmentQuery (std::ostream &os) const

bool	canBePredicated (Operation &op, const std::string &operandTypes)

TCEString	getLLVMPatternWithConstants (const Operation &op, const std::string &operandTypes, const std::string &operand0, const std::string &operand1) const

std::string	operandTypesToRegisters (const std::string &opdTypes) const

char	operandTypeToRegister (const char &opdType) const

TCEString	getMovePattern (const char &opdType, const std::string &inputPattern) const

void	initializeBackendContents ()

Protected Attributes
BinaryEncoding *	bem_

std::map< std::string, int >	customOps_

std::string	declarationStr_

std::string	patternStr_

Protected Attributes inherited from TDGen
std::map< ImmInfoKey, std::string >	immOperandDefs_
	Maps (operation, operand) pairs to i32 immediate operand definition names.

const TTAMachine::Machine &	mach_

ImmInfo *	immInfo_

unsigned	dregNum_

std::string	registerInfo_

std::string	addressingModeDefs_

std::string	operandDefs_

std::string	instrInfo_

std::string	instrFormats_

std::string	callingConv_

std::string	argRegsArray_

std::string	backendCode_

std::string	topLevelTD_

OperationDAGSelector::OperationSet	allOpNames_
	Contains all operation names in upper case.

std::map< TCEString, Operation * >	scalarOps_
	Contains all scalar operations (<Name, Operation>).

std::map< TCEString, Operation * >	vectorOps_
	Contains all vector operations (<Name, Operation>).

std::map< int, TCEString >	baseClasses_
	Contains vector base classes for register files (<Width, Name>).

std::map< int, std::vector< TDGenerator::RegisterInfo > >	registers_
	Contains registers fit for being vector registers (<Width, Registers>).

std::map< TCEString, TDGenerator::RegisterClass >	vRegClasses_
	Contains required vector register classes (<ValueType, RegClass>).

std::map< TCEString, TDGenerator::InstructionInfo >	registerStores_
	All register store operations (<ValueType, InstrInfo>).

std::map< TCEString, TDGenerator::InstructionInfo >	registerLoads_
	All register load operations (<ValueType, InstrInfo>).

std::map< TCEString, TDGenerator::InstructionInfo >	immediateStores_
	All immediate store operations (<ValueType, InstrInfo>).

std::map< TCEString, TDGenerator::InstructionInfo >	immediateLoads_
	All immediate load operations (<ValueType, InstrInfo>).

std::map< TCEString, TCEString >	packOperations_
	Contains machine's PACK instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	vbcastOperations_
	Contains machine's VBCAST instructions (<ValueType, InstrName>).

std::vector< std::pair< const Operation *, TCEString > >	truncOperations_
	Contains machine's TRUNCxx/CFH instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	vselectOperations_
	Contains machine's VSELECT instructions (<instrName, ValueType>).

std::map< TCEString, TCEString >	vshuffle1Operations_
	Contains machine's VSHUFFLE1 instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	vshuffle2Operations_
	Contains machine's VSHUFFLE2 instructions (<ValueType, InstrName>).

std::map< std::pair< TCEString, std::vector< int > >, TCEString >	vcshuffleOperations_
	Contains machine's VCSHUFFLE instructions (<<ValueType, ConstantSelects>, InstrName>).

std::map< TCEString, TCEString >	extractElemOperations_
	Contains machine's EXTRACTELEM instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	shlSameOperations_
	Contains machine's SHLSAME instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	shrSameOperations_
	Contains machine's SHRSAME instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	shruSameOperations_
	Contains machine's SHRUSAME instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	andSameOperations_
	Contains machine's ANDSAME instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	iorSameOperations_
	Contains machine's IORSAME instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	xorSameOperations_
	Contains machine's XORSAME instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	gatherOperations_
	Contains machine's GATHER instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	addOperations_
	Contains machine's add instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	shlOperations_
	Contains machine's shl instructions (<ValueType, InstrName>).

std::map< TCEString, TCEString >	iorOperations_
	Contains machine's shl instructions (<ValueType, InstrName>).

std::set< TCEString >	movOperations_
	Contains all moves between register classes (<InstrName>).

std::vector< RegInfo >	regs1bit_

std::vector< RegInfo >	regs8bit_

std::vector< RegInfo >	regs16bit_

std::vector< RegInfo >	regs32bit_

std::vector< RegInfo >	regs64bit_

std::vector< std::string >	llvmGuardRegs_
	The LLVM register defs used as guards.

std::map< std::string, RegInfo >	regs_
	Map of generated llvm register names to physical register in the machine.

std::vector< std::string >	argRegNames_

std::vector< std::string >	resRegNames_

std::vector< std::string >	gprRegNames_

std::map< std::string, std::string >	opNames_

std::map< std::string, std::string >	truePredOps_

std::map< std::string, std::string >	falsePredOps_

int	maxVectorSize_

int	highestLaneInt_

int	highestLaneBool_

bool	hasExBoolRegs_

bool	hasExIntRegs_

bool	hasSelect_

bool	hasConditionalMoves_

int	maxScalarWidth_

bool	littleEndian_

unsigned int	argRegCount_

unsigned int	requiredI32Regs_
	Minimum number of 32 bit registers.

unsigned int	requiredI64Regs_

bool	prebypassStackIndeces_

bool	use64bitForFP_

std::set< RegInfo >	guardedRegs_
	List of register that are associated with a guard on a bus.

std::set< const TTAMachine::RegisterFile *, TTAMachine::MachinePart::Comparator >	tempRegFiles_
	Register files whose last reg reserved for temp reg copies.

RegClassMap	regsInClasses_
	All registers in certain group.

RegClassMap	regsInRFClasses_

std::vector< std::string >	constantMaterializationPredicates_
	All predicates used in constant materialization patterns.

Additional Inherited Members
Static Public Attributes inherited from TDGen
static const char	OT_REG_BOOL = 'b'

static const char	OT_REG_INT = 'r'

static const char	OT_REG_LONG = 's'

static const char	OT_REG_FP = 'f'

static const char	OT_REG_HFP = 'h'

static const char	OT_REG_DOUBLE = 'd'

static const char	OT_IMM_BOOL = 'j'

static const char	OT_IMM_INT = 'i'

static const char	OT_IMM_FP = 'k'

static const char	OT_IMM_HFP = 'l'

static const char	OT_IMM_LONG = 'a'

static const char	OT_VREG_BOOL = 'a'

static const char	OT_VREG_INT8 = 'q'

static const char	OT_VREG_INT16 = 't'

static const char	OT_VREG_INT32 = 'u'

static const char	OT_VREG_FP = 'e'

static const char	OT_VREG_HFP = 'g'

Protected Types inherited from TDGen
enum	RegType { GPR = 0 , RESERVED , ARGUMENT , RESULT }

enum	RegsToProcess { ALL_REGISTERS , ONLY_EXTRAS , ONLY_LANES , ONLY_NORMAL }

typedef std::map< std::string, std::vector< std::string > >	RegClassMap

Static Protected Member Functions inherited from TDGen
static std::vector< std::string >	supportedStackAccessOperations (const TTAMachine::Machine &mach)

Static Protected Attributes inherited from TDGen
static const int	FP_SUBW_WIDTH
	Float type subword width.

static const int	HFP_SUBW_WIDTH
	Half float type subword width.

static const int	BOOL_SUBW_WIDTH
	Bool type subword width.

static const int	MAX_SCALAR_WIDTH = 64
	Distincts wide vs scalar registers.

static const int	MAX_SUBW_COUNT = SIMD_WORD_WIDTH / BYTE_BITWIDTH
	Maximum number of subwords that any SIMD operation can have.

static const bool	EXPLOIT_BIGGER_REGISTERS = true
	If set to true, smaller vector value types can be stored to larger register files, e.g. v4i8 vectors can be stored to registers that are over 32 bits in size.

static const std::map< TCEString, TCEString >	OPERATION_PATTERNS_
	Contains <BaseOpName, OpPattern> key-value pairs.

static const std::string	guardRegTemplateName = "Guard"

Detailed Description

Definition at line 42 of file RISCVTDGen.hh.

Constructor & Destructor Documentation

◆ RISCVTDGen()

RISCVTDGen::RISCVTDGen ( const TTAMachine::Machine & mach )

Definition at line 52 of file RISCVTDGen.cc.

    : TDGen(mach, false), bem_(NULL) {
    bem_ = BEMGenerator(mach).generate();
    assert(bem_ != NULL);
    findCustomOps();
    initializeBackendContents();
}

References assert, bem_, findCustomOps(), BEMGenerator::generate(), and initializeBackendContents().

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◆ ~RISCVTDGen()

virtual RISCVTDGen::~RISCVTDGen ( )

virtualdefault

Member Function Documentation

◆ decimalsToHex()

std::string RISCVTDGen::decimalsToHex ( const std::string & pattern ) const

protected

OpenASIP converts hex numbers to unsigned by default. The converted number might not fit into i32. This function transforms the given instruction pattern to use hex encoding.

Parameters

pattern The instruction pattern.

Returns: The instruction pattern in hex format.

Definition at line 69 of file RISCVTDGen.cc.

                                                        {
    std::regex patternRegex(R"((i32\s)(-?\d+))");
    std::smatch match;
    std::string modifiedPattern = pattern;
 
    auto start = modifiedPattern.cbegin();
    while (std::regex_search(
        start, modifiedPattern.cend(), match, patternRegex)) {
        try {
            std::string numStr = match[2].str();
            std::string hexStr;
 
            if (numStr[0] == '-') {
                int num = std::stoi(numStr);
                hexStr = TCEString::intToHexString(num);
            } else {
                unsigned long num = std::stoul(numStr);
                hexStr = TCEString::unsignedToHexString(num);
            }
 
            // Calculate the actual start position in the modified string
            size_t matchPos = match.position(2) + std::distance(
                modifiedPattern.cbegin(), start);
            modifiedPattern.replace(matchPos, match.length(2), hexStr);
            // Move start past the replaced part
            start = modifiedPattern.cbegin() + matchPos + hexStr.length();
        } catch (const std::invalid_argument& e) {
            std::cerr << "Invalid argument: " << e.what() << std::endl;
            break;
        } catch (const std::out_of_range& e) {
            std::cerr << "Out of range error: " << e.what() << std::endl;
            break;
        }
    }
 
    return modifiedPattern;
}

References TCEString::intToHexString(), and TCEString::unsignedToHexString().

Referenced by transformTCEPattern().

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◆ dumpClassDefinitions()

void RISCVTDGen::dumpClassDefinitions ( std::ostream & o ) const

protected

Definition at line 313 of file RISCVTDGen.cc.

                                                    {
    o << "/*\n";
    o << " * Generated by OpenASIP\n";
    /* These are not needed since the target contents would be different
    between versions if necessary. */
    o << " * OpenASIP version: " << Application::TCEVersionString() << "\n";
    o << " * LLVM version: " << LLVM_VERSION << "\n";
    o << " */\n";
    o << "\n";
    o << "class OARVInstR1<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,\n";
    o << "    dag outs, dag ins, string opcodestr, string argstr>\n";
    o << "    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {\n";
    o << "  bits<5> rs1;\n";
    o << "\n";
    o << "  let Inst{31-25} = funct7;\n";
    o << "  let Inst{24-20} = 0;\n";
    o << "  let Inst{19-15} = rs1;\n";
    o << "  let Inst{14-12} = funct3;\n";
    o << "  let Inst{11-7} = 0;\n";
    o << "  let Inst{6-0} = opcode.Value;\n";
    o << "}\n";
    o << "\n";
    o << "class OARVInstR1R<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,\n";
    o << "    dag outs, dag ins, string opcodestr, string argstr>\n";
    o << "    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {\n";
    o << "  bits<5> rs1;\n";
    o << "  bits<5> rd;\n";
    o << "\n";
    o << "  let Inst{31-25} = funct7;\n";
    o << "  let Inst{24-20} = 0;\n";
    o << "  let Inst{19-15} = rs1;\n";
    o << "  let Inst{14-12} = funct3;\n";
    o << "  let Inst{11-7} = rd;\n";
    o << "  let Inst{6-0} = opcode.Value;\n";
    o << "}\n";
    o << "\n";
    o << "let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in\n";
    o << "class OARVR2R<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, string\n";
    o << "             opcodestr, bit Commutable = 0>\n";
    o << "    : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1,\n";
    o << "              GPR:$rs2), opcodestr, \"$rd, $rs1, $rs2\"> {\n";
    o << "  let isCommutable = Commutable;\n";
    o << "}\n";
    o << "\n";
    o << "let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in\n";
    o << "class OARVR3R<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, string\n";
    o << "             opcodestr, bit Commutable = 0>\n";
    o << "    : RVInstR4<funct2, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1,\n";
    o << "              GPR:$rs2, GPR:$rs3), opcodestr, \"$rd, $rs1, $rs2, $rs3\"> {\n";
    o << "  let isCommutable = Commutable;\n";
    o << "}\n";
    o << "\n";
    o << "let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in\n";
    o << "class OARVR1R<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, string\n";
    o << "           opcodestr>\n";
    o << "    : OARVInstR1R<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),\n";
    o << "              opcodestr, \"$rd, $rs1\"> {\n";
    o << "}\n";
    o << "\n";
    o << "let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in\n";
    o << "class OARVR1<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, string\n";
    o << "           opcodestr>\n";
    o << "    : OARVInstR1<funct7, funct3, opcode, (outs), (ins GPR:$rs1),\n";
    o << "              opcodestr, \"$rs1\"> {\n";
    o << "}\n";
}

References Application::TCEVersionString().

Referenced by writeInstructionDeclarations().

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◆ findCustomOps()

void RISCVTDGen::findCustomOps ( )

protected

Definition at line 109 of file RISCVTDGen.cc.

                          {
    customOps_.clear();
    const std::vector<std::string> formatsToSearch = {
        RISCVFields::RISCV_R_TYPE_NAME,
        RISCVFields::RISCV_R1R_TYPE_NAME,
        RISCVFields::RISCV_R1_TYPE_NAME,
        RISCVFields::RISCV_R3R_TYPE_NAME
    };
    for (const std::string& fName : formatsToSearch) {
        InstructionFormat* format = bem_->instructionFormat(fName);
        if (format == NULL) {
            continue;
        }
        for (int i = 0; i < format->operationCount(); i++) {
            const std::string op = format->operationAtIndex(i);
            if (!MapTools::containsKey(RISCVFields::RISCVRTypeOperations, op)) {
                customOps_.insert({op, format->encoding(op)});
            }
        }
    }
}

References bem_, MapTools::containsKey(), customOps_, InstructionFormat::encoding(), BinaryEncoding::instructionFormat(), InstructionFormat::operationAtIndex(), InstructionFormat::operationCount(), RISCVFields::RISCV_R1_TYPE_NAME, RISCVFields::RISCV_R1R_TYPE_NAME, RISCVFields::RISCV_R3R_TYPE_NAME, RISCVFields::RISCV_R_TYPE_NAME, and RISCVFields::RISCVRTypeOperations.

Referenced by RISCVTDGen().

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◆ findFormat()

InstructionFormat * RISCVTDGen::findFormat ( const std::string name ) const

protected

◆ generateBackend() [1/2]

std::string RISCVTDGen::generateBackend ( ) const

virtual

Writes tce backend plugin code into a single string. Used for hash generation.

Reimplemented from TDGen.

Definition at line 308 of file RISCVTDGen.cc.

                                  {
    return declarationStr_;
}

References declarationStr_.

◆ generateBackend() [2/2]

void RISCVTDGen::generateBackend ( const std::string & path ) const

virtual

Generates all files required to build a tce backend plugin (excluding static plugin code included from include/llvm/TCE/).

Reimplemented from TDGen.

Definition at line 299 of file RISCVTDGen.cc.

                                                       {
    std::ofstream customInstrInfoTD;
    customInstrInfoTD.open((path + "/RISCVInstrInfoOpenASIP.td").c_str());
    customInstrInfoTD << declarationStr_;
    customInstrInfoTD << patternStr_;
    customInstrInfoTD.close();
}

References declarationStr_, and patternStr_.

Referenced by main().

◆ getFormatType()

std::string RISCVTDGen::getFormatType ( const std::string & opName ) const

protected

Definition at line 134 of file RISCVTDGen.cc.

                                                       {
    OperationPool opPool;
    Operation& op = opPool.operation(opName.c_str());
    const unsigned numIns = op.numberOfInputs();
    const unsigned numOuts = op.numberOfOutputs();
    if (numIns == 3 && numOuts == 1) {
        return "OARVR3R";
    } else if (numIns == 2 && numOuts == 1) {
        return "OARVR2R";
    } else if (numIns == 1 && numOuts == 1) {
        return "OARVR1R";
    } else if (numIns == 1 && numOuts == 0) {
        return "OARVR1";
    } else {
        std::cerr << "Error: cannot find format type for operation "
                << op.name() << " with numIns=" << numIns << " numOuts="
                << numOuts << std::endl;
        std::cerr << "Legal configurations: " << std::endl;
        std::cerr << "  numIns=3, numOuts=1"  << std::endl;
        std::cerr << "  numIns=2, numOuts=1"  << std::endl;
        std::cerr << "  numIns=1, numOuts=1"  << std::endl;
        std::cerr << "  numIns=1, numOuts=0"  << std::endl;
        assert(false);
    }
    return "";
}

References assert, Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), and OperationPool::operation().

Referenced by writeInstructionDeclaration().

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◆ initializeBackendContents()

void RISCVTDGen::initializeBackendContents ( )

protectedvirtual

Definition at line 284 of file RISCVTDGen.cc.

                                      {
    std::ostringstream tdDeclarationBuffer;
    std::ostringstream tdPatternBuffer;
    writeInstructionDeclarations(tdDeclarationBuffer);
    declarationStr_ = tdDeclarationBuffer.str();
    writePatternDefinitions(tdPatternBuffer);
    patternStr_ = tdPatternBuffer.str();
 
#ifdef DEBUG_RISCV_TDGEN
    std::cout << declarationStr_;
    std::cout << patternStr_;
#endif
}

References declarationStr_, patternStr_, writeInstructionDeclarations(), and writePatternDefinitions().

Referenced by RISCVTDGen().

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◆ transformTCEPattern()

std::string RISCVTDGen::transformTCEPattern	(	std::string	pattern,
		const unsigned	numIns
	)		const

protected

OpenASIP uses different reg declarations and pattern structure than the upstream RISC-V BE. This method transforms the TDGen generated patterns to the RISC-V one.

Parameters

pattern The pattern generated by TDGen

Returns: The RISC-V target pattern

Definition at line 200 of file RISCVTDGen.cc.

                                                             {
    assert(numIns == 3 || numIns == 2 || numIns == 1);
    // Remove the output specifier
    size_t pos = pattern.find(',');
    if (pos != std::string::npos) {
        pattern = pattern.substr(pos + 2);
    }
    // Replace register specifiers
    TCEString patTCEStr = TCEString(pattern);
    patTCEStr.replaceString("R32IRegs:$op1", "(XLenVT GPR:$rs1)");
    if (numIns == 3) {
        patTCEStr.replaceString("R32IRegs:$op2", "(XLenVT GPR:$rs2)");
        patTCEStr.replaceString("R32IRegs:$op3", "(XLenVT GPR:$rs3)");
        patTCEStr.replaceString("R32IRegs:$op4", "(XLenVT GPR:$rd)");
    } else if (numIns == 2) {
        patTCEStr.replaceString("R32IRegs:$op2", "(XLenVT GPR:$rs2)");
        patTCEStr.replaceString("R32IRegs:$op3", "(XLenVT GPR:$rd)");
    } else {
        patTCEStr.replaceString("R32IRegs:$op2", "(XLenVT GPR:$rd)");
    }
    patTCEStr.replaceString("\n", "");
    patTCEStr = decimalsToHex(patTCEStr);
    return patTCEStr;
}

References assert, decimalsToHex(), and TCEString::replaceString().

Referenced by writePatternDefinition().

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◆ writeInstructionDeclaration()

void RISCVTDGen::writeInstructionDeclaration	(	std::ostream &	o,
		const std::string &	name,
		const int	encoding
	)		const

protected

Definition at line 162 of file RISCVTDGen.cc.

                                                                  {
    const TCEString opName = TCEString(name);
    const std::string f3 = RISCVTools::getFunc3Str(encoding);
    std::string f7 = RISCVTools::getFunc7Str(encoding);
    const std::string fType = getFormatType(name);
    assert(fType != "");
    std::string opc = "OPC_CUSTOM_0";
    if (fType == "OARVR3R") {
        std::string opc = "OPC_CUSTOM_1";
        // rs3 takes 5 bits from f7
        f7 = RISCVTools::getFunc2Str(encoding);
    } else {
        f7 = RISCVTools::getFunc7Str(encoding);
    }
    o << "def " << "OA_" + opName.upper() << " : " << fType << "<" << f7
      <<", " << f3 << ", " << opc << ", \"" << "oa_" + name << "\">;";
    o << "\n";
}

References assert, getFormatType(), RISCVTools::getFunc2Str(), RISCVTools::getFunc3Str(), RISCVTools::getFunc7Str(), and TCEString::upper().

Referenced by writeInstructionDeclarations().

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◆ writeInstructionDeclarations()

void RISCVTDGen::writeInstructionDeclarations ( std::ostream & o ) const

protected

Definition at line 184 of file RISCVTDGen.cc.

                                                            {
    dumpClassDefinitions(o);
    for (auto op : customOps_) {
        writeInstructionDeclaration(o, op.first, op.second);
    }
}

References customOps_, dumpClassDefinitions(), and writeInstructionDeclaration().

Referenced by initializeBackendContents().

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◆ writePatternDefinition()

void RISCVTDGen::writePatternDefinition	(	std::ostream &	o,
		Operation &	op
	)

protected

Definition at line 227 of file RISCVTDGen.cc.

                                                               {
    const unsigned numIns = op.numberOfInputs();
    const unsigned numOuts = op.numberOfOutputs();
    if (!operationCanBeMatched(op) || numIns > 3 || numIns < 1 ||
        numOuts != 1) {
        std::cout << "Skipping pattern for " << op.name() << std::endl;
        return;
    }
    std::string pattern;
    const std::string operandTypes =
        mach_.is64bit() ? std::string(numIns + numOuts, OT_REG_LONG)
                        : std::string(numIns + numOuts, OT_REG_INT);
 
    std::vector<OperationDAG*> dags;
    OperationDAG* trivialDag = NULL;
    const char operandChar = mach_.is64bit() ? OT_REG_LONG : OT_REG_INT;
    
    if (TDGen::llvmOperationPattern(op, operandChar) != "" ||
        op.dagCount() == 0) {
        trivialDag = createTrivialDAG(op);
        dags.push_back(trivialDag);
    } else {
        const std::vector<OperationDAG*> matchableDAGs =
            getMatchableOperationDAGs(op);
        dags.insert(dags.end(), matchableDAGs.begin(), matchableDAGs.end());
    }
    for (const OperationDAG* dag : dags) {
        pattern = operationPattern(op, *dag, operandTypes);
        o << "def : Pat<(XLenVT ";
        o << transformTCEPattern(pattern, numIns);
        o << ", (" << "OA_" + op.name().upper();
        if (numIns == 3) {
            o << " GPR:$rs1, GPR:$rs2, GPR:$rs3)>;\n";
        } else if (numIns == 2) {
            o << " GPR:$rs1, GPR:$rs2)>;\n";
        } else {
            o << " GPR:$rs1)>;\n";
        }
    }
    if (trivialDag != NULL) {
        delete trivialDag;
    }
}

References TDGen::createTrivialDAG(), Operation::dagCount(), TDGen::getMatchableOperationDAGs(), TTAMachine::Machine::is64bit(), TDGen::llvmOperationPattern(), TDGen::mach_, Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), TDGen::operandChar(), TDGen::operationCanBeMatched(), TDGen::operationPattern(), TDGen::OT_REG_INT, TDGen::OT_REG_LONG, transformTCEPattern(), and TCEString::upper().

Referenced by writePatternDefinitions().

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◆ writePatternDefinitions()

void RISCVTDGen::writePatternDefinitions ( std::ostream & o )

protected

Definition at line 272 of file RISCVTDGen.cc.

                                                 {
    OperationPool opPool;
    // o << "// ---- Instruction pattern defs start ----\n\n";
    for (auto customOp : customOps_) {
        const std::string opName = customOp.first;
        Operation& op = opPool.operation(opName.c_str());
        writePatternDefinition(o, op);
    }
    // o << "// ---- Instruction pattern defs end   ----\n\n";
}

References customOps_, OperationPool::operation(), and writePatternDefinition().

Referenced by initializeBackendContents().

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Member Data Documentation

◆ bem_

BinaryEncoding* RISCVTDGen::bem_

protected

Definition at line 69 of file RISCVTDGen.hh.

Referenced by findCustomOps(), and RISCVTDGen().

◆ customOps_

std::map<std::string, int> RISCVTDGen::customOps_

protected

Definition at line 70 of file RISCVTDGen.hh.

Referenced by findCustomOps(), writeInstructionDeclarations(), and writePatternDefinitions().

◆ declarationStr_

std::string RISCVTDGen::declarationStr_

protected

Definition at line 71 of file RISCVTDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ patternStr_

std::string RISCVTDGen::patternStr_

protected

Definition at line 72 of file RISCVTDGen.hh.

Referenced by generateBackend(), and initializeBackendContents().

The documentation for this class was generated from the following files:

Public Member Functions

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ RISCVTDGen()

◆ ~RISCVTDGen()

Member Function Documentation

◆ decimalsToHex()

◆ dumpClassDefinitions()

◆ findCustomOps()

◆ findFormat()

◆ generateBackend() [1/2]

◆ generateBackend() [2/2]

◆ getFormatType()

◆ initializeBackendContents()

◆ transformTCEPattern()

◆ writeInstructionDeclaration()

◆ writeInstructionDeclarations()

◆ writePatternDefinition()

◆ writePatternDefinitions()

Member Data Documentation

◆ bem_

◆ customOps_

◆ declarationStr_

◆ patternStr_