OpenASIP 2.2
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Classes | Public Member Functions | Static Public Attributes | Protected Types | Protected Member Functions | Static Protected Member Functions | Protected Attributes | Static Protected Attributes | List of all members
TDGen Class Reference

#include <TDGen.hh>

Inheritance diagram for TDGen:
Inheritance graph
Collaboration diagram for TDGen:
Collaboration graph

Classes

struct  RegInfo
 
struct  TerminalDef
 

Public Member Functions

 TDGen (const TTAMachine::Machine &mach, bool initialize=true)
 
virtual ~TDGen ()
 
virtual void generateBackend (const std::string &path) const
 
virtual std::string generateBackend () const
 

Static Public Attributes

static const char OT_REG_BOOL = 'b'
 
static const char OT_REG_INT = 'r'
 
static const char OT_REG_LONG = 's'
 
static const char OT_REG_FP = 'f'
 
static const char OT_REG_HFP = 'h'
 
static const char OT_REG_DOUBLE = 'd'
 
static const char OT_IMM_BOOL = 'j'
 
static const char OT_IMM_INT = 'i'
 
static const char OT_IMM_FP = 'k'
 
static const char OT_IMM_HFP = 'l'
 
static const char OT_IMM_LONG = 'a'
 
static const char OT_VREG_BOOL = 'a'
 
static const char OT_VREG_INT8 = 'q'
 
static const char OT_VREG_INT16 = 't'
 
static const char OT_VREG_INT32 = 'u'
 
static const char OT_VREG_FP = 'e'
 
static const char OT_VREG_HFP = 'g'
 

Protected Types

enum  RegType { GPR = 0 , RESERVED , ARGUMENT , RESULT }
 
enum  RegsToProcess { ALL_REGISTERS , ONLY_EXTRAS , ONLY_LANES , ONLY_NORMAL }
 
typedef std::map< std::string, std::vector< std::string > > RegClassMap
 

Protected Member Functions

bool writeRegisterInfo (std::ostream &o)
 
void writeStartOfRegisterInfo (std::ostream &o)
 
void writeOperandDefs (std::ostream &o)
 
void writeIntegerImmediateDefs (std::ostream &o, const ImmInfo &iivis)
 
void writeMoveImmediateDefs (std::ostream &o)
 
void writeInstrInfo (std::ostream &o)
 
void writeBackendCode (std::ostream &o)
 
void writeTopLevelTD (std::ostream &o)
 
void writeInstrFormats (std::ostream &o)
 
bool checkRequiredRegisters ()
 
void analyzeRegisters ()
 
void analyzeRegisterFileClasses ()
 
void analyzeRegisters (RegsToProcess regsToProcess)
 
void gatherAllMachineOperations ()
 
void analyzeMachineVectorRegisterClasses ()
 
void analyzeMachineRegisters ()
 
void associateRegistersWithVectorRegisterClasses ()
 
void orderEqualWidthRegistersToRoundRobin ()
 
void verbose (const TCEString &msg) const
 
bool isVectorLoadOperation (const Operation &op) const
 
bool isVectorStoreOperation (const Operation &op) const
 
bool isWrongEndianessVectorOp (const Operation &op) const
 
bool isVectorBitwiseOperation (const Operation &op) const
 
bool hasRawOperands (const Operation &op) const
 
int subwordWidthOfRawData (const Operation &op) const
 
bool hasRegisterClassSupport (const Operation &op) const
 
bool hasRegisterClassSupport (const TDGenerator::ValueType &vt) const
 
TCEString associatedVectorRegisterClass (const Operand &operand) const
 
void writePatternReplacement (std::ostream &o, const TCEString &origPat, const TCEString &replacerPat) const
 
void writeOperationDefUsingGivenOperandTypes (std::ostream &o, Operation &op, bool skipPattern, std::vector< TDGenerator::ValueType > inputs, std::vector< TDGenerator::ValueType > outputs, TCEString instrSuffix="")
 
void writeRegisterDef (std::ostream &o, const RegInfo &reg, const std::string regName, const std::string regTemplate, const std::string aliases, RegType type)
 
void write64bitRegisterInfo (std::ostream &o)
 
void write32bitRegisterInfo (std::ostream &o)
 
void write16bitRegisterInfo (std::ostream &o)
 
void write8bitRegisterInfo (std::ostream &o)
 
void write1bitRegisterInfo (std::ostream &o)
 
void writeRARegisterInfo (std::ostream &o)
 
void writeGuardRegisterClassInfo (std::ostream &o)
 
void writeVectorRegisterBaseClasses (std::ostream &o) const
 
void writeVectorRegisterNames (std::ostream &o)
 
void writeVectorRegisterClasses (std::ostream &o) const
 
void writeVectorOperationDefs (std::ostream &o, Operation &op, bool skipPattern)
 
void writeVectorOperationDef (std::ostream &o, Operation &op, TCEString valueTypes, const TCEString &attributes, bool skipPattern)
 
void saveAdditionalVectorOperationInfo (const Operation &op, const TCEString &valueTypes, bool isRegisterOp)
 
void writeVectorMemoryOperationDefs (std::ostream &o, Operation &op, bool skipPattern)
 
void writeVectorBitwiseOperationDefs (std::ostream &o, Operation &op, bool skipPattern)
 
void writeVectorRegisterMoveDefs (std::ostream &o)
 
void writeVectorTruncStoreDefs (std::ostream &o) const
 
void writeScalarToVectorDefs (std::ostream &o) const
 
void writeVectorBitConversions (std::ostream &o) const
 
void writeScalarOperationExploitations (std::ostream &o)
 
void writeVectorLoadStoreOperationExploitations (std::ostream &o)
 
void writeWiderVectorOperationExploitations (std::ostream &o)
 
void genGeneratedTCEPlugin_getStore (std::ostream &o) const
 
void genGeneratedTCEPlugin_getLoad (std::ostream &o) const
 
void genGeneratedTCEPlugin_isVectorRegisterMove (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorValueType (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorBroadcastOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorPackOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorSelectOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorShuffle1Opcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorShuffle2Opcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getConstantVectorShuffleOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getExtractElemOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorShlSameOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorShrSameOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorShruSameOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorAndSameOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorIorSameOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorXorSameOpcode (std::ostream &o) const
 
void genTCETargetLoweringSIMD_addVectorRegisterClasses (std::ostream &o) const
 
void genTCETargetLoweringSIMD_associatedVectorRegClass (std::ostream &o) const
 
void genTCETargetLoweringSIMD_getSetCCResultVT (std::ostream &o) const
 
void genTCEInstrInfoSIMD_copyPhysVectorReg (std::ostream &o) const
 
void genGeneratedTCEPlugin_getVectorImmediateOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getGatherOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getLoadOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getAddOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getShlOpcode (std::ostream &o) const
 
void genGeneratedTCEPlugin_getIorOpcode (std::ostream &o) const
 
void writeVectorImmediateWriteDefs (std::ostream &instrInfoTD)
 
void createMinMaxDef (const TCEString &opName, const TCEString &valueName, std::ostream &os)
 
void createVectorMinMaxDef (const TCEString &opName, int bits, char llvmTypeChar, const TCEString &postFix, std::ostream &os)
 
void writeOperationDefs (std::ostream &o, Operation &op, bool skipPattern)
 
void writeOperationDef (std::ostream &o, Operation &op, const std::string &operandTypes, const std::string &attrs, bool skipPattern, std::string backendPrefix="")
 
std::string emulatingOpNodeLLVMName (const Operation &op, const OperationDAG &dag, const OperationNode &node, const std::string &operandTypes)
 
void writeEmulationPattern (std::ostream &o, const Operation &op, const OperationDAG &dag)
 
void write64bitMoveDefs (std::ostream &o)
 
void writeControlFlowInstrDefs (std::ostream &os)
 
void writeCondBranchDefs (std::ostream &os)
 
void writeCallDef (std::ostream &o)
 
void writeHWLoopDef (std::ostream &o)
 
virtual void writeCallDefRegs (std::ostream &o)
 
void writeRegisterClasses (std::ostream &o)
 
virtual TCEString llvmOperationPattern (const Operation &op, char operandType=' ') const
 
virtual TCEString llvmOperationName (const TCEString &opName) const
 
bool operationCanBeMatched (const Operation &op, std::set< std::string > *recursionCycleCheck=NULL, bool recursionHasStore=false)
 
bool operationDAGCanBeMatched (const OperationDAG &op, std::set< std::string > *recursionCycleCheck=NULL, bool recursionHasStore=false)
 
const OperationDAG * getMatchableOperationDAG (const Operation &op)
 
const std::vector< OperationDAG * > getMatchableOperationDAGs (const Operation &op)
 
std::string tceOperationPattern (const Operation &op)
 
std::string patOutputs (const Operation &op, const std::string &oprTypes)
 
std::string patInputs (const Operation &op, const std::string &oprTypes)
 
virtual std::string operandToString (const Operand &operand, bool match, char operandType, const std::string &immDefName="")
 
std::string operationNodeToString (const Operation &op, const OperationDAG &dag, const OperationNode &node, bool emulationPattern, const std::string &operandTypes)
 
std::string constantNodeString (const Operation &op, const OperationDAG &dag, const ConstantNode &node, const std::string &operandTypes, const OperationDAGNode *successor=nullptr)
 
std::string dagNodeToString (const Operation &op, const OperationDAG &dag, const OperationDAGNode &node, bool emulationPattern, const std::string &operandTypes, const Operation *emulatingOp=nullptr, const OperationDAGNode *successor=nullptr)
 
std::string operationPattern (const Operation &op, const OperationDAG &dag, const std::string &operandTypes)
 
virtual char operandChar (Operand &operand)
 
std::string createDefaultOperandTypeString (const Operation &op)
 
void writeVectorStoreDefs (std::ostream &o, const TCEString &opName, const TCEString &opNameSuffix, bool addrImm, const TCEString &dataType, bool writePredicatedVersions)
 
void genTCEInstrInfo_copyPhys64bitReg (std::ostream &o) const
 
void writeArgRegsArray (std::ostream &os)
 
virtual void createSelectPatterns (std::ostream &os)
 
void writeAddressingModeDefs (std::ostream &o)
 
void createByteExtLoadPatterns (std::ostream &os)
 
void createShortExtLoadPatterns (std::ostream &os)
 
void create32BitExtLoadPatterns (std::ostream &os)
 
void createEndiannesQuery (std::ostream &os)
 
void createConstantMaterializationQuery (std::ostream &os)
 
void createConstShiftPatterns (std::ostream &os)
 
void writeOperationDefs (std::ostream &o, Operation &op, const std::string &operandTypes, const std::string &attrs, bool skipPattern, std::string backendPrefix="")
 
void writeVectorStoreDefs (std::ostream &o, Operation &op, int vectorLen)
 
void writeVectorTruncStoreDefs (std::ostream &o, Operation &op, int bitsize, int vectorLen)
 
void createGetMaxMemoryAlignment (std::ostream &os) const
 
void writeVectorAnyextPattern (std::ostream &o, Operation &op, const TCEString &loadPatternName, int vectorLen)
 
void writeVectorLoadDefs (std::ostream &o, const TCEString &opName, const TCEString &opNameSuffix, bool addrImm, const TCEString &resultType, const TCEString &loadPatternName, bool writePredicatedVersions)
 
virtual void writeImmediateDef (std::ostream &o, const std::string &defName, const std::string &operandType, const std::string &predicate)
 
void writeInstrDef (std::ostream &o, const std::string &instrDefName, const std::string &outs, const std::string &ins, const std::string &asmString, const std::string &pattern)
 
void writeVectorLoadDefs (std::ostream &o, Operation &op, const TCEString &loadPatternName, int vectorLen)
 
void writeBooleanStorePatterns (std::ostream &os)
 
std::string immediatePredicate (int64_t lowerBoundInclusive, uint64_t upperBoundInclusive)
 
std::string immediateOperandNameForEmulatedOperation (const OperationDAG &, const Operand &operand)
 
bool areImmediateOperandsLegal (const Operation &operation, const std::string &operandTypes) const
 
void writeBroadcastDefs (std::ostream &o, Operation &op, int vectorLen)
 
bool writePortGuardedJumpDefPair (std::ostream &os, const TCEString &tceop1, const TCEString &tceop2, bool fp=false)
 
std::string subPattern (const Operation &op, const OperationDAG &dag)
 
OperationDAG * createTrivialDAG (Operation &op)
 
bool canBeImmediate (const OperationDAG &dag, const TerminalNode &node)
 
virtual void createMinMaxGenerator (std::ostream &os)
 
void writeCallSeqStart (std::ostream &os)
 
void writeMiscPatterns (std::ostream &o)
 
void generateLoadStoreCopyGenerator (std::ostream &os)
 
void createParamDRegNums (std::ostream &os)
 
virtual void createVectorRVDRegNums (std::ostream &os)
 
void writeCallingConv (std::ostream &os)
 
void writeCallingConvLicenceText (std::ostream &os)
 
void writeConstShiftPat (std::ostream &os, const TCEString &nodeName, const TCEString &opNameBase, int i)
 
void createBoolAndHalfLoadPatterns (std::ostream &os)
 
virtual void createConstantMaterializationPatterns (std::ostream &os)
 
void createBranchAnalysis (std::ostream &os)
 
void genTCERegisterInfo_setReservedVectorRegs (std::ostream &os) const
 
void writeGetPointerAdjustmentQuery (std::ostream &os) const
 
bool canBePredicated (Operation &op, const std::string &operandTypes)
 
TCEString getLLVMPatternWithConstants (const Operation &op, const std::string &operandTypes, const std::string &operand0, const std::string &operand1) const
 
std::string operandTypesToRegisters (const std::string &opdTypes) const
 
char operandTypeToRegister (const char &opdType) const
 
TCEString getMovePattern (const char &opdType, const std::string &inputPattern) const
 
void initializeBackendContents ()
 

Static Protected Member Functions

static std::vector< std::string > supportedStackAccessOperations (const TTAMachine::Machine &mach)
 

Protected Attributes

std::map< ImmInfoKey, std::string > immOperandDefs_
 Maps (operation, operand) pairs to i32 immediate operand definition names.
 
const TTAMachine::Machine & mach_
 
ImmInfo * immInfo_
 
unsigned dregNum_
 
std::string registerInfo_
 
std::string addressingModeDefs_
 
std::string operandDefs_
 
std::string instrInfo_
 
std::string instrFormats_
 
std::string callingConv_
 
std::string argRegsArray_
 
std::string backendCode_
 
std::string topLevelTD_
 
OperationDAGSelector::OperationSet allOpNames_
 Contains all operation names in upper case.
 
std::map< TCEString, Operation * > scalarOps_
 Contains all scalar operations (<Name, Operation>).
 
std::map< TCEString, Operation * > vectorOps_
 Contains all vector operations (<Name, Operation>).
 
std::map< int, TCEString > baseClasses_
 Contains vector base classes for register files (<Width, Name>).
 
std::map< int, std::vector< TDGenerator::RegisterInfo > > registers_
 Contains registers fit for being vector registers (<Width, Registers>).
 
std::map< TCEString, TDGenerator::RegisterClass > vRegClasses_
 Contains required vector register classes (<ValueType, RegClass>).
 
std::map< TCEString, TDGenerator::InstructionInfo > registerStores_
 All register store operations (<ValueType, InstrInfo>).
 
std::map< TCEString, TDGenerator::InstructionInfo > registerLoads_
 All register load operations (<ValueType, InstrInfo>).
 
std::map< TCEString, TDGenerator::InstructionInfo > immediateStores_
 All immediate store operations (<ValueType, InstrInfo>).
 
std::map< TCEString, TDGenerator::InstructionInfo > immediateLoads_
 All immediate load operations (<ValueType, InstrInfo>).
 
std::map< TCEString, TCEString > packOperations_
 Contains machine's PACK instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > vbcastOperations_
 Contains machine's VBCAST instructions (<ValueType, InstrName>).
 
std::vector< std::pair< const Operation *, TCEString > > truncOperations_
 Contains machine's TRUNCxx/CFH instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > vselectOperations_
 Contains machine's VSELECT instructions (<instrName, ValueType>).
 
std::map< TCEString, TCEString > vshuffle1Operations_
 Contains machine's VSHUFFLE1 instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > vshuffle2Operations_
 Contains machine's VSHUFFLE2 instructions (<ValueType, InstrName>).
 
std::map< std::pair< TCEString, std::vector< int > >, TCEString > vcshuffleOperations_
 Contains machine's VCSHUFFLE instructions (<<ValueType, ConstantSelects>, InstrName>).
 
std::map< TCEString, TCEString > extractElemOperations_
 Contains machine's EXTRACTELEM instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > shlSameOperations_
 Contains machine's SHLSAME instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > shrSameOperations_
 Contains machine's SHRSAME instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > shruSameOperations_
 Contains machine's SHRUSAME instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > andSameOperations_
 Contains machine's ANDSAME instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > iorSameOperations_
 Contains machine's IORSAME instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > xorSameOperations_
 Contains machine's XORSAME instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > gatherOperations_
 Contains machine's GATHER instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > addOperations_
 Contains machine's add instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > shlOperations_
 Contains machine's shl instructions (<ValueType, InstrName>).
 
std::map< TCEString, TCEString > iorOperations_
 Contains machine's shl instructions (<ValueType, InstrName>).
 
std::set< TCEString > movOperations_
 Contains all moves between register classes (<InstrName>).
 
std::vector< RegInfo > regs1bit_
 
std::vector< RegInfo > regs8bit_
 
std::vector< RegInfo > regs16bit_
 
std::vector< RegInfo > regs32bit_
 
std::vector< RegInfo > regs64bit_
 
std::vector< std::string > llvmGuardRegs_
 The LLVM register defs used as guards.
 
std::map< std::string, RegInfo > regs_
 Map of generated llvm register names to physical register in the machine.
 
std::vector< std::string > argRegNames_
 
std::vector< std::string > resRegNames_
 
std::vector< std::string > gprRegNames_
 
std::map< std::string, std::string > opNames_
 
std::map< std::string, std::string > truePredOps_
 
std::map< std::string, std::string > falsePredOps_
 
int maxVectorSize_
 
int highestLaneInt_
 
int highestLaneBool_
 
bool hasExBoolRegs_
 
bool hasExIntRegs_
 
bool hasSelect_
 
bool hasConditionalMoves_
 
int maxScalarWidth_
 
bool littleEndian_
 
unsigned int argRegCount_
 
unsigned int requiredI32Regs_
 Minimum number of 32 bit registers.
 
unsigned int requiredI64Regs_
 
bool prebypassStackIndeces_
 
bool use64bitForFP_
 
std::set< RegInfo > guardedRegs_
 List of register that are associated with a guard on a bus.
 
std::set< const TTAMachine::RegisterFile *, TTAMachine::MachinePart::Comparator > tempRegFiles_
 Register files whose last reg reserved for temp reg copies.
 
RegClassMap regsInClasses_
 All registers in certain group.
 
RegClassMap regsInRFClasses_
 
std::vector< std::string > constantMaterializationPredicates_
 All predicates used in constant materialization patterns.
 

Static Protected Attributes

static const int FP_SUBW_WIDTH
 Float type subword width.
 
static const int HFP_SUBW_WIDTH
 Half float type subword width.
 
static const int BOOL_SUBW_WIDTH
 Bool type subword width.
 
static const int MAX_SCALAR_WIDTH = 64
 Distincts wide vs scalar registers.
 
static const int MAX_SUBW_COUNT = SIMD_WORD_WIDTH / BYTE_BITWIDTH
 Maximum number of subwords that any SIMD operation can have.
 
static const bool EXPLOIT_BIGGER_REGISTERS = true
 If set to true, smaller vector value types can be stored to larger register files, e.g. v4i8 vectors can be stored to registers that are over 32 bits in size.
 
static const std::map< TCEString, TCEString > OPERATION_PATTERNS_
 Contains <BaseOpName, OpPattern> key-value pairs.
 
static const std::string guardRegTemplateName = "Guard"
 

Detailed Description

TCE Backend plugin source code and .td definition generator.

Generates files for building target architecture plugin for LLVM-TCE backend. This version generates the backend files for the "RISC instruction set style" output and provides useful methods.

Definition at line 77 of file TDGen.hh.

Member Typedef Documentation

◆ RegClassMap

typedef std::map<std::string, std::vector<std::string> > TDGen::RegClassMap
protected

Definition at line 643 of file TDGen.hh.

Member Enumeration Documentation

◆ RegsToProcess

enum TDGen::RegsToProcess
protected
Enumerator
ALL_REGISTERS 
ONLY_EXTRAS 
ONLY_LANES 
ONLY_NORMAL 

Definition at line 127 of file TDGen.hh.

127 {
128 ALL_REGISTERS,
129 ONLY_EXTRAS,
130 ONLY_LANES,
131 ONLY_NORMAL
132 };
TDGen::ONLY_LANES
@ ONLY_LANES
Definition TDGen.hh:130
TDGen::ALL_REGISTERS
@ ALL_REGISTERS
Definition TDGen.hh:128
TDGen::ONLY_NORMAL
@ ONLY_NORMAL
Definition TDGen.hh:131
TDGen::ONLY_EXTRAS
@ ONLY_EXTRAS
Definition TDGen.hh:129

◆ RegType

enum TDGen::RegType
protected
Enumerator
GPR 
RESERVED 
ARGUMENT 
RESULT 

Definition at line 97 of file TDGen.hh.

97 {
98 GPR = 0,
99 RESERVED,
100 ARGUMENT,
101 RESULT
102 };
TDGen::RESERVED
@ RESERVED
Definition TDGen.hh:99
TDGen::ARGUMENT
@ ARGUMENT
Definition TDGen.hh:100
TDGen::RESULT
@ RESULT
Definition TDGen.hh:101
TDGen::GPR
@ GPR
Definition TDGen.hh:98

Constructor & Destructor Documentation

◆ TDGen()

TDGen::TDGen ( const TTAMachine::Machine &  mach,
bool  initialize = true 
)

Constructor.

Parameters
machMachine to generate plugin for.

Definition at line 341 of file TDGen.cc.

341 :
342 mach_(mach), immInfo_(NULL), dregNum_(0), maxVectorSize_(0),
343 highestLaneInt_(-1), highestLaneBool_(-1),
344 hasExBoolRegs_(false), hasExIntRegs_(false), hasSelect_(false),
345 littleEndian_(mach.isLittleEndian()),
346 argRegCount_(1),
347 requiredI32Regs_(0), requiredI64Regs_(0), prebypassStackIndeces_(false),
348 use64bitForFP_(false) {
349 // These are TTA-specific, which we don't want to run for other targets
350 if (initialize) {
351 tempRegFiles_ = MachineConnectivityCheck::tempRegisterFiles(mach);
352
353 prebypassStackIndeces_ = false;
354
355 if (mach.is64bit()) {
356 std::set<int> scalarWidths { 1, 32 };
357 hasConditionalMoves_ =
358 MachineConnectivityCheck::hasConditionalMoves(mach_, scalarWidths);
359
360 // TODO: this does not make sense! requires more!
361 requiredI64Regs_ = 0;
362 requiredI64Regs_ += argRegCount_;
363
364 } else {
365 std::set<int> scalarWidths { 1, 32 };
366 hasConditionalMoves_ =
367 MachineConnectivityCheck::hasConditionalMoves(mach_, scalarWidths);
368
369 // TODO: this does not make sense! requires more!
370 requiredI32Regs_ = 0;
371 requiredI32Regs_ += argRegCount_;
372 }
373 immInfo_ = ImmediateAnalyzer::analyze(mach_);
374 maxScalarWidth_ = mach.is64bit() ? 64 : 32;
375 initializeBackendContents();
376 }
377
378}
ImmediateAnalyzer::analyze
static ImmInfo * analyze(const TTAMachine::Machine &mach)
Definition ImmediateAnalyzer.cc:60
MachineConnectivityCheck::tempRegisterFiles
static std::set< const TTAMachine::RegisterFile *, TTAMachine::MachinePart::Comparator > tempRegisterFiles(const TTAMachine::Machine &machine)
Definition MachineConnectivityCheck.cc:1041
MachineConnectivityCheck::hasConditionalMoves
static bool hasConditionalMoves(const TTAMachine::Machine &mach, const std::set< int > &rfWidths)
Definition MachineConnectivityCheck.cc:1879
TDGen::highestLaneBool_
int highestLaneBool_
Definition TDGen.hh:617
TDGen::highestLaneInt_
int highestLaneInt_
Definition TDGen.hh:616
TDGen::hasConditionalMoves_
bool hasConditionalMoves_
Definition TDGen.hh:623
TDGen::use64bitForFP_
bool use64bitForFP_
Definition TDGen.hh:633
TDGen::mach_
const TTAMachine::Machine & mach_
Definition TDGen.hh:463
TDGen::maxVectorSize_
int maxVectorSize_
Definition TDGen.hh:614
TDGen::dregNum_
unsigned dregNum_
Definition TDGen.hh:468
TDGen::immInfo_
ImmInfo * immInfo_
Definition TDGen.hh:465
TDGen::requiredI64Regs_
unsigned int requiredI64Regs_
Definition TDGen.hh:631
TDGen::tempRegFiles_
std::set< const TTAMachine::RegisterFile *, TTAMachine::MachinePart::Comparator > tempRegFiles_
Register files whose last reg reserved for temp reg copies.
Definition TDGen.hh:641
TDGen::argRegCount_
unsigned int argRegCount_
Definition TDGen.hh:628
TDGen::hasSelect_
bool hasSelect_
Definition TDGen.hh:621
TDGen::initializeBackendContents
void initializeBackendContents()
Definition TDGen.cc:394
TDGen::prebypassStackIndeces_
bool prebypassStackIndeces_
Definition TDGen.hh:632
TDGen::requiredI32Regs_
unsigned int requiredI32Regs_
Minimum number of 32 bit registers.
Definition TDGen.hh:630
TDGen::littleEndian_
bool littleEndian_
Definition TDGen.hh:627
TDGen::hasExIntRegs_
bool hasExIntRegs_
Definition TDGen.hh:620
TDGen::hasExBoolRegs_
bool hasExBoolRegs_
Definition TDGen.hh:619
TDGen::maxScalarWidth_
int maxScalarWidth_
Definition TDGen.hh:625
TTAMachine::Machine::isLittleEndian
bool isLittleEndian() const
Definition Machine.hh:258
TTAMachine::Machine::is64bit
bool is64bit() const
Definition Machine.hh:260

References ImmediateAnalyzer::analyze(), argRegCount_, MachineConnectivityCheck::hasConditionalMoves(), hasConditionalMoves_, immInfo_, initializeBackendContents(), TTAMachine::Machine::is64bit(), mach_, maxScalarWidth_, prebypassStackIndeces_, requiredI32Regs_, requiredI64Regs_, tempRegFiles_, and MachineConnectivityCheck::tempRegisterFiles().

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◆ ~TDGen()

TDGen::~TDGen ( )
virtual

Destructor.

Definition at line 383 of file TDGen.cc.

383 {
384 if (immInfo_ != NULL) {
385 delete immInfo_;
386 }
387}

References immInfo_.

Member Function Documentation

◆ analyzeMachineRegisters()

void TDGen::analyzeMachineRegisters ( )
protected

Groups all registers in the machine by register width.

Goes through register files and sorts all real machine registers into <Width, vector<Register>> groups. A base class for each Width is also created.

Todo:
Apparently TDGen does not write information of 8 bit registers -> can't add them.

Definition at line 1478 of file TDGen.cc.

1478 {
1479 const TTAMachine::Machine::RegisterFileNavigator nav =
1480 mach_.registerFileNavigator();
1481 std::map<int, std::vector<RegisterInfo>>::iterator it;
1482
1483 // Go through every register file in the machine.
1484 for (int i = 0; i < nav.count(); i++) {
1485 const TTAMachine::RegisterFile* rf = nav.item(i);
1486 assert(rf != NULL);
1487
1488 // Check that the registerfile has both input and output ports.
1489 bool hasInput = false;
1490 bool hasOutput = false;
1491 for (int p = 0; p < rf->portCount(); p++) {
1492 if (rf->port(p)->isInput()) hasInput = true;
1493 if (rf->port(p)->isOutput()) hasOutput = true;
1494 }
1495
1496 if (!hasInput) {
1497 if (Application::verboseLevel() >
1498 Application::VERBOSE_LEVEL_DEFAULT) {
1499
1500 Application::logStream()
1501 << "Warning: Skipping register file '"
1502 << rf->name()
1503 << "': no input ports."
1504 << std::endl;
1505 }
1506 continue;
1507 }
1508
1509 if (!hasOutput) {
1510 if (Application::verboseLevel() >
1511 Application::VERBOSE_LEVEL_DEFAULT) {
1512 Application::logStream()
1513 << "Warning Skipping register file '"
1514 << rf->name()
1515 << "': no output ports."
1516 << std::endl;
1517 }
1518 continue;
1519 }
1520
1521 int rfWidth = rf->width();
1522
1523 // If there is no entry for the width of the registers, create one.
1524 if (registers_.find(rfWidth) == registers_.end()) {
1525 registers_.insert(
1526 std::make_pair(rfWidth, std::vector<RegisterInfo>()));
1527 }
1528
1529 it = registers_.find(rfWidth);
1530 std::vector<RegisterInfo>& registers = it->second;
1531
1532 // Skip scalar size registers, they have been listed in TDGen.
1533 if (rfWidth > MAX_SCALAR_WIDTH) {
1534 // Kludge fix: Machines with >32 bit regs but without any vector
1535 // operations generates register info td file with 64 bit register
1536 // definition which are not associated to any register class.
1537 // This triggers assertion in LLVM side.
1538 if (vRegClasses_.empty()) continue;
1539
1540 int lastIdx = rf->size();
1541
1542 bool isTempRegRf = AssocTools::containsKey(tempRegFiles_, rf);
1543 if (isTempRegRf) {
1544 // If the machine is not enough connected,
1545 // preserve last register
1546 // of all register files for routing values.
1547 lastIdx--;
1548 }
1549
1550 // Associate register file's registers with the width.
1551 for (int index = 0; index < lastIdx; ++index) {
1552 TCEString regName(
1553 rf->name() + "_" + Conversion::toString(index));
1554 RegisterInfo reg(regName, rf->name(), index, rfWidth);
1555 registers.push_back(reg);
1556 }
1557 }
1558 }
1559
1560 orderEqualWidthRegistersToRoundRobin();
1561
1562 // TDGen has hardcoded register name definitions, some
1563 // inspection needs to be done to create correct register names.
1564
1565 std::vector<RegisterInfo> regs1bit;
1566 for (size_t i = 0; i < regs1bit_.size(); ++i) {
1567 RegisterInfo reg(
1568 "B" + Conversion::toString(i),
1569 regs1bit_[i].rf,
1570 regs1bit_[i].idx,
1571 1);
1572 regs1bit.push_back(reg);
1573 }
1574 registers_[1] = regs1bit;
1575
1576 /// @todo Apparently TDGen does not write information of 8 bit
1577 /// registers -> can't add them.
1578
1579 std::vector<RegisterInfo> regs16bit;
1580 for (size_t i = 0; i < regs16bit_.size(); ++i) {
1581 RegisterInfo reg(
1582 "H" + Conversion::toString(i),
1583 regs16bit_[i].rf,
1584 regs16bit_[i].idx,
1585 16);
1586
1587 if (i == 0) {
1588 reg.regName_ = "HIRES0";
1589 }
1590
1591 regs16bit.push_back(reg);
1592 }
1593 registers_[16] = regs16bit;
1594
1595 std::vector<RegisterInfo> regs32bit;
1596 for (size_t i = 0; i < regs32bit_.size(); ++i) {
1597 RegisterInfo reg(
1598 "I" + Conversion::toString(i),
1599 regs32bit_[i].rf,
1600 regs32bit_[i].idx,
1601 32);
1602
1603
1604 if (!mach_.is64bit()) {
1605 if (i == 0) {
1606 reg.regName_ = "SP";
1607 } else if (i == 1) {
1608 reg.regName_ = "IRES0";
1609 } else if (i == 2) {
1610 reg.regName_ = "FP";
1611 } else if (i == 3) {
1612 reg.regName_ = "KLUDGE_REGISTER";
1613 } else if (i < argRegCount_ + 3) {
1614 reg.regName_ = "A" + Conversion::toString(i);
1615 }
1616 }
1617 regs32bit.push_back(reg);
1618 }
1619 registers_[32] = regs32bit;
1620
1621 std::vector<RegisterInfo> regs64bit;
1622 for (size_t i = 0; i < regs64bit_.size(); ++i) {
1623 RegisterInfo reg(
1624 "L" + Conversion::toString(i),
1625 regs64bit_[i].rf,
1626 regs64bit_[i].idx,
1627 64);
1628
1629 if (mach_.is64bit()) {
1630 if (i == 0) {
1631 reg.regName_ = "SP";
1632 } else if (i == 1) {
1633 reg.regName_ = "IRES0";
1634 } else if (i == 2) {
1635 reg.regName_ = "FP";
1636 } else if (i == 3) {
1637 reg.regName_ = "KLUDGE_REGISTER";
1638 } else if (i < argRegCount_ + 3) {
1639 reg.regName_ = "A" + Conversion::toString(i);
1640 }
1641 }
1642 regs64bit.push_back(reg);
1643 }
1644 registers_[64] = regs64bit;
1645
1646 // Create base classes for different register widths.
1647 for (it = registers_.begin(); it != registers_.end(); ++it) {
1648 int width = it->first;
1649 if (width > MAX_SCALAR_WIDTH) {
1650 baseClasses_.insert(
1651 std::make_pair(width, "VR" + Conversion::toString(width)));
1652 } else {
1653 baseClasses_.insert(
1654 std::make_pair(width, "R" + Conversion::toString(width)));
1655 }
1656 }
1657}
assert
#define assert(condition)
Definition Application.hh:86
Application::VERBOSE_LEVEL_DEFAULT
static const int VERBOSE_LEVEL_DEFAULT
Default verbose level - do not print anything unnecessary.
Definition Application.hh:222
Application::verboseLevel
static int verboseLevel()
Definition Application.hh:176
Application::logStream
static std::ostream & logStream()
Definition Application.cc:155
AssocTools::containsKey
static bool containsKey(const ContainerType &aContainer, const KeyType &aKey)
Conversion::toString
static std::string toString(const T &source)
TDGen::regs32bit_
std::vector< RegInfo > regs32bit_
Definition TDGen.hh:595
TDGen::MAX_SCALAR_WIDTH
static const int MAX_SCALAR_WIDTH
Distincts wide vs scalar registers.
Definition TDGen.hh:486
TDGen::vRegClasses_
std::map< TCEString, TDGenerator::RegisterClass > vRegClasses_
Contains required vector register classes (<ValueType, RegClass>).
Definition TDGen.hh:535
TDGen::regs64bit_
std::vector< RegInfo > regs64bit_
Definition TDGen.hh:597
TDGen::baseClasses_
std::map< int, TCEString > baseClasses_
Contains vector base classes for register files (<Width, Name>).
Definition TDGen.hh:529
TDGen::registers_
std::map< int, std::vector< TDGenerator::RegisterInfo > > registers_
Contains registers fit for being vector registers (<Width, Registers>).
Definition TDGen.hh:532
TDGen::orderEqualWidthRegistersToRoundRobin
void orderEqualWidthRegistersToRoundRobin()
Definition TDGen.cc:1674
TDGen::regs16bit_
std::vector< RegInfo > regs16bit_
Definition TDGen.hh:593
TDGen::regs1bit_
std::vector< RegInfo > regs1bit_
Definition TDGen.hh:589
TTAMachine::BaseRegisterFile::size
virtual int size() const
TTAMachine::BaseRegisterFile::width
virtual int width() const
TTAMachine::BaseRegisterFile::port
virtual RFPort * port(const std::string &name) const
Definition BaseRegisterFile.cc:129
TTAMachine::Component::name
virtual TCEString name() const
Definition MachinePart.cc:125
TTAMachine::Machine::Navigator::item
ComponentType * item(int index) const
TTAMachine::Machine::registerFileNavigator
virtual RegisterFileNavigator registerFileNavigator() const
Definition Machine.cc:450
TTAMachine::Port::isInput
virtual bool isInput() const
Definition Port.cc:298
TTAMachine::Port::isOutput
virtual bool isOutput() const
Definition Port.cc:308
TTAMachine::Unit::portCount
virtual int portCount() const
Definition Unit.cc:135

References argRegCount_, assert, baseClasses_, AssocTools::containsKey(), TTAMachine::Machine::Navigator< ComponentType >::count(), TTAMachine::Machine::is64bit(), TTAMachine::Port::isInput(), TTAMachine::Port::isOutput(), TTAMachine::Machine::Navigator< ComponentType >::item(), Application::logStream(), mach_, MAX_SCALAR_WIDTH, TTAMachine::Component::name(), orderEqualWidthRegistersToRoundRobin(), TTAMachine::BaseRegisterFile::port(), TTAMachine::Unit::portCount(), TTAMachine::Machine::registerFileNavigator(), registers_, TDGenerator::RegisterInfo::regName_, regs16bit_, regs1bit_, regs32bit_, regs64bit_, TTAMachine::BaseRegisterFile::size(), tempRegFiles_, Conversion::toString(), Application::VERBOSE_LEVEL_DEFAULT, Application::verboseLevel(), vRegClasses_, and TTAMachine::BaseRegisterFile::width().

Referenced by writeRegisterInfo().

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◆ analyzeMachineVectorRegisterClasses()

void TDGen::analyzeMachineVectorRegisterClasses ( )
protected

Creates vector register classes required by the machine.

The function goes through all operations and lists all different vector operand value types, after which a register class is created for each vector value type to support the vector value type.

Definition at line 1282 of file TDGen.cc.

1282 {
1283 OperationPool opPool;
1284
1285 // Has all vector value types (e.g. "v4i32", "v16i8", "v2f16", "v8f32")
1286 // that can be found among all the operands present in the machine.
1287 // Register classes will be defined based on these vector value types.
1288 std::set<TCEString> reqRegClassTypes;
1289
1290 // List all existing vector value types in the machine.
1291 OperationDAGSelector::OperationSet::iterator opnIt;
1292 for (opnIt = allOpNames_.begin(); opnIt != allOpNames_.end(); ++opnIt) {
1293 Operation& op = opPool.operation((*opnIt).c_str());
1294
1295 if (&op == &NullOperation::instance()) {
1296 continue;
1297 }
1298
1299 // Go through every operand of the operation.
1300 for (int i = 1; i <= op.operandCount(); ++i) {
1301 Operand& operand = op.operand(i);
1302
1303 // We are only interested in vector operands, skip otherwise.
1304 if (!operand.isVector()) {
1305 continue;
1306 }
1307
1308 TCEString vtStr = ValueType::valueTypeStr(operand);
1309 if (vRegClasses_.find(vtStr) == vRegClasses_.end()) {
1310 reqRegClassTypes.insert(vtStr);
1311 }
1312
1313 // If operand type is "raw" and vector subword width matches
1314 // float or half float width, list it also.
1315 if (operand.type() == Operand::RAW_DATA &&
1316 (operand.elementWidth() == FP_SUBW_WIDTH ||
1317 operand.elementWidth() == HFP_SUBW_WIDTH)) {
1318
1319 ValueType vt(operand);
1320 vt.isFloat_ = true;
1321 const TCEString floatVtStr = vt.valueTypeStr();
1322
1323 if (vRegClasses_.find(floatVtStr) == vRegClasses_.end()) {
1324 reqRegClassTypes.insert(floatVtStr);
1325 }
1326 }
1327 }
1328 }
1329
1330 // Now we have listed all differend vector value types from the machine.
1331 // Create a register class for every LLVM supported vector value type.
1332
1333 std::set<TCEString>::iterator it;
1334 for (it = reqRegClassTypes.begin(); it != reqRegClassTypes.end(); ++it) {
1335 const TCEString& vtStr = *it;
1336 const ValueType vt(vtStr);
1337
1338 if (vt.isSupportedByLLVM()) {
1339 TCEString name = "V" + Conversion::toString(vt.subwCount_);
1340
1341 if ((vt.isFloat_ && vt.subwWidth_ == FP_SUBW_WIDTH) ||
1342 (vt.isFloat_ && vt.subwWidth_ == HFP_SUBW_WIDTH)) {
1343 name += "F";
1344 } else {
1345 name += "I";
1346 }
1347
1348 name += Conversion::toString(vt.subwWidth_) + "Regs";
1349
1350 RegisterClass newRegClass(vt, name);
1351 vRegClasses_.insert(std::make_pair(vtStr, newRegClass));
1352 } else {
1353 verbose("Warning: RegisterClass not created for type: " + vtStr);
1354 }
1355 }
1356}
NullOperation::instance
static NullOperation & instance()
Operand::isVector
virtual bool isVector() const
Definition Operand.cc:268
Operand::type
virtual OperandType type() const
Definition Operand.cc:165
Operand::RAW_DATA
@ RAW_DATA
Definition Operand.hh:65
Operand::elementWidth
virtual int elementWidth() const
Definition Operand.cc:278
OperationPool::operation
Operation & operation(const char *name)
Definition OperationPool.cc:99
Operation::operandCount
virtual int operandCount() const
Definition Operation.cc:212
Operation::operand
virtual Operand & operand(int id) const
Definition Operation.cc:541
TDGen::verbose
void verbose(const TCEString &msg) const
Definition TDGen.cc:1862
TDGen::FP_SUBW_WIDTH
static const int FP_SUBW_WIDTH
Float type subword width.
Definition TDGen.hh:480
TDGen::allOpNames_
OperationDAGSelector::OperationSet allOpNames_
Contains all operation names in upper case.
Definition TDGen.hh:520
TDGen::HFP_SUBW_WIDTH
static const int HFP_SUBW_WIDTH
Half float type subword width.
Definition TDGen.hh:482
TDGenerator::ValueType::valueTypeStr
TCEString valueTypeStr() const
Definition TDGen.cc:8846

References allOpNames_, Operand::elementWidth(), FP_SUBW_WIDTH, HFP_SUBW_WIDTH, NullOperation::instance(), TDGenerator::ValueType::isFloat_, TDGenerator::ValueType::isSupportedByLLVM(), Operand::isVector(), Operation::operand(), Operation::operandCount(), OperationPool::operation(), Operand::RAW_DATA, TDGenerator::ValueType::subwCount_, TDGenerator::ValueType::subwWidth_, Conversion::toString(), Operand::type(), TDGenerator::ValueType::valueTypeStr(), verbose(), and vRegClasses_.

Referenced by writeRegisterInfo().

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◆ analyzeRegisterFileClasses()

void TDGen::analyzeRegisterFileClasses ( )
protected

◆ analyzeRegisters() [1/2]

void TDGen::analyzeRegisters ( )
protected

Iterates through all registers in the machine and adds register information to the register sets.

Definition at line 838 of file TDGen.cc.

838 {
839
840 const TTAMachine::Machine::BusNavigator busNav =
841 mach_.busNavigator();
842
843 // Check which registers have guards and put their info in
844 // guardedRegs_ set.
845 for (int i = 0; i < busNav.count(); i++) {
846 const TTAMachine::Bus& bus = *busNav.item(i);
847 for (int g = 0; g < bus.guardCount(); g++) {
848 const TTAMachine::RegisterGuard* rg =
849 dynamic_cast<const TTAMachine::RegisterGuard*>(bus.guard(g));
850
851 if (rg != NULL) {
852 RegInfo reg = {
853 rg->registerFile()->name(),
854 (unsigned)rg->registerIndex() };
855
856 guardedRegs_.insert(reg);
857 }
858 }
859 }
860
861 const TTAMachine::Machine::RegisterFileNavigator nav =
862 mach_.registerFileNavigator();
863
864 bool regsFound = true;
865 int currentIdx = 0;
866 while (regsFound) {
867 regsFound = false;
868 for (int i = 0; i < nav.count(); i++) {
869 const TTAMachine::RegisterFile* rf = nav.item(i);
870
871 // Skip definition for registers that are marked as 'reserved'
872 if (rf->isReserved()) continue;
873
874 // Skip the 0th index of a register file with zero register flag
875 if (currentIdx == 0 && rf->zeroRegister()) {
876 regsFound = true;
877 continue;
878 }
879
880 // Check that the registerfile has both input and output ports.
881 bool hasInput = false;
882 bool hasOutput = false;
883 for (int p = 0; p < rf->portCount(); p++) {
884 if (rf->port(p)->isInput()) hasInput = true;
885 if (rf->port(p)->isOutput()) hasOutput = true;
886 }
887
888 if (!hasInput) {
889 if (Application::verboseLevel() >
890 Application::VERBOSE_LEVEL_DEFAULT) {
891
892 Application::logStream()
893 << "Warning: Skipping register file '"
894 << rf->name()
895 << "': no input ports."
896 << std::endl;
897 }
898 continue;
899 }
900
901 if (!hasOutput) {
902 if (Application::verboseLevel() >
903 Application::VERBOSE_LEVEL_DEFAULT) {
904
905 Application::logStream()
906 << "Warning Skipping register file '"
907 << rf->name()
908 << "': no output ports."
909 << std::endl;
910 }
911 continue;
912 }
913
914 unsigned width = rf->width();
915 std::vector<RegInfo>* ri = NULL;
916 if (width == 64) ri = &regs64bit_;
917 else if (width == 32) ri = &regs32bit_;
918 //else if (width == 16) ri = &regs16bit_;
919 else if (width == 8) ri = &regs8bit_;
920 else if (width == 1) ri = &regs1bit_;
921 else {
922 continue;
923 }
924
925 int lastIdx = rf->size();
926 // todo: find a good solution to use just one big rf for this.
927
928 bool isTempRegRf = AssocTools::containsKey(tempRegFiles_, rf);
929 if (isTempRegRf) {
930 // If the machine is not enough connected,
931 // preserve last register
932 // of all register files for routing values.
933 lastIdx--;
934 }
935
936 // leave some 32bit regs unallocated for the post pass scheduler's
937 // register renamer
938 if (width == 32) {
939 int renamerRegs = rf->size() * REG_RENAMER_PART / 100;
940 lastIdx -= renamerRegs;
941 }
942
943 if (currentIdx < lastIdx) {
944 RegInfo reg = {rf->name(), (unsigned)currentIdx};
945 if (!(width == 32 &&
946 guardedRegs_.find(reg) != guardedRegs_.end())) {
947 ri->push_back(reg);
948 }
949 regsFound = true;
950 }
951 }
952 currentIdx++;
953 }
954}
REG_RENAMER_PART
static const unsigned REG_RENAMER_PART
Definition TDGen.cc:332
TDGen::guardedRegs_
std::set< RegInfo > guardedRegs_
List of register that are associated with a guard on a bus.
Definition TDGen.hh:636
TDGen::regs8bit_
std::vector< RegInfo > regs8bit_
Definition TDGen.hh:591
TTAMachine::Bus::guard
Guard * guard(int index) const
Definition Bus.cc:456
TTAMachine::Bus::guardCount
int guardCount() const
Definition Bus.cc:441
TTAMachine::Machine::busNavigator
virtual BusNavigator busNavigator() const
Definition Machine.cc:356
TTAMachine::RegisterFile::isReserved
virtual bool isReserved() const
Definition RegisterFile.cc:184
TTAMachine::RegisterFile::zeroRegister
virtual bool zeroRegister() const
Definition RegisterFile.cc:629
TTAMachine::RegisterGuard::registerFile
const RegisterFile * registerFile() const

References TTAMachine::Machine::busNavigator(), AssocTools::containsKey(), TTAMachine::Machine::Navigator< ComponentType >::count(), TTAMachine::Bus::guard(), TTAMachine::Bus::guardCount(), guardedRegs_, TTAMachine::Port::isInput(), TTAMachine::Port::isOutput(), TTAMachine::RegisterFile::isReserved(), TTAMachine::Machine::Navigator< ComponentType >::item(), Application::logStream(), mach_, TTAMachine::Component::name(), TTAMachine::BaseRegisterFile::port(), TTAMachine::Unit::portCount(), REG_RENAMER_PART, TTAMachine::RegisterGuard::registerFile(), TTAMachine::Machine::registerFileNavigator(), TTAMachine::RegisterGuard::registerIndex(), regs1bit_, regs32bit_, regs64bit_, regs8bit_, TTAMachine::BaseRegisterFile::size(), tempRegFiles_, Application::VERBOSE_LEVEL_DEFAULT, Application::verboseLevel(), TTAMachine::BaseRegisterFile::width(), and TTAMachine::RegisterFile::zeroRegister().

Referenced by writeRegisterInfo().

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◆ analyzeRegisters() [2/2]

void TDGen::analyzeRegisters ( RegsToProcess  regsToProcess)
protected

◆ areImmediateOperandsLegal()

bool TDGen::areImmediateOperandsLegal ( const Operation &  operation,
const std::string &  operandTypes 
) const
protected

Checks if the operation can have the specified immediate operands.

Definition at line 7617 of file TDGen.cc.

7619 {
7620
7621 assert(static_cast<int>(operandTypes.size()) >= operation.operandCount());
7622
7623 for (int i = 0 ; i < operation.numberOfInputs(); i++) {
7624 if (operandTypes.at(i + operation.numberOfOutputs()) != OT_IMM_INT) {
7625 continue;
7626 }
7627
7628 const Operand& operand = operation.operand(i+1);
7629
7630 // Kludge fix for ADDri/MEMri operands. LLVM wants some times to select
7631 // store/load instruction, where the address operand is immediate.
7632 // However, the machine may not have capability to directly transport
7633 // immediate to the address operand. Considering the case as illegal
7634 // will reject operation definitions using ADDri/MEMri operands and
7635 // breaks the instruction selection later on. Temporarily accept
7636 // ADDri/MEMri operands until the issue is fixed.
7637 if (operand.isAddress()) {
7638 continue;
7639 }
7640
7641 if (immInfo_->count(operation, operand) == 0) {
7642 for (int swappableWith : operand.swap()) {
7643 const Operand& otherOperand = operation.operand(swappableWith);
7644 if (immInfo_->count(operation, otherOperand)
7645 && operation.name() != "EQ"
7646 && operation.name() != "NE") {
7647 // ^ EQ and NE are not commutative in LLVM
7648 return true;
7649 }
7650 }
7651 return false;
7652 }
7653 }
7654
7655 return true;
7656}
ImmInfo::count
size_t count(const ImmInfoKey &key) const
Definition ImmInfo.hh:87
Operand::isAddress
virtual bool isAddress() const
Definition Operand.cc:328
Operation::name
virtual TCEString name() const
Definition Operation.cc:93
Operation::numberOfInputs
virtual int numberOfInputs() const
Definition Operation.cc:192
Operation::numberOfOutputs
virtual int numberOfOutputs() const
Definition Operation.cc:202
TDGen::OT_IMM_INT
static const char OT_IMM_INT
Definition TDGen.hh:504

References assert, ImmInfo::count(), immInfo_, Operand::isAddress(), Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), Operation::operand(), Operation::operandCount(), OT_IMM_INT, and Operand::swap().

Referenced by writeOperationDef().

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◆ associatedVectorRegisterClass()

TCEString TDGen::associatedVectorRegisterClass ( const Operand &  operand) const
protected

Returns the name of the vector class that supports given operand.

Parameters
operandChecked if any register class supports value type of this.
Returns
Name of the register class that supports operand's value type.

Definition at line 1842 of file TDGen.cc.

1842 {
1843 std::map<TCEString, RegisterClass>::const_iterator it =
1844 vRegClasses_.find(ValueType::valueTypeStr(operand));
1845
1846 if (it == vRegClasses_.end()) {
1847 // Shouldn't get here because any operation whose operands are not
1848 // supported will not get created.
1849 assert(false);
1850 }
1851
1852 const RegisterClass& regClass = it->second;
1853 return regClass.name();
1854}
TDGenerator::RegisterClass::name
TCEString name() const
Definition TDGen.cc:9054

References assert, TDGenerator::RegisterClass::name(), TDGenerator::ValueType::valueTypeStr(), and vRegClasses_.

Referenced by operandToString().

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◆ associateRegistersWithVectorRegisterClasses()

void TDGen::associateRegistersWithVectorRegisterClasses ( )
protected

Attaches proper register groups to register files.

Definition at line 1709 of file TDGen.cc.

1709 {
1710 std::map<TCEString, RegisterClass>::iterator rcIt;
1711 for (rcIt = vRegClasses_.begin(); rcIt != vRegClasses_.end(); ++rcIt) {
1712 RegisterClass& regClass = rcIt->second;
1713
1714 // Go through all register groups (they are in ascending order by
1715 // width -> starts from the smallest width always towards wider ones).
1716 std::map<int, std::vector<RegisterInfo>>::iterator regsIt =
1717 registers_.begin();
1718
1719 bool found = false;
1720 while (!found && regsIt != registers_.end()) {
1721 int regsWidth = regsIt->first;
1722 size_t amountOfRegs = (regsIt->second).size();
1723
1724 // If can find a group of registers which satisfies the
1725 // register class width requirement, choose those registers.
1726 if (regsWidth >= regClass.valueType().width() &&
1727 amountOfRegs > 0) {
1728 const std::vector<RegisterInfo>& regs = regsIt->second;
1729 regClass.addRegisters(regs);
1730 found = true;
1731 }
1732
1733 ++regsIt;
1734 }
1735
1736 // If bigger register exploitation is desired, append all the rest
1737 // of the registers, because there are only wider registers left.
1738 if (EXPLOIT_BIGGER_REGISTERS) {
1739 while (regsIt != registers_.end()) {
1740 const std::vector<RegisterInfo>& biggerRegs = regsIt->second;
1741 regClass.addRegisters(biggerRegs);
1742 ++regsIt;
1743 }
1744 }
1745 }
1746}
TDGen::EXPLOIT_BIGGER_REGISTERS
static const bool EXPLOIT_BIGGER_REGISTERS
If set to true, smaller vector value types can be stored to larger register files,...
Definition TDGen.hh:493
TDGenerator::RegisterClass::valueType
ValueType valueType() const
Definition TDGen.cc:9064
TDGenerator::RegisterClass::addRegisters
void addRegisters(const std::vector< RegisterInfo > &registers)
Definition TDGen.cc:9107
TDGenerator::ValueType::width
int width() const
Definition TDGen.cc:8776

References TDGenerator::RegisterClass::addRegisters(), EXPLOIT_BIGGER_REGISTERS, registers_, TDGenerator::RegisterClass::valueType(), vRegClasses_, and TDGenerator::ValueType::width().

Referenced by writeRegisterInfo().

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◆ canBeImmediate()

bool TDGen::canBeImmediate ( const OperationDAG &  dag,
const TerminalNode &  node 
)
protected

Returns true if the operand corresponding to the given TerminalNode in an OperationDAG can be immediate in the llvm pattern.

Parameters
dagDAG of the whole operation.
nodeTerminalNode corresponding to the operand queried.

Definition at line 6123 of file TDGen.cc.

6124 {
6125
6126 if (dag.inDegree(node) != 0) {
6127 return false;
6128 }
6129
6130 for (int i = 0; i < dag.outDegree(node); i++) {
6131 const OperationDAGEdge& edge = dag.outEdge(node, i);
6132 const OperationDAGNode& dstNode = dag.headNode(edge);
6133 const OperationNode* opNode =
6134 dynamic_cast<const OperationNode*>(&dstNode);
6135
6136 if (opNode == NULL) {
6137 return false;
6138 }
6139 }
6140 return true;
6141}
BoostGraph::headNode
virtual Node & headNode(const Edge &edge) const
BoostGraph::outEdge
virtual Edge & outEdge(const Node &node, const int index) const
BoostGraph::inDegree
virtual int inDegree(const Node &node) const
BoostGraph::outDegree
virtual int outDegree(const Node &node) const

References BoostGraph< GraphNode, GraphEdge >::headNode(), BoostGraph< GraphNode, GraphEdge >::inDegree(), BoostGraph< GraphNode, GraphEdge >::outDegree(), and BoostGraph< GraphNode, GraphEdge >::outEdge().

Referenced by dagNodeToString().

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◆ canBePredicated()

bool TDGen::canBePredicated ( Operation &  op,
const std::string &  operandTypes 
)
protected

Returns true if the instruction can be predicated.

TODO

Definition at line 7665 of file TDGen.cc.

7665 {
7666
7667 // Predicating operands with immediates can currently lead to
7668 // unschedulable code in case there's no bus that has both the
7669 // predicate and the immediate transfer capability. Disable
7670 // generating the predicated versions for immediate operand
7671 // patterns for now.
7672 if (operandTypes.find(OT_IMM_INT) != std::string::npos) return false;
7673
7674 if (hasConditionalMoves_) return true;
7675
7676 return false;
7677}

References hasConditionalMoves_, and OT_IMM_INT.

Referenced by writeOperationDef().

◆ checkRequiredRegisters()

bool TDGen::checkRequiredRegisters ( )
protected

Checks that the target machine has required registers to build a usable plugin.

Returns
True if required registers were found, false if not.

Definition at line 3336 of file TDGen.cc.

3336 {
3337 if (!mach_.is64bit() && regs32bit_.size() < requiredI32Regs_) {
3338 std::string msg =
3339 (boost::format(
3340 "Architecture doesn't meet the minimal requirements.\n"
3341 "Only %d 32-bit general purpose registers found. At least %d\n"
3342 "needed.")
3343 % regs32bit_.size() % requiredI32Regs_)
3344 .str();
3345
3346 if (tempRegFiles_.size() > 0) {
3347 msg += "Your machine is not fully connected, thus one register\n"
3348 "from each register file are reserved for temp moves and\n"
3349 "not used as general purpose registers.";
3350 }
3351
3352 throw InvalidData(__FILE__, __LINE__, __func__, msg);
3353 return false;
3354 }
3355
3356 if (regs64bit_.size() < requiredI64Regs_) {
3357 std::string msg =
3358 (boost::format(
3359 "Architecture doesn't meet the minimal requirements.\n"
3360 "Only %d 64-bit general purpose registers found. At least %d\n"
3361 "needed. ")
3362 % regs64bit_.size() % requiredI64Regs_)
3363 .str();
3364
3365 if (tempRegFiles_.size() > 0) {
3366 msg += "Your machine is not fully connected, thus one register\n"
3367 "from each register file is reserved for temp moves and\n"
3368 "not used as general purpose registers.";
3369 }
3370
3371 throw InvalidData(__FILE__, __LINE__, __func__, msg);
3372 return false;
3373 }
3374
3375 return true;
3376}
__func__
#define __func__
Definition Application.hh:67

References __func__, TTAMachine::Machine::is64bit(), mach_, regs32bit_, regs64bit_, requiredI32Regs_, requiredI64Regs_, and tempRegFiles_.

Referenced by writeRegisterInfo().

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◆ constantNodeString()

std::string TDGen::constantNodeString ( const Operation &  op,
const OperationDAG &  dag,
const ConstantNode &  node,
const std::string &  operandTypes,
const OperationDAGNode *  successor = nullptr 
)
protected

Definition at line 5611 of file TDGen.cc.

5616 {
5617
5618 assert(dag.inDegree(node) == 0);
5619 assert(dag.outDegree(node) == 1 || successor);
5620 const OperationDAGNode& succ = successor ?
5621 *successor : dag.headNode(dag.outEdge(node,0));
5622 const OperationNode* opn = dynamic_cast<const OperationNode*>(&succ);
5623 OperationDAG::NodeSet siblings = dag.predecessors(*opn);
5624 for (OperationDAG::NodeSet::iterator i = siblings.begin();
5625 i!= siblings.end(); i++) {
5626 const TerminalNode* tNode = dynamic_cast<const TerminalNode*>(*i);
5627 if (tNode != NULL) {
5628 const Operand& operand = op.operand(tNode->operandIndex());
5629 assert(operand.isInput());
5630 char operandType =
5631 operandTypes[operand.index()-1 + op.numberOfOutputs()];
5632 // Retrieve largest short immediate for the operand.
5633 switch (operandType) {
5634 case OT_REG_BOOL:
5635 case OT_IMM_BOOL:
5636 return "(i1 " + Conversion::toString(node.value()) + ")";
5637 case OT_REG_DOUBLE:
5638 return "(f64 " + Conversion::toString(node.value()) +")";
5639 case OT_REG_HFP:
5640 return "(f16 " + Conversion::toString(node.value()) + ")";
5641 // TODO: f16 vectors not yet implemented
5642 case OT_REG_FP:
5643 case OT_IMM_FP:
5644 return "(f32 " + Conversion::toString(node.value()) + ")";
5645 case OT_REG_LONG:
5646 case OT_IMM_LONG:
5647 return "(i64 " + Conversion::toString(node.value()) + ")";
5648 case OT_REG_INT:
5649 case OT_IMM_INT:
5650 return mach_.is64bit() ?
5651 "(i64 " + Conversion::toString(node.value()) + ")":
5652 "(i32 " + Conversion::toString(node.value()) + ")";
5653 default:
5654 break;
5655 }
5656 }
5657 }
5658 // TODO: Declaring without type specifier is not valid?
5659 // The constnode would return this if it is the outer most op in the dag
5660 return mach_.is64bit() ?
5661 "(i64 " + Conversion::toString(node.value()) + ")":
5662 "(i32 " + Conversion::toString(node.value()) + ")";
5663}
BoostGraph::predecessors
virtual NodeSet predecessors(const Node &node, bool ignoreBackEdges=false, bool ignoreForwardEdges=false) const
ConstantNode::value
virtual long value() const
Definition ConstantNode.cc:60
GraphBase::NodeSet
std::set< GraphNode *, typename GraphNode::Comparator > NodeSet
Definition Graph.hh:53
Operand::isInput
virtual bool isInput() const
Definition Operand.cc:145
Operand::index
virtual int index() const
Definition Operand.cc:135
TDGen::OT_REG_LONG
static const char OT_REG_LONG
Definition TDGen.hh:499
TDGen::OT_REG_BOOL
static const char OT_REG_BOOL
Definition TDGen.hh:497
TDGen::OT_IMM_LONG
static const char OT_IMM_LONG
Definition TDGen.hh:507
TDGen::OT_REG_FP
static const char OT_REG_FP
Definition TDGen.hh:500
TDGen::OT_REG_HFP
static const char OT_REG_HFP
Definition TDGen.hh:501
TDGen::OT_IMM_FP
static const char OT_IMM_FP
Definition TDGen.hh:505
TDGen::OT_IMM_BOOL
static const char OT_IMM_BOOL
Definition TDGen.hh:503
TDGen::OT_REG_DOUBLE
static const char OT_REG_DOUBLE
Definition TDGen.hh:502
TDGen::OT_REG_INT
static const char OT_REG_INT
Definition TDGen.hh:498
TerminalNode::operandIndex
virtual int operandIndex() const
Definition TerminalNode.cc:60

References assert, BoostGraph< GraphNode, GraphEdge >::headNode(), BoostGraph< GraphNode, GraphEdge >::inDegree(), Operand::index(), TTAMachine::Machine::is64bit(), Operand::isInput(), mach_, Operation::numberOfOutputs(), Operation::operand(), TerminalNode::operandIndex(), OT_IMM_BOOL, OT_IMM_FP, OT_IMM_INT, OT_IMM_LONG, OT_REG_BOOL, OT_REG_DOUBLE, OT_REG_FP, OT_REG_HFP, OT_REG_INT, OT_REG_LONG, BoostGraph< GraphNode, GraphEdge >::outDegree(), BoostGraph< GraphNode, GraphEdge >::outEdge(), BoostGraph< GraphNode, GraphEdge >::predecessors(), Conversion::toString(), and ConstantNode::value().

Referenced by dagNodeToString().

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◆ create32BitExtLoadPatterns()

void TDGen::create32BitExtLoadPatterns ( std::ostream &  os)
protected

Definition at line 6808 of file TDGen.cc.

6808 {
6809 TCEString load = "LD32";
6810 const TCEString uload = "LDU32";
6811 TCEString ZXOP = "ZXW64";
6812 TCEString ZXOPC = "ZXW64ss";
6813
6814 if (mach_.hasOperation(load)) {
6815 if (!mach_.hasOperation(uload)) {
6816 if (!mach_.hasOperation(ZXOP)) {
6817 // emulate zero ext with sing-ext and and
6818 os << "def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), "
6819 << "(AND64ssa (LD32ss ADDRrr:$addr),"
6820 << "0xffffffff)>;" << std::endl;
6821
6822 os << "def : Pat<(i64 (zextloadi32 ADDRri:$addr)), "
6823 << "(AND64ssa (LD32sa ADDRri:$addr),"
6824 << "0xffffffff)>;" << std::endl;
6825 } else {
6826 // use zxw64 instr for zext
6827 os << "def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), "
6828 << "(" << ZXOPC << " (LD32ss ADDRrr:$addr))>;" <<std::endl;
6829
6830 os << "def : Pat<(i64 (zextloadi32 ADDRri:$addr)), "
6831 << "(" << ZXOPC << " (LD32sa ADDRri:$addr))>;" <<std::endl;
6832 }
6833 }
6834 } else {
6835 if (!mach_.hasOperation(uload)) {
6836 std::cerr << "Warning: The architecture is missing any 16-bit loads."
6837 << std::endl;
6838 return;
6839 }
6840 load = uload;
6841
6842 if (mach_.hasOperation("SXW64")) {
6843 // use zextload + sext for sextload
6844 os << "def : Pat<(i64 (sextloadi32 ADDRrr:$addr)), "
6845 << "(SXW64ss (LDU32ss ADDRrr:$addr))>;" << std::endl;
6846
6847 os << "def : Pat<(i64 (sextloadi32 ADDRri:$addr)), "
6848 << "(SXW64ss (LDU32sa ADDRri:$addr))>;" << std::endl;
6849 } else {
6850 std::cerr << "Warning: no sign-extending 32-bit loads or"
6851 << " 32-bit sign extension instruction!"
6852 << " in the processor. All code may not compile!"
6853 << std::endl;
6854 }
6855 }
6856 // anyext.
6857 os << "def : Pat<(i64 (extloadi32 ADDRrr:$src)), "
6858 << "(" << load << "ss ADDRrr:$src)>;" << std::endl
6859
6860 << "def : Pat<(i64 (extloadi32 ADDRri:$src)), "
6861 << "(" << load << "sa ADDRrr:$src)>;" << std::endl;
6862}
TTAMachine::Machine::hasOperation
bool hasOperation(const TCEString &opName) const
Definition Machine.cc:1042

References TTAMachine::Machine::hasOperation(), and mach_.

Referenced by writeInstrInfo().

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◆ createBoolAndHalfLoadPatterns()

void TDGen::createBoolAndHalfLoadPatterns ( std::ostream &  os)
protected

Definition at line 8608 of file TDGen.cc.

8608 {
8609
8610 // TODO: what about true/false versions of these ops?
8611
8612 TCEString load = littleEndian_ ? "LD8" : "LDQ";
8613 TCEString uload = littleEndian_ ? "LDU8" : "LDQU";
8614 TCEString wload = littleEndian_ ?
8615 (mach_.is64bit() ? "LD64" : "LD32") : "LDW";
8616 if (mach_.hasOperation(load)) {
8617 os << "def " << load
8618 << "Br : InstTCE<(outs R1Regs:$op2), (ins MEMrr:$op1), \"\", "
8619 << "[(set R1Regs:$op2, (sextloadi1 ADDRrr:$op1))]>;" << std::endl
8620 << "def " << load
8621 << "Bi : InstTCE<(outs R1Regs:$op2), (ins MEMri:$op1), \"\", "
8622 << "[(set R1Regs:$op2, (sextloadi1 ADDRri:$op1))]>; " << std::endl;
8623
8624 opNames_[load + "Br"] = load;
8625 opNames_[load + "Bi"] = load;
8626
8627 }
8628 if (mach_.hasOperation(uload)) {
8629 os << "def " << uload
8630 << "Br : InstTCE<(outs R1Regs:$op2), (ins MEMrr:$op1), \"\", "
8631 << "[(set R1Regs:$op2, (zextloadi1 ADDRrr:$op1))]>;" << std::endl
8632 << "def " << uload
8633 << "Bi : InstTCE<(outs R1Regs:$op2), (ins MEMri:$op1), \"\", "
8634 << "[(set R1Regs:$op2, (zextloadi1 ADDRri:$op1))]>;" << std::endl;
8635 opNames_[uload + "Br"] = uload;
8636 opNames_[uload + "Bi"] = uload;
8637
8638 os << "def : Pat<(i1 (load ADDRrr:$addr)), ("
8639 << uload << "Br ADDRrr:$addr)>;" << std::endl;
8640 os << "def : Pat<(i1 (load ADDRri:$addr)), ("
8641 << uload << "Bi ADDRri:$addr)>;" << std::endl;
8642 } else {
8643 if (mach_.hasOperation(load)) {
8644 os << "def : Pat<(i1 (load ADDRrr:$addr)), ("
8645 << load << "Br ADDRrr:$addr)>;" << std::endl;
8646 os << "def : Pat<(i1 (load ADDRri:$addr)), ("
8647 << load << "Bi ADDRri:$addr)>;" << std::endl;
8648 }
8649 }
8650
8651 // if no 8-bit loads, create 32/64-bit loads for stack access but
8652 // no patterns for isel as only the stack is 32/64-bit aligned.
8653 // 1- and 8-bit loads on isel will be handled by lowering.
8654 if (!mach_.hasOperation(load) &&
8655 !mach_.hasOperation(uload) &&
8656 mach_.hasOperation(wload)) {
8657 os << "def " << wload
8658 << "Br : InstTCE<(outs R1Regs:$op2), (ins MEMrr:$op1), \"\", "
8659 << "[]>;" << std::endl
8660 << "def " << wload
8661 << "Bi : InstTCE<(outs R1Regs:$op2), (ins MEMri:$op1), \"\", "
8662 << "[]>;" << std::endl;
8663
8664 opNames_[wload + "Br"] = wload;
8665 opNames_[wload + "Bi"] = wload;
8666 }
8667
8668 TCEString halfLoad = littleEndian_ ? "LD16" : "LDH";
8669 if (!mach_.hasOperation(halfLoad)) {
8670 TCEString halfULoad = littleEndian_ ? "LDU16" : "LDHU";
8671 if (mach_.hasOperation(halfULoad)) {
8672 halfLoad = halfULoad;
8673 } else {
8674 return;
8675 }
8676 }
8677
8678 os << "def " << halfLoad << "hr : InstTCE<(outs HFPRegs:$op2), "
8679 << "(ins MEMrr:$op1), \"\", [(set HFPRegs:$op2, "
8680 << "(load ADDRrr:$op1))]>;" << std::endl;
8681
8682 os << "def " << halfLoad << "hi : InstTCE<(outs HFPRegs:$op2), "
8683 << "(ins MEMri:$op1), \"\", [(set HFPRegs:$op2, "
8684 << "(load ADDRri:$op1))]>;" << std::endl;
8685
8686 opNames_[halfLoad + "hr"] = halfLoad;
8687 opNames_[halfLoad + "hi"] = halfLoad;
8688
8689 // TODO: what about 32-bit?
8690}
TDGen::opNames_
std::map< std::string, std::string > opNames_
Definition TDGen.hh:609

References TTAMachine::Machine::hasOperation(), TTAMachine::Machine::is64bit(), littleEndian_, mach_, and opNames_.

Referenced by writeInstrInfo().

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◆ createBranchAnalysis()

void TDGen::createBranchAnalysis ( std::ostream &  os)
protected

Definition at line 7970 of file TDGen.cc.

7970 {
7971 os << "bool GeneratedTCEPlugin::analyzeCCBranch(" << std::endl
7972 << "\tllvm::MachineInstr& i," << std::endl
7973 << "\tllvm::SmallVectorImpl<llvm::MachineOperand>& cond) const {"
7974 << std::endl
7975 << std::endl;
7976
7977 if (!MachineInfo::supportsBoolRegisterGuardedJumps(mach_) &&
7978 MachineInfo::supportsPortGuardedJumps(mach_)) {
7979
7980 os << "\tif (i.getOpcode() == TCE::EQ_JUMP) {" << std::endl
7981 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
7982 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
7983 << "\t\tcond.push_back(MachineOperand::CreateImm(2));"
7984 << std::endl
7985 << "\t\treturn false; }" << std::endl;
7986
7987 os << "\tif (i.getOpcode() == TCE::NE_JUMP) {" << std::endl
7988 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
7989 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
7990 << "\t\tcond.push_back(MachineOperand::CreateImm(3));"
7991 << std::endl
7992 << "\t\treturn false; }" << std::endl;
7993
7994 os << "\tif (i.getOpcode() == TCE::GT_JUMP) {" << std::endl
7995 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
7996 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
7997 << "\t\tcond.push_back(MachineOperand::CreateImm(4));"
7998 << std::endl
7999 << "\t\treturn false; }" << std::endl;
8000
8001 os << "\tif (i.getOpcode() == TCE::LE_JUMP) {" << std::endl
8002 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8003 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8004 << "\t\tcond.push_back(MachineOperand::CreateImm(5));"
8005 << std::endl
8006 << "\t\treturn false; }" << std::endl;
8007
8008 os << "\tif (i.getOpcode() == TCE::GTU_JUMP) {" << std::endl
8009 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8010 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8011 << "\t\tcond.push_back(MachineOperand::CreateImm(6));"
8012 << std::endl
8013 << "\t\treturn false; }" << std::endl;
8014
8015 os << "\tif (i.getOpcode() == TCE::LEU_JUMP) {" << std::endl
8016 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8017 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8018 << "\t\tcond.push_back(MachineOperand::CreateImm(7));"
8019 << std::endl
8020 << "\t\treturn false; }" << std::endl;
8021
8022 if (opNames_.find("EQF_JUMP") != opNames_.end()) {
8023 os << "\tif (i.getOpcode() == TCE::EQF_JUMP) {" << std::endl
8024 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8025 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8026 << "\t\tcond.push_back(MachineOperand::CreateImm(8));"
8027 << std::endl
8028 << "\t\treturn false; }" << std::endl;
8029 }
8030
8031 if (opNames_.find("NEF_JUMP") != opNames_.end()) {
8032 os << "\tif (i.getOpcode() == TCE::NEF_JUMP) {" << std::endl
8033 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8034 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8035 << "\t\tcond.push_back(MachineOperand::CreateImm(9));"
8036 << std::endl
8037 << "\t\treturn false; }" << std::endl;
8038 }
8039
8040 if (opNames_.find("LEF_JUMP") != opNames_.end()) {
8041 os << "\tif (i.getOpcode() == TCE::LEF_JUMP) {" << std::endl
8042 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8043 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8044 << "\t\tcond.push_back(MachineOperand::CreateImm(10));"
8045 << std::endl
8046 << "\t\treturn false; }" << std::endl;
8047 }
8048
8049 if (opNames_.find("GEF_JUMP") != opNames_.end()) {
8050 os << "\tif (i.getOpcode() == TCE::GEF_JUMP) {" << std::endl
8051 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8052 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8053 << "\t\tcond.push_back(MachineOperand::CreateImm(10));"
8054 << std::endl
8055 << "\t\treturn false; }" << std::endl;
8056 }
8057
8058 if (opNames_.find("LTF_JUMP") != opNames_.end()) {
8059 os << "\tif (i.getOpcode() == TCE::LTF_JUMP) {" << std::endl
8060 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8061 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8062 << "\t\tcond.push_back(MachineOperand::CreateImm(12));"
8063 << std::endl
8064 << "\t\treturn false; }" << std::endl;
8065 }
8066
8067 if (opNames_.find("GTF_JUMP") != opNames_.end()) {
8068 os << "\tif (i.getOpcode() == TCE::GTF_JUMP) {" << std::endl
8069 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8070 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8071 << "\t\tcond.push_back(MachineOperand::CreateImm(13));"
8072 << std::endl
8073 << "\t\treturn false; }" << std::endl;
8074 }
8075 }
8076
8077 if (!MachineInfo::supportsBoolRegisterGuardedJumps(mach_) &&
8078 !MachineInfo::supportsPortGuardedJumps(mach_)) {
8079 if (opNames_.count("TCEBREQrr")) {
8080 os << "\tif (i.getOpcode() == TCE::TCEBREQrr) {" << std::endl
8081 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8082 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8083 << "\t\tcond.push_back(MachineOperand::CreateImm(2));"
8084 << std::endl
8085 << "\t\treturn false;" << std::endl
8086 << "\t}" << std::endl;
8087
8088 os << "\tif (i.getOpcode() == TCE::TCEBREQri) {" << std::endl
8089 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8090 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8091 << "\t\tcond.push_back(MachineOperand::CreateImm(102));"
8092 << std::endl
8093 << "\t\treturn false;" << std::endl
8094 << "\t}" << std::endl;
8095 }
8096
8097 if (opNames_.count("TCEBRNErr")) {
8098 os << "\tif (i.getOpcode() == TCE::TCEBRNErr) {" << std::endl
8099 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8100 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8101 << "\t\tcond.push_back(MachineOperand::CreateImm(3));"
8102 << std::endl
8103 << "\t\treturn false;" << std::endl
8104 << "\t}" << std::endl;
8105
8106 os << "\tif (i.getOpcode() == TCE::TCEBRNEri) {" << std::endl
8107 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8108 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8109 << "\t\tcond.push_back(MachineOperand::CreateImm(103));"
8110 << std::endl
8111 << "\t\treturn false;" << std::endl
8112 << "\t}" << std::endl;
8113 }
8114
8115 if (opNames_.count("TCEBRGTrr")) {
8116 os << "\tif (i.getOpcode() == TCE::TCEBRGTrr) {" << std::endl
8117 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8118 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8119 << "\t\tcond.push_back(MachineOperand::CreateImm(4));"
8120 << std::endl
8121 << "\t\treturn false;" << std::endl
8122 << "\t}" << std::endl;
8123
8124 os << "\tif (i.getOpcode() == TCE::TCEBRGTri) {" << std::endl
8125 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8126 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8127 << "\t\tcond.push_back(MachineOperand::CreateImm(104));"
8128 << std::endl
8129 << "\t\treturn false;" << std::endl
8130 << "\t}" << std::endl;
8131 }
8132
8133 if (opNames_.count("TCEBRGTUrr")) {
8134 os << "\tif (i.getOpcode() == TCE::TCEBRGTUrr) {" << std::endl
8135 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8136 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8137 << "\t\tcond.push_back(MachineOperand::CreateImm(6));"
8138 << std::endl
8139 << "\t\treturn false;" << std::endl
8140 << "\t}" << std::endl;
8141
8142 os << "\tif (i.getOpcode() == TCE::TCEBRGTUri) {" << std::endl
8143 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8144 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8145 << "\t\tcond.push_back(MachineOperand::CreateImm(106));"
8146 << std::endl
8147 << "\t\treturn false;" << std::endl
8148 << "\t}" << std::endl;
8149 }
8150
8151 if (opNames_.count("TCEBRLTrr")) {
8152 os << "\tif (i.getOpcode() == TCE::TCEBRLTrr) {" << std::endl
8153 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8154 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8155 << "\t\tcond.push_back(MachineOperand::CreateImm(14));"
8156 << std::endl
8157 << "\t\treturn false;" << std::endl
8158 << "\t}" << std::endl;
8159
8160 os << "\tif (i.getOpcode() == TCE::TCEBRLTri) {" << std::endl
8161 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8162 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8163 << "\t\tcond.push_back(MachineOperand::CreateImm(114));"
8164 << std::endl
8165 << "\t\treturn false;" << std::endl
8166 << "\t}" << std::endl;
8167 }
8168
8169 if (opNames_.count("TCEBRLTUrr")) {
8170 os << "\tif (i.getOpcode() == TCE::TCEBRLTUrr) {" << std::endl
8171 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8172 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8173 << "\t\tcond.push_back(MachineOperand::CreateImm(15));"
8174 << std::endl
8175 << "\t\treturn false;" << std::endl
8176 << "\t}" << std::endl;
8177
8178 os << "\tif (i.getOpcode() == TCE::TCEBRLTUri) {" << std::endl
8179 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8180 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8181 << "\t\tcond.push_back(MachineOperand::CreateImm(115));"
8182 << std::endl
8183 << "\t\treturn false;" << std::endl
8184 << "\t}" << std::endl;
8185 }
8186
8187 if (opNames_.count("TCEBRLErr")) {
8188 os << "\tif (i.getOpcode() == TCE::TCEBRLErr) {" << std::endl
8189 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8190 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8191 << "\t\tcond.push_back(MachineOperand::CreateImm(5));"
8192 << std::endl
8193 << "\t\treturn false;" << std::endl
8194 << "\t}" << std::endl;
8195
8196 os << "\tif (i.getOpcode() == TCE::TCEBRLEri) {" << std::endl
8197 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8198 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8199 << "\t\tcond.push_back(MachineOperand::CreateImm(105));"
8200 << std::endl
8201 << "\t\treturn false;" << std::endl
8202 << "\t}" << std::endl;
8203 }
8204
8205 if (opNames_.count("TCEBRLEUrr")) {
8206 os << "\tif (i.getOpcode() == TCE::TCEBRLEUrr) {" << std::endl
8207 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8208 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8209 << "\t\tcond.push_back(MachineOperand::CreateImm(7));"
8210 << std::endl
8211 << "\t\treturn false;" << std::endl
8212 << "\t}" << std::endl;
8213
8214 os << "\tif (i.getOpcode() == TCE::TCEBRLEUri) {" << std::endl
8215 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8216 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8217 << "\t\tcond.push_back(MachineOperand::CreateImm(107));"
8218 << std::endl
8219 << "\t\treturn false;" << std::endl
8220 << "\t}" << std::endl;
8221 }
8222
8223 if (opNames_.count("TCEBRGErr")) {
8224 os << "\tif (i.getOpcode() == TCE::TCEBRGErr) {" << std::endl
8225 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8226 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8227 << "\t\tcond.push_back(MachineOperand::CreateImm(16));"
8228 << std::endl
8229 << "\t\treturn false;" << std::endl
8230 << "\t}" << std::endl;
8231
8232 os << "\tif (i.getOpcode() == TCE::TCEBRGEri) {" << std::endl
8233 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8234 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8235 << "\t\tcond.push_back(MachineOperand::CreateImm(116));"
8236 << std::endl
8237 << "\t\treturn false;" << std::endl
8238 << "\t}" << std::endl;
8239 }
8240
8241 if (opNames_.count("TCEBRGEUrr")) {
8242 os << "\tif (i.getOpcode() == TCE::TCEBRGEUrr) {" << std::endl
8243 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8244 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8245 << "\t\tcond.push_back(MachineOperand::CreateImm(17));"
8246 << std::endl
8247 << "\t\treturn false;" << std::endl
8248 << "\t}" << std::endl;
8249
8250 os << "\tif (i.getOpcode() == TCE::TCEBRGEUri) {" << std::endl
8251 << "\t\tcond.push_back(i.getOperand(0));" << std::endl
8252 << "\t\tcond.push_back(i.getOperand(1));" << std::endl
8253 << "\t\tcond.push_back(MachineOperand::CreateImm(117));"
8254 << std::endl
8255 << "\t\treturn false;" << std::endl
8256 << "\t}" << std::endl;
8257 }
8258 }
8259 os << "\treturn true;"
8260 << "}" << std::endl << std::endl;
8261
8262 // insert branch
8263
8264 os << "#include <llvm/CodeGen/MachineInstrBuilder.h>" << std::endl
8265 << std::endl;
8266
8267 os << "void TCEInstrInfo::insertCCBranch( " << std::endl
8268 << "\tMachineBasicBlock& mbb," << std::endl
8269 << "\tMachineBasicBlock& tbb," << std::endl
8270 << "\tArrayRef<MachineOperand> cond," << std::endl
8271 << "const DebugLoc& dl) const {" << std::endl
8272 << "\tassert(cond.size() == 3);" << std::endl;
8273
8274 os << "\tint opcode;" << std::endl;
8275
8276 if (!MachineInfo::supportsBoolRegisterGuardedJumps(mach_) &&
8277 MachineInfo::supportsPortGuardedJumps(mach_)) {
8278 os << "\tswitch (cond[2].getImm()) {" << std::endl
8279 << "\t\tcase 2: opcode = TCE::EQ_JUMP;break;" << std::endl
8280 << "\t\tcase 3: opcode = TCE::NE_JUMP;break;" << std::endl
8281 << "\t\tcase 4: opcode = TCE::GT_JUMP;break;" << std::endl
8282 << "\t\tcase 5: opcode = TCE::LE_JUMP;break;" << std::endl
8283 << "\t\tcase 6: opcode = TCE::GTU_JUMP;break;" << std::endl
8284 << "\t\tcase 7: opcode = TCE::LEU_JUMP;break;" << std::endl;
8285
8286 if (opNames_.find("EQF_JUMP") != opNames_.end()) {
8287 os << "\t\tcase 8: opcode = TCE::EQF_JUMP;break;" << std::endl;
8288 }
8289 if (opNames_.find("NEF_JUMP") != opNames_.end()) {
8290 os << "\t\tcase 9: opcode = TCE::NEF_JUMP;break;" << std::endl;
8291 }
8292 if (opNames_.find("LEF_JUMP") != opNames_.end()) {
8293 os << "\t\tcase 10: opcode = TCE::LEF_JUMP;break;" << std::endl;
8294 }
8295 if (opNames_.find("GEF_JUMP") != opNames_.end()) {
8296 os << "\t\tcase 11: opcode = TCE::GEF_JUMP;break;" << std::endl;
8297 }
8298 if (opNames_.find("LTF_JUMP") != opNames_.end()) {
8299 os << "\t\tcase 12: opcode = TCE::LTF_JUMP;break;" << std::endl;
8300 }
8301 if (opNames_.find("GEF_JUMP") != opNames_.end()) {
8302 os << "\t\tcase 13: opcode = TCE::GTF_JUMP;break;" << std::endl;
8303 }
8304
8305 os << "\t\tdefault: assert(false && \"Unknown condition code\");}"
8306 << std::endl;
8307 } else if (!MachineInfo::supportsBoolRegisterGuardedJumps(mach_) &&
8308 !MachineInfo::supportsPortGuardedJumps(mach_)) {
8309 os << "\tswitch (cond[2].getImm()) {" << std::endl;
8310 if (opNames_.count("TCEBREQrr")) {
8311 os << "\t\tcase 2: opcode = TCE::TCEBREQrr; break;" << std::endl
8312 << "\t\tcase 102: opcode = TCE::TCEBREQri; break;"
8313 << std::endl;
8314 }
8315 if (opNames_.count("TCEBRNErr")) {
8316 os << "\t\tcase 3: opcode = TCE::TCEBRNErr; break;" << std::endl
8317 << "\t\tcase 103: opcode = TCE::TCEBRNEri; break;"
8318 << std::endl;
8319 }
8320 if (opNames_.count("TCEBRGTrr")) {
8321 os << "\t\tcase 4: opcode = TCE::TCEBRGTrr; break;" << std::endl
8322 << "\t\tcase 104: opcode = TCE::TCEBRGTri; break;"
8323 << std::endl;
8324 }
8325 if (opNames_.count("TCEBRGTUrr")) {
8326 os << "\t\tcase 6: opcode = TCE::TCEBRGTUrr; break;" << std::endl
8327 << "\t\tcase 106: opcode = TCE::TCEBRGTUri; break;"
8328 << std::endl;
8329 }
8330 if (opNames_.count("TCEBRLTrr")) {
8331 os << "\t\tcase 14: opcode = TCE::TCEBRLTrr; break;" << std::endl
8332 << "\t\tcase 114: opcode = TCE::TCEBRLTri; break;"
8333 << std::endl;
8334 }
8335 if (opNames_.count("TCEBRLTUrr")) {
8336 os << "\t\tcase 15: opcode = TCE::TCEBRLTUrr; break;" << std::endl
8337 << "\t\tcase 115: opcode = TCE::TCEBRLTUri; break;"
8338 << std::endl;
8339 }
8340 if (opNames_.count("TCEBRLErr")) {
8341 os << "\t\tcase 5: opcode = TCE::TCEBRLErr; break;" << std::endl
8342 << "\t\tcase 105: opcode = TCE::TCEBRLEri; break;"
8343 << std::endl;
8344 }
8345 if (opNames_.count("TCEBRLEUrr")) {
8346 os << "\t\tcase 7: opcode = TCE::TCEBRLEUrr; break;" << std::endl
8347 << "\t\tcase 107: opcode = TCE::TCEBRLEUri; break;"
8348 << std::endl;
8349 }
8350 if (opNames_.count("TCEBRGErr")) {
8351 os << "\t\tcase 16: opcode = TCE::TCEBRGErr; break;" << std::endl
8352 << "\t\tcase 116: opcode = TCE::TCEBRGEri; break;"
8353 << std::endl;
8354 }
8355 if (opNames_.count("TCEBRGEUrr")) {
8356 os << "\t\tcase 17: opcode = TCE::TCEBRGEUrr; break;" << std::endl
8357 << "\t\tcase 117: opcode = TCE::TCEBRGEUri; break;"
8358 << std::endl;
8359 }
8360 os << "\t\tdefault: assert(false && \"Unknown condition code\");}"
8361 << std::endl;
8362 } else {
8363 os << "\tassert(false && \"Unknown condition code\");" << std::endl;
8364 }
8365
8366 os << "\tif (cond[1].isReg()) {" << std::endl
8367 << "\t\tBuildMI(&mbb, dl, get(opcode)).addReg(cond[0].getReg())"
8368 << std::endl
8369 << "\t\t .addReg(cond[1].getReg()).addMBB(&tbb);" << std::endl
8370 << "\t} else {" << std::endl
8371 << "\t\tBuildMI(&mbb, dl, get(opcode)).addReg(cond[0].getReg())"
8372 << std::endl
8373 << "\t\t .addImm(cond[1].getImm()).addMBB(&tbb);" << std::endl
8374 << "\t}" << std::endl;
8375 os << "}";
8376}
MachineInfo::supportsPortGuardedJumps
static bool supportsPortGuardedJumps(const TTAMachine::Machine &machine)
Definition MachineInfo.cc:663
MachineInfo::supportsBoolRegisterGuardedJumps
static bool supportsBoolRegisterGuardedJumps(const TTAMachine::Machine &machine)
Definition MachineInfo.cc:616

References mach_, opNames_, MachineInfo::supportsBoolRegisterGuardedJumps(), and MachineInfo::supportsPortGuardedJumps().

Referenced by writeBackendCode().

Here is the call graph for this function:

◆ createByteExtLoadPatterns()

void TDGen::createByteExtLoadPatterns ( std::ostream &  os)
protected

Definition at line 6531 of file TDGen.cc.

6531 {
6532 TCEString load = littleEndian_ ? "LD8" : "LDQ";
6533 TCEString uload = littleEndian_ ? "LDU8" : "LDQU";
6534 TCEString destSize = mach_.is64bit() ? "64" : "32";
6535 int bits = mach_.is64bit() ? 64 : 32;
6536 TCEString ANDIMM = mach_.is64bit() ? "AND64ssa" : "ANDrri";
6537 TCEString ANDREG = mach_.is64bit() ? "AND64sss" : "ANDrrr";
6538 TCEString SUBIMM = mach_.is64bit() ? "SUB64sas" : "SUBrir";
6539 TCEString EXTOP = mach_.is64bit() ? "SXQ64" : "SXQW";
6540 TCEString EXTOPC = mach_.is64bit() ? "SXQ64sr" : "SXQWrr";
6541 TCEString SHL = mach_.is64bit() ? "SHL" : "SHL64";
6542 TCEString SHR = mach_.is64bit() ? "SHR" : "SHR64";
6543 TCEString SHRU = mach_.is64bit() ? "SHRU" : "SHRU64ssa";
6544 TCEString SHLOPC = mach_.is64bit() ? "SHLrri" : "SHL64ssa";
6545 TCEString SHROPC = mach_.is64bit() ? "SHRrri" : "SHR64ssa";
6546 TCEString SHRUOPC = mach_.is64bit() ? "SHRUrri" : "SHRU64ssa";
6547 TCEString SHL4 = mach_.is64bit() ? "SHL4_32" : "SHL4_64";
6548 TCEString SHR4 = mach_.is64bit() ? "SHR4_32" : "SHR4_64";
6549 TCEString SHRU4 = mach_.is64bit() ? "SHRU4_32" : "SHRU4_64ssa";
6550 TCEString regSrcChar = mach_.is64bit() ? OT_REG_LONG : OT_REG_INT;
6551 TCEString dstTypeChar = OT_REG_INT;
6552 TCEString immSrcChar = mach_.is64bit() ? OT_IMM_LONG : OT_IMM_INT;
6553 TCEString loadOpcReg = load + dstTypeChar + regSrcChar;
6554 TCEString loadOpcImm = load + dstTypeChar + immSrcChar;
6555
6556 if (mach_.hasOperation(load)) {
6557 if (!mach_.hasOperation(uload)) {
6558
6559 // emulate zero ext with sing-ext and and
6560 os << "def : Pat<(i" << destSize << " (zextloadi8 ADDRrr:$addr)), "
6561 << "(" << ANDIMM << " ("
6562 << loadOpcReg << " ADDRrr:$addr), 255)>;"
6563 << std::endl;
6564 os << "def : Pat<(i" << destSize << " (zextloadi8 ADDRri:$addr)), "
6565 << "(" << ANDIMM << " ("
6566 << loadOpcImm << " ADDRri:$addr), 255)>;"
6567 << std::endl;
6568 }
6569 } else {
6570 // if no sign ext load, try zero ext load
6571 if (!mach_.hasOperation(uload)) {
6572 std::cerr << "Warning: The architecture is missing any 8-bit loads."
6573 << " All code may not compile!"
6574 << std::endl;
6575 return;
6576 }
6577 loadOpcReg = uload + dstTypeChar + regSrcChar;
6578 loadOpcImm = uload + dstTypeChar + immSrcChar;
6579
6580 if (mach_.hasOperation(EXTOP)) {
6581 // use zextload + sext for sextload
6582 os << "def : Pat<(i" << destSize
6583 << " (sextloadi8 ADDRrr:$addr)), "
6584 << "(" << EXTOPC << " ("
6585 << loadOpcReg << " ADDRrr:$addr))>;" << std::endl;
6586 os << "def : Pat<(i" << destSize
6587 << " (sextloadi8 ADDRri:$addr)), "
6588 << "(" << EXTOPC << " ("
6589 << loadOpcImm << " ADDRri:$addr))>;" << std::endl;
6590
6591 } else {
6592 if (mach_.hasOperation(SHL) && mach_.hasOperation(SHR)) {
6593
6594 int sb = bits -8;
6595 os << "def : Pat<(i" << destSize
6596 << " (sextloadi16 ADDRrr:$addr)), "
6597 << "(" << SHROPC << " (" << SHLOPC << " ("
6598 << load << "rr ADDRrr:$addr), "
6599 << sb << "), " << sb << ")>;" << std::endl;
6600
6601 os << "def : Pat<(i" << destSize
6602 << " (sextloadi16 ADDRri:$addr)), "
6603 << "(" << SHROPC << " (" << SHLOPC << " ("
6604 << load << "ri ADDRri:$addr), "
6605 << sb << "), " << sb << ")>;" << std::endl;
6606 } else if (mach_.hasOperation(SHL4) &&
6607 mach_.hasOperation(SHR4)) {
6608 if (!mach_.is64bit()) {
6609 os << "def : Pat<(i32 (sextloadi8 ADDRrr:$addr)), "
6610 << "(SHR4_32rr (SHR4_32rr (SHR4_32rr (SHR4_32rr "
6611 << "(SHR4_32rr (SHR4_32rr "
6612 << "(SHL4_32rr (SHL4_32rr (SHL4_32rr (SHL4_32rr "
6613 << "(SHL4_32rr (SHL4_32rr ("
6614 << load << "rr ADDRrr:$addr)))))))))))))>;"
6615 << std::endl;
6616
6617 os << "def : Pat<(i32 (sextloadi8 ADDRri:$addr)), "
6618 << "(SHR4_32rr (SHR4_32rr (SHR4_32rr (SHR4_32rr "
6619 << "(SHR4_32rr (SHR4_32rr "
6620 << "(SHL4_32rr (SHL4_32rr (SHL4_32rr (SHL4_32rr "
6621 << "(SHL4_32rr (SHL4_32rr ("
6622 << load << "ri ADDRri:$addr)))))))))))))>;"
6623 << std::endl;
6624 } else {
6625 os << "def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), "
6626 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6627 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6628 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6629 << "(SHR4_64ss (SHR4_64ss "
6630 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6631 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6632 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6633 << "(SHL4_64ss (SHL4_64ss ("
6634 << load << "rr ADDRrr:$addr)))))))))))))>;"
6635 << std::endl;
6636
6637 os << "def : Pat<(i64 (sextloadi8 ADDRri:$addr)), "
6638 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6639 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6640 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6641 << "(SHR4_64ss (SHR4_64ss "
6642 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6643 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6644 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6645 << "(SHL4_64ss (SHL4_64ss ("
6646 << load << "ri ADDRri:$addr)))))))))))))>;"
6647 << std::endl;
6648 }
6649 } else {
6650 std::cerr << "Warning: no sign-extending 8-bit loads,"
6651 << " 8-bit sign extension instruction or suitable"
6652 << " shifts for sext-emulation in the processor."
6653 << " All code may not compile!" << std::endl;
6654 }
6655 }
6656 }
6657
6658 // TODO: is there a more capable version of this code
6659 // commented out above???
6660
6661 os << "def : Pat<(i" << destSize << " (zextloadi1 ADDRrr:$addr)), ("
6662 << loadOpcReg << " ADDRrr:$addr)>;"
6663 << std::endl
6664 << "def : Pat<(i" << destSize << " (zextloadi1 ADDRri:$addr)), ("
6665 << loadOpcImm << " ADDRri:$addr)>;"
6666 << std::endl;
6667
6668 os << "def : Pat<(i" << destSize << " (sextloadi1 ADDRrr:$addr)), "
6669 << "(" << SUBIMM << " 0, "
6670 << "(" << ANDREG << " ("
6671 << loadOpcReg << " ADDRrr:$addr), 1))>;"
6672 << std::endl
6673 << "def : Pat<(i" << destSize << " (sextloadi1 ADDRri:$addr)), "
6674 << "(" << SUBIMM << " 0, "
6675 << "(" << ANDREG << " ("
6676 << loadOpcImm << " ADDRri:$addr), 1))>;"
6677 << std::endl
6678 << "// anyextloads" << std::endl;
6679
6680 os << "def : Pat<(i" << destSize << " (extloadi1 ADDRrr:$src)), ("
6681 << loadOpcReg << " ADDRrr:$src)>;" << std::endl
6682 << "def : Pat<(i" << destSize << " (extloadi1 ADDRri:$src)), ("
6683 << loadOpcImm << " ADDRri:$src)>;" << std::endl
6684 << "def : Pat<(i" << destSize << " (extloadi8 ADDRrr:$src)), ("
6685 << loadOpcReg << " ADDRrr:$src)>;" << std::endl
6686 << "def : Pat<(i" << destSize << " (extloadi8 ADDRri:$src)), ("
6687 << loadOpcImm << " ADDRri:$src)>;" << std::endl
6688 << std::endl;
6689}
SUBIMM
#define SUBIMM
Definition TCEFrameInfo.cc:63

References TTAMachine::Machine::hasOperation(), TTAMachine::Machine::is64bit(), littleEndian_, mach_, OT_IMM_INT, OT_IMM_LONG, OT_REG_INT, OT_REG_LONG, and SUBIMM.

Referenced by writeInstrInfo().

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◆ createConstantMaterializationPatterns()

void TDGen::createConstantMaterializationPatterns ( std::ostream &  os)
protectedvirtual

Generates llvm patterns for constants which are not supported directly as immediates by the target machine.

For example, if a target does not sign extending immediates, a pattern is generated that transforms negative constants C to (SUB 0, -C).

Definition at line 7458 of file TDGen.cc.

7458 {
7459
7460 // TODO: this is used when when not needed!
7461 // creating unnecessary NEG operations!
7462
7463 // LLVM XForm fragments //
7464
7465 // Transformation functions definitions that creates new constants
7466 // from unsupported constants.
7467 os << std::endl << "// Arithmetic negation XForm fragment."
7468 << std::endl << "def aneg_xform : SDNodeXForm<imm, [{"
7469 << std::endl << " return CurDAG->getTargetConstant("
7470 << std::endl << " -(N->getZExtValue()), SDLoc(N), MVT::i32);"
7471 << std::endl << "}]>;"
7472 << std::endl << std::endl;
7473
7474 // Constant select operand definitions //
7475
7476 // Used in Constant materialization patterns to select the constant values
7477 // that are valid for the pattern transformation. The predicate must
7478 // test that the original constant can be accepted by the materialization
7479 // pattern itself and test that the resulted constants by XForms are
7480 // supported too by the target machine.
7481
7482 // Negative constant materialization: C -> NEG(-C) or C -> SUB(0, -C)
7483 // selecting the cheapest.
7484 std::vector<std::string> ops;
7485 if (opNames_.count("NEGri")) ops.push_back("NEG");
7486 if (opNames_.count("SUBrri")) ops.push_back("SUB");
7487 for (auto op : ops) {
7488 // Predicate that accepts the negative constants
7489 std::string predicate = "Imm < 0";
7490 std::pair<int64_t, int64_t> tmp = immInfo_->immediateValueBounds(
7491 ImmInfoKey{op , 1} , 32);
7492 if (tmp.second < 2) continue;
7493
7494 predicate += " && Imm >= -" + Conversion::toString(tmp.second-1);
7495
7496 writeImmediateDef(os, "minus_i32imm", "i32", predicate);
7497 // store predicates for the materialization queries by ISelLowering,
7498 // where decisions to bail unsupported constants to constant pool are
7499 // made. The stored predicates are written to Backend.inc later on.
7500 constantMaterializationPredicates_.push_back(predicate);
7501
7502 os << std::endl << "def : Pat<(i32 minus_i32imm:$imm)," << std::endl;
7503 if (op == "NEG") {
7504 os << " (NEGri (aneg_xform imm:$imm))>;";
7505 } else if (op == "SUB") {
7506 os << " (SUBrri (MOVI32ri 0), (aneg_xform imm:$imm))>;";
7507 }
7508 os << std::endl;
7509 break; // We need only the cheapest materialization pattern.
7510 }
7511}
ImmInfoKey
std::pair< std::string, int > ImmInfoKey
Definition ImmInfo.hh:53
ImmInfo::immediateValueBounds
std::pair< int64_t, int64_t > immediateValueBounds(const ImmInfoKey &key, int destWidth) const
Definition ImmInfo.cc:219
TDGen::constantMaterializationPredicates_
std::vector< std::string > constantMaterializationPredicates_
All predicates used in constant materialization patterns.
Definition TDGen.hh:649
TDGen::writeImmediateDef
virtual void writeImmediateDef(std::ostream &o, const std::string &defName, const std::string &operandType, const std::string &predicate)
Definition TDGen.cc:4610

References constantMaterializationPredicates_, ImmInfo::immediateValueBounds(), immInfo_, opNames_, Conversion::toString(), and writeImmediateDef().

Referenced by writeInstrInfo().

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◆ createConstantMaterializationQuery()

void TDGen::createConstantMaterializationQuery ( std::ostream &  os)
protected

Creates query function for TCEISelLowering for testing if otherwise unsupported constant as immediate can be materialized instead of converting it to constant pool load.

Definition at line 6501 of file TDGen.cc.

6501 {
6502
6503 if (constantMaterializationPredicates_.empty()) {
6504 os << "bool GeneratedTCEPlugin::canMaterializeConstant("
6505 << "const ConstantInt&) const { " << std::endl
6506 << " return false;" << std::endl
6507 << "};" << std::endl;
6508 return;
6509 }
6510
6511 os << "bool GeneratedTCEPlugin::canMaterializeConstant("
6512 << "const ConstantInt& ci) const {"
6513 << std::endl
6514 << " int64_t Imm = ci.getSExtValue();" << std::endl
6515 << " if (";
6516 bool first = true;
6517 for (auto& predicate : constantMaterializationPredicates_) {
6518 if (!first) {
6519 os << std::endl << " || ";
6520 }
6521 os << "(" << predicate << ")";
6522 first = false;
6523 }
6524 os << ") {"
6525 << " return true;" << std::endl
6526 << " }" << std::endl
6527 << " return false;" << std::endl
6528 << "}" << std::endl;
6529}

References constantMaterializationPredicates_.

Referenced by writeBackendCode().

◆ createConstShiftPatterns()

void TDGen::createConstShiftPatterns ( std::ostream &  os)
protected

Definition at line 8599 of file TDGen.cc.

8599 {
8600 int bits = mach_.is64bit() ? 64: 32;
8601 for (int i = 1; i < bits; i++) {
8602 writeConstShiftPat(os, "TCESRAConst", "SHR", i);
8603 writeConstShiftPat(os, "TCESRLConst", "SHRU", i);
8604 writeConstShiftPat(os, "TCESHLConst", "SHL", i);
8605 }
8606}
TDGen::writeConstShiftPat
void writeConstShiftPat(std::ostream &os, const TCEString &nodeName, const TCEString &opNameBase, int i)
Definition TDGen.cc:8577

References TTAMachine::Machine::is64bit(), mach_, and writeConstShiftPat().

Referenced by writeInstrInfo().

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◆ createDefaultOperandTypeString()

std::string TDGen::createDefaultOperandTypeString ( const Operation &  op)
protected

Definition at line 5439 of file TDGen.cc.

5439 {
5440 std::string operandTypes;
5441
5442 int inputs = op.numberOfInputs();
5443 int outputs = op.numberOfOutputs();
5444
5445 for (int i = 0; i < outputs; i++) {
5446 Operand& operand = op.operand(i + inputs +1);
5447 operandTypes += operandChar(operand);
5448 }
5449
5450 for (int i = 0; i < inputs ; i++) {
5451 Operand& operand = op.operand(i +1);
5452 operandTypes += operandChar(operand);
5453 }
5454 return operandTypes;
5455}
TDGen::operandChar
virtual char operandChar(Operand &operand)
Definition TDGen.cc:4755

References Operation::numberOfInputs(), Operation::numberOfOutputs(), Operation::operand(), and operandChar().

Referenced by subPattern(), writeOperationDefs(), and writeOperationDefUsingGivenOperandTypes().

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◆ createEndiannesQuery()

void TDGen::createEndiannesQuery ( std::ostream &  os)
protected

Definition at line 6487 of file TDGen.cc.

6487 {
6488 bool is64bit = mach_.is64bit();
6489 os << "bool GeneratedTCEPlugin::isLittleEndian() const {" << std::endl;
6490 os << "return " << littleEndian_ << "; }" << std::endl;
6491 os << "bool GeneratedTCEPlugin::is64bit() const {" << std::endl;
6492 os << "return " << is64bit << "; }" << std::endl;
6493}

References TTAMachine::Machine::is64bit(), littleEndian_, and mach_.

Referenced by writeBackendCode().

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◆ createGetMaxMemoryAlignment()

void TDGen::createGetMaxMemoryAlignment ( std::ostream &  os) const
protected

Definition at line 7048 of file TDGen.cc.

7048 {
7049 if (mach_.is64bit()) {
7050 os << std::endl
7051 << "unsigned GeneratedTCEPlugin::getMaxMemoryAlignment() const {"
7052 << std::endl
7053 << "\treturn 8;"
7054 << std::endl << "}" << std::endl;
7055 } else {
7056 os << std::endl
7057 << "unsigned GeneratedTCEPlugin::getMaxMemoryAlignment() const {"
7058 << std::endl
7059 << "\treturn 4;"
7060 << std::endl << "}" << std::endl;
7061 }
7062}

References TTAMachine::Machine::is64bit(), and mach_.

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◆ createMinMaxDef()

void TDGen::createMinMaxDef ( const TCEString &  opName,
const TCEString &  valueName,
std::ostream &  os 
)
protected

Definition at line 6370 of file TDGen.cc.

6371 {
6372 if (opNames_.find(opName) != opNames_.end()) {
6373 os << "\tif (vt == MVT::" << valueName << ") return TCE::"
6374 << opName << ";" << std::endl;
6375 }
6376}

References opNames_.

Referenced by createVectorMinMaxDef().

◆ createMinMaxGenerator()

void TDGen::createMinMaxGenerator ( std::ostream &  os)
protectedvirtual

Definition at line 6398 of file TDGen.cc.

6398 {
6399
6400 bool is64bit = mach_.is64bit();
6401 // MIN
6402 os << "int GeneratedTCEPlugin::getMinOpcode(SDNode* n) const {" << std::endl
6403 << "\tEVT vt = n->getOperand(1).getValueType();" << std::endl;
6404 if (!is64bit) {
6405 if (opNames_.find("MINrrr") != opNames_.end()) {
6406 os << "if (vt == MVT::i32) return TCE::MINrrr;" << std::endl;
6407 }
6408 } else {
6409 if (opNames_.find("MIN64sss") != opNames_.end()) {
6410 os << "if (vt == MVT::i64) return TCE::MIN64sss;" << std::endl;
6411 }
6412 }
6413 if (opNames_.find("MINFfff") != opNames_.end()) {
6414 os << "if (vt == MVT::f32) return TCE::MINFfff;" << std::endl;
6415 }
6416
6417 createVectorMinMaxDef("MINH", 16, 'f', "ggg", os);
6418 createVectorMinMaxDef("MINF", 32, 'f', "eee", os);
6419 createVectorMinMaxDef("MIN", 32, 'i', "uuu", os);
6420 createVectorMinMaxDef("MIN", 16, 'i', "ttt", os);
6421
6422 os << "\treturn -1; " << std::endl << "}" << std::endl;
6423
6424 // MAX
6425 os << "int GeneratedTCEPlugin::getMaxOpcode(SDNode* n) const {" << std::endl
6426 << "\tEVT vt = n->getOperand(1).getValueType();" << std::endl;
6427
6428 if (!is64bit) {
6429 if (opNames_.find("MAXrrr") != opNames_.end()) {
6430 os << "if (vt == MVT::i32) return TCE::MAXrrr;" << std::endl;
6431 }
6432 } else {
6433 if (opNames_.find("MAX64sss") != opNames_.end()) {
6434 os << "if (vt == MVT::i64) return TCE::MAX64sss;" << std::endl;
6435 }
6436
6437 }
6438 if (opNames_.find("MAXFfff") != opNames_.end()) {
6439 os << "if (vt == MVT::f32) return TCE::MAXFfff;" << std::endl;
6440 }
6441
6442 createVectorMinMaxDef("MAXH", 16, 'f', "ggg", os);
6443 createVectorMinMaxDef("MAXF", 32, 'f', "eee", os);
6444 createVectorMinMaxDef("MAX", 32, 'i', "uuu", os);
6445 createVectorMinMaxDef("MAX", 16, 'i', "ttt", os);
6446
6447 os << "\treturn -1; " << std::endl << "}" << std::endl;
6448
6449 // MINU
6450 os << "int GeneratedTCEPlugin::getMinuOpcode(SDNode* n) const {" << std::endl;
6451 os << "\tEVT vt = n->getOperand(1).getValueType();" << std::endl;
6452
6453 if (!is64bit) {
6454 if (opNames_.find("MINUrrr") != opNames_.end()) {
6455 os << "if (vt == MVT::i32) return TCE::MINUrrr;" << std::endl;
6456 }
6457 } else {
6458 if (opNames_.find("MINU64sss") != opNames_.end()) {
6459 os << "if (vt == MVT::i64) return TCE::MINU64sss;" << std::endl;
6460 }
6461 }
6462 createVectorMinMaxDef("MINU", 32, 'i', "uuu", os);
6463 createVectorMinMaxDef("MINU", 16, 'i', "ttt", os);
6464
6465 os << "\treturn -1; " << std::endl << "}" << std::endl;
6466
6467 // MAXU
6468 os << "int GeneratedTCEPlugin::getMaxuOpcode(SDNode* n) const {" << std::endl;
6469 os << "\tEVT vt = n->getOperand(1).getValueType();" << std::endl;
6470
6471
6472 if (!is64bit) {
6473 if (opNames_.find("MAXUrrr") != opNames_.end()) {
6474 os << "if (vt == MVT::i32) return TCE::MAXUrrr;" << std::endl;
6475 }
6476 } else {
6477 if (opNames_.find("MAXU64sss") != opNames_.end()) {
6478 os << "if (vt == MVT::i64) return TCE::MAXU64sss;" << std::endl;
6479 }
6480 }
6481
6482 createVectorMinMaxDef("MAXU", 32, 'i', "uuu", os);
6483 createVectorMinMaxDef("MAXU", 16, 'i', "ttt", os);
6484 os << "\treturn -1; " << std::endl << "}" << std::endl;
6485}
TDGen::createVectorMinMaxDef
void createVectorMinMaxDef(const TCEString &opName, int bits, char llvmTypeChar, const TCEString &postFix, std::ostream &os)
Definition TDGen.cc:6380

References createVectorMinMaxDef(), TTAMachine::Machine::is64bit(), mach_, and opNames_.

Referenced by writeBackendCode().

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◆ createParamDRegNums()

void TDGen::createParamDRegNums ( std::ostream &  os)
protected

Definition at line 7010 of file TDGen.cc.

7010 {
7011 os <<
7012 "std::vector<unsigned>" << std::endl <<
7013 "GeneratedTCEPlugin::getParamDRegNums() const {" << std::endl <<
7014 "std::vector<unsigned> res;" << std::endl;
7015 for (unsigned int i = 4; i < argRegCount_ + 3; i++) {
7016 os << "res.push_back(TCE::A" << i << ");" << std::endl;
7017 }
7018 os << "return res;}" << std::endl;
7019}

References argRegCount_.

Referenced by writeBackendCode().

◆ createSelectPatterns()

void TDGen::createSelectPatterns ( std::ostream &  os)
protectedvirtual

Definition at line 7065 of file TDGen.cc.

7065 {
7066 os << "// Creating select patterns. " << std::endl;
7067 if (!hasSelect_) {
7068 os << "// Does not have select instr. " << std::endl;
7069 if (!hasConditionalMoves_) {
7070 std::string NEG = mach_.is64bit() ? "NEG64" : "NEG";
7071 std::string NEGOPC = mach_.is64bit() ? "NEG64ss" : "NEGrr";
7072 std::string gprRegs = mach_.is64bit() ? "R64IRegs" : "R32IRegs";
7073 std::string typeStr = mach_.is64bit() ? "ssa" : "rri";
7074 std::string typeStrInv = mach_.is64bit() ? "sas" : "rir";
7075
7076 const char* sub = mach_.is64bit() ? "SUB64" : "SUB";
7077 const char* iand = mach_.is64bit() ? "AND64" : "AND";
7078 std::string ior = mach_.is64bit() ? "IOR64" : "IOR";
7079 std::string defType = mach_.is64bit() ? "i64" : "i32";
7080 std::string andReg = mach_.is64bit() ? "AND64sss" : "ANDrrr";
7081 std::string iorReg = mach_.is64bit() ? "IOR64sss" : "IORrrr";
7082
7083 std::string iorBool = mach_.is64bit() ? "IOR64bbb" : "IORbbb";
7084 std::string andBool = mach_.is64bit() ? "AND64bbb" : "ANDbbb";
7085 std::string xorBooli = mach_.is64bit() ? "XOR64bbj" : "XORbbj";
7086
7087 bool hasNeg = opNames_.count("NEGrr");
7088
7089 std::string condRC = regs1bit_.empty() ? gprRegs : "R1Regs";
7090 std::string truncOp = regs1bit_.empty() ? std::string(iand) + typeStr : "ANDext";
7091 OperationPool opPool;
7092 std::string truncPattern = regs1bit_.empty()
7093 ? std::string("$c")
7094 : std::string("(") + truncOp + " " + condRC + ":$c" + ", 1)";
7095 std::string falseMask = getLLVMPatternWithConstants(
7096 opPool.operation(sub), typeStr, truncPattern, "1");
7097
7098 std::string trueMask = hasNeg ?
7099 std::string("(" + NEGOPC + " ") + truncPattern +
7100 std::string(")")
7101 : getLLVMPatternWithConstants(
7102 opPool.operation(sub), typeStrInv, "0", truncPattern);
7103
7104 std::string applyTrueMaskOnImm = getLLVMPatternWithConstants(
7105 opPool.operation(iand), typeStr, trueMask, "imm:$t");
7106 std::string applyFalseMaskOnImm = getLLVMPatternWithConstants(
7107 opPool.operation(iand), typeStr, falseMask, "imm:$f");
7108
7109#if 0 // TODO: why is this commented out???
7110 if (mach_.is64bit()) {
7111 os << std::endl
7112 << "def : Pat<(i64 (select R1Regs:$c, R64Regs:$t, R64Regs:$f)), "
7113 << "(IOR64sss (AND64sss R32Regs:$t, (SUB64sas 0, (ANDext R1Regs:$c, 1))),"
7114 << "(AND64sss R32Regs:$f, (SUB64ssa (ANDext R1Regs:$c, 1), 1)))>;"
7115 << std::endl << std::endl
7116
7117 << "def : Pat<(i64 (select R1Regs:$c, (i64 imm:$t),(i64 imm:$f))),"
7118 << "(IOR64sss (AND64ssa (SUB64sas 0, (ANDext R1Regs:$c, 1)), imm:$t),"
7119 << "(AND64ssa (SUB64ssa (ANDext R1Regs:$c, 1), 1), imm:$f))>;"
7120 << std::endl << std::endl
7121
7122 << "def : Pat<(i64 (select R1Regs:$c, R64Regs:$t, (i64 imm:$f))),"
7123 << "(IOR64sss (AND64sss (SUB64sas 0, (ANDext R1Regs:$c, 1)), R32Regs:$t),"
7124 << "(AND64ssa (SUB64ssa (ANDext R1Regs:$c, 1), 1), imm:$f))>;"
7125 << std::endl << std::endl
7126
7127 << "def : Pat<(i64 (select R1Regs:$c, (i64 imm:$t), R64Regs:$f)),"
7128 << "(IOR64sss (AND64ssa (SUB64sas 0, (ANDext R1Regs:$c, 1)), imm:$t),"
7129 << "(AND64sss (SUB64ssa (ANDext R1Regs:$c, 1), 1), R32Regs:$f))>;"
7130 << std::endl << std::endl;
7131
7132 os << std::endl
7133 << "def : Pat<(i64 (select R1Regs:$c, R64Regs:$t, R64Regs:$f)), "
7134 << "(IOR64sss (AND64sss R64Regs:$t, (SUB64sas 0, (ANDext R1Regs:$c, 1))),"
7135 << "(AND64sss R64Regs:$f, (SUB64ssa (ANDext R1Regs:$c, 1), 1)))>;"
7136 << std::endl << std::endl
7137
7138 << "def : Pat<(i64 (select R1Regs:$c, (i64 imm:$t),(i64 imm:$f))),"
7139 << "(IOR64sss (AND64ssa (SUB64sas 0, (ANDext R1Regs:$c, 1)), imm:$t),"
7140 << "(AND64ssa (SUB64ssa (ANDext R1Regs:$c, 1), 1), imm:$f))>;"
7141 << std::endl << std::endl
7142
7143 << "def : Pat<(i64 (select R1Regs:$c, R64Regs:$t, (i64 imm:$f))),"
7144 << "(IOR64sss (AND64sss (SUB64sas 0, (ANDext R1Regs:$c, 1)), R64Regs:$t),"
7145 << "(AND64ssa (SUB64ssa (ANDext R1Regs:$c, 1), 1), imm:$f))>;"
7146 << std::endl << std::endl
7147
7148 << "def : Pat<(i64 (select R1Regs:$c, (i64 imm:$t), R64Regs:$f)),"
7149 << "(IOR64sss (ANDssa (SUB64sas 0, (ANDext R1Regs:$c, 1)), imm:$t),"
7150 << "(ANDsss (SUBssa (ANDext R1Regs:$c, 1), 1), R64Regs:$f))>;"
7151 << std::endl << std::endl
7152
7153 << "def : Pat<(i1 (select R1Regs:$c, R1Regs:$t, R1Regs:$f)),"
7154 << "(IOR64bbb (AND64bbb R1Regs:$c, R1Regs:$t), "
7155 << "(AND64bbb (XOR64bbj R1Regs:$c, 1), R1Regs:$f))>;"
7156 << std::endl << std::endl
7157
7158 << "def : Pat<(i1 (select R1Regs:$c, (i1 0), R1Regs:$f)),"
7159 << "(AND64bbb (XOR64bbj R1Regs:$c, 1), R1Regs:$f)>;"
7160 << std::endl << std::endl
7161
7162 << "def : Pat<(i1 (select R1Regs:$c, R1Regs:$t, (i1 -1))),"
7163 << "(IOR64bbb (AND64bbb R1Regs:$c, R1Regs:$t),"
7164 << "(XOR64bbj R1Regs:$c, 1))>;"
7165 << std::endl << std::endl;
7166 } //else {
7167#endif
7168
7169 if (mach_.is64bit()) {
7170 // optimize select with zero.
7171 os << "def : Pat<(i64 (select "
7172 << condRC << ":$c, R64Regs:$t, (i64 0)))," << std::endl
7173 << " (AND64sss "
7174 << trueMask << ", R64Regs:$t)>;"
7175 << std::endl << std::endl
7176
7177 << "def : Pat<(i64 (select "
7178 << condRC << ":$c, (i64 0), R64Regs:$f))," << std::endl
7179 << "(AND64sss " << falseMask << ", R64Regs:$f)>;"
7180 << std::endl << std::endl;
7181
7182 // also select with zero and some other imm
7183 os << "def : Pat<(i64 (select "
7184 << condRC << ":$c, (i64 imm:$t),(i64 0)))," << std::endl
7185 << " " << applyTrueMaskOnImm << ">;"
7186 << std::endl << std::endl;
7187
7188 os << "def : Pat<(i64 (select "
7189 << condRC << ":$c, (i64 0),(i64 imm:$f)))," << std::endl
7190 << " " << applyFalseMaskOnImm << ">;"
7191 << std::endl << std::endl;
7192 } else {
7193 // optimize select with zero.
7194 os << "def : Pat<(i32 (select "
7195 << condRC << ":$c, R32Regs:$t, (i32 0)))," << std::endl
7196 << " (ANDrrr "
7197 << trueMask << ", R32Regs:$t)>;"
7198 << std::endl << std::endl
7199
7200 << "def : Pat<(i32 (select "
7201 << condRC << ":$c, (i32 0), R32Regs:$f))," << std::endl
7202 << "(ANDrrr " << falseMask << ", R32Regs:$f)>;"
7203 << std::endl << std::endl;
7204
7205 // also select with zero and some other imm
7206 os << "def : Pat<(i32 (select "
7207 << condRC << ":$c, (i32 imm:$t),(i32 0)))," << std::endl
7208 << " " << applyTrueMaskOnImm << ">;"
7209 << std::endl << std::endl;
7210
7211 os << "def : Pat<(i32 (select "
7212 << condRC << ":$c, (i32 0),(i32 imm:$f)))," << std::endl
7213 << " " << applyFalseMaskOnImm << ">;"
7214 << std::endl << std::endl;
7215 }
7216
7217
7218 // TODO: similar patterns could be made with -1, avoiding one AND?
7219
7220 // then the more generic ones
7221 os << std::endl
7222 << "def : Pat<(" << defType << " (select "
7223 << condRC << ":$c, " << gprRegs << ":$t, " << gprRegs << ":$f)), " << std::endl
7224 << " (" << iorReg << " (" << andReg << " " << gprRegs << ":$t, "
7225 << trueMask << "),"
7226 << "(" << andReg << " " << gprRegs << ":$f, " << falseMask << "))>;"
7227 << std::endl << std::endl
7228
7229 << "def : Pat<(" << defType << " (select "
7230 << condRC << ":$c, (" << defType << " imm:$t),(" << defType << " imm:$f)))," << std::endl
7231 << " (" << iorReg << " " << applyTrueMaskOnImm << ","
7232 << applyFalseMaskOnImm << ")>;"
7233 << std::endl << std::endl
7234
7235 << "def : Pat<(" << defType << " (select "
7236 << condRC << ":$c, " << gprRegs << ":$t, (" << defType << " imm:$f)))," << std::endl
7237 << " (" << iorReg << " (" << andReg << " "
7238 << trueMask << ", " << gprRegs << ":$t)," << applyFalseMaskOnImm << ")>;"
7239 << std::endl << std::endl
7240
7241 << "def : Pat<(" << defType << " (select "
7242 << condRC << ":$c, (" << defType << " imm:$t), " << gprRegs << ":$f))," << std::endl
7243 << " (" << iorReg << " " << applyTrueMaskOnImm << ","
7244 << "(" << andReg << " " << falseMask << ", " << gprRegs << ":$f))>;"
7245 << std::endl << std::endl;
7246
7247 if (!regs1bit_.empty()) {
7248 os << "def : Pat<(i1 (select R1Regs:$c, R1Regs:$t, R1Regs:$f)),"
7249 << std::endl
7250 << " (" << iorBool << " (" << andBool << " R1Regs:$c, R1Regs:$t), "
7251 << "(" << andBool << " (" << xorBooli << " R1Regs:$c, 1), R1Regs:$f))>;"
7252 << std::endl << std::endl
7253
7254 << "def : Pat<(i1 (select R1Regs:$c, (i1 0), R1Regs:$f)),"
7255 << std::endl
7256 << " (" << andBool << " (" << xorBooli << " R1Regs:$c, 1), R1Regs:$f)>;"
7257 << std::endl << std::endl
7258
7259 << "def : Pat<(i1 (select R1Regs:$c, R1Regs:$t, (i1 -1))),"
7260 << std::endl
7261 << " (" << iorBool << " (" << andBool << " R1Regs:$c, R1Regs:$t),"
7262 << "(" << xorBooli << " R1Regs:$c, 1))>;"
7263 << std::endl << std::endl;
7264 }
7265
7266 os << "def : Pat<(f32 (select " << condRC << ":$c, "
7267 "FPRegs:$t,FPRegs:$f))," << std::endl
7268 << " (IORfff (ANDfff FPRegs:$t, (SUBfir 0, "
7269 << truncPattern << ")),"
7270 << "(ANDfff FPRegs:$f, (SUBfri "
7271 << truncPattern << ",1)))>;"
7272 << std::endl << std::endl
7273
7274 << "def : Pat<(f16 (select " << condRC << ":$c, "
7275 "R32HFPRegs:$t, R32HFPRegs:$f))," << std::endl
7276 << " (IORhhh (ANDhhh R32HFPRegs:$t, (SUBhir 0, "
7277 << truncPattern << ")),"
7278 << "(ANDhhh R32HFPRegs:$f, (SUBhri "
7279 << truncPattern << ",1)))>;"
7280 << std::endl << std::endl;
7281// }
7282 } else { // has conditional moves.
7283 opNames_["SELECT_I1bb"] = "CMOV_SELECT";
7284 opNames_["SELECT_I1bj"] = "CMOV_SELECT";
7285 opNames_["SELECT_I1jb"] = "CMOV_SELECT";
7286 opNames_["SELECT_I1jj"] = "CMOV_SELECT";
7287 opNames_["SELECT_I32rr"] = "CMOV_SELECT";
7288 opNames_["SELECT_I32ir"] = "CMOV_SELECT";
7289 opNames_["SELECT_I32ri"] = "CMOV_SELECT";
7290 opNames_["SELECT_I32ii"] = "CMOV_SELECT";
7291 opNames_["SELECT_F32"] = "CMOV_SELECT";
7292 opNames_["SELECT_F16"] = "CMOV_SELECT";
7293
7294 // TODO: why does this break??
7295 os << " let isSelect = 1 in {" << std::endl;
7296
7297 if (mach_.is64bit()) {
7298 opNames_["SELECT_I64rr"] = "CMOV_SELECT";
7299 opNames_["SELECT_I64ir"] = "CMOV_SELECT";
7300 opNames_["SELECT_I64ri"] = "CMOV_SELECT";
7301 opNames_["SELECT_I64ii"] = "CMOV_SELECT";
7302 opNames_["SELECT_F64"] = "CMOV_SELECT";
7303
7304
7305
7306 os << "def SELECT_I64rr : InstTCE<(outs R64IRegs:$dst),"
7307 << "(ins R1Regs:$c, R64IRegs:$T, R64IRegs:$F),"
7308 << "\"# SELECT_I64 PSEUDO!\","
7309 << "[(set R64IRegs:$dst,"
7310 << "(select R1Regs:$c, R64IRegs:$T, R64IRegs:$F))]>;"
7311 << std::endl << std::endl
7312
7313 << "def SELECT_I64ri : InstTCE<(outs R64IRegs:$dst),"
7314 << "(ins R64IRegs:$c, R64IRegs:$T, i64imm:$F),"
7315 << "\"# SELECT_I64 PSEUDO!\","
7316 << "[(set R64IRegs:$dst,"
7317 << "(select R64IRegs:$c, R64IRegs:$T, (i64 imm:$F)))]>;"
7318 << std::endl << std::endl
7319
7320 << "def SELECT_I64ir : InstTCE<(outs R64IRegs:$dst),"
7321 << "(ins R64IRegs:$c, i64imm:$T, R64IRegs:$F),"
7322 << "\"# SELECT_I64 PSEUDO!\","
7323 << "[(set R64IRegs:$dst,"
7324 << "(select R64IRegs:$c, (i64 imm:$T), R64IRegs:$F))]>;"
7325 << std::endl << std::endl
7326
7327 << "def SELECT_I64ii : InstTCE<(outs R64IRegs:$dst),"
7328 << "(ins R64IRegs:$c, i64imm:$T, i64imm:$F),"
7329 << "\"# SELECT_I64 PSEUDO!\","
7330 << "[(set R64IRegs:$dst,"
7331 << "(select R64IRegs:$c, (i64 imm:$T), (i64 imm:$F)))]>;"
7332 << std::endl << std::endl
7333
7334 << "def SELECT_F64 : InstTCE<(outs R64DFPRegs:$dst),"
7335 << "(ins R1Regs:$c, R64DFPRegs:$T, R64DFPRegs:$F),"
7336 << "\"# SELECT_F64 PSEUDO!\","
7337 << "[(set R64DFPRegs:$dst,"
7338 << "(select R1Regs:$c, R64DFPRegs:$T, R64DFPRegs:$F))]>;"
7339 << std::endl << std::endl;
7340 }
7341
7342 os << "def SELECT_I1bb : InstTCE<(outs R1Regs:$dst),"
7343 << "(ins GuardRegs:$c, R1Regs:$T, R1Regs:$F),"
7344 << "\"# SELECT_I1 PSEUDO!\","
7345 << " [(set R1Regs:$dst,"
7346 << "(select GuardRegs:$c, R1Regs:$T, R1Regs:$F))]>;"
7347 << std::endl << std::endl
7348
7349 << "def SELECT_I1bj : InstTCE<(outs R1Regs:$dst),"
7350 << " (ins GuardRegs:$c, R1Regs:$T, i1imm:$F),"
7351 << "\"# SELECT_I1 PSEUDO!\","
7352 << "[(set R1Regs:$dst,"
7353 << "(select GuardRegs:$c, R1Regs:$T, (i1 imm:$F)))]>;"
7354 << std::endl << std::endl
7355
7356 << "def SELECT_I1jb : InstTCE<(outs R1Regs:$dst),"
7357 << "(ins GuardRegs:$c, i1imm:$T, R1Regs:$F),"
7358 << "\"# SELECT_I1 PSEUDO!\","
7359 << "[(set R1Regs:$dst,"
7360 << "(select GuardRegs:$c, (i1 imm:$T), R1Regs:$F))]>;"
7361 << std::endl << std::endl
7362
7363 << "def SELECT_I1jj : InstTCE<(outs R1Regs:$dst),"
7364 << "(ins GuardRegs:$c, i1imm:$T, i1imm:$F),"
7365 << "\"# SELECT_I1 PSEUDO!\","
7366 << "[(set R1Regs:$dst,"
7367 << "(select GuardRegs:$c, (i1 imm:$T), (i1 imm:$F)))]>;"
7368 << std::endl << std::endl
7369
7370 << "def SELECT_I32rr : InstTCE<(outs R32IRegs:$dst),"
7371 << "(ins GuardRegs:$c, R32IRegs:$T, R32IRegs:$F),"
7372 << "\"# SELECT_I32 PSEUDO!\","
7373 << "[(set R32IRegs:$dst,"
7374 << "(select GuardRegs:$c, R32IRegs:$T, R32IRegs:$F))]>;"
7375 << std::endl << std::endl
7376// select with the cond in an i32 (produced by expanded vselects with i32 cond vectors)
7377
7378 << "def SELECT_I32ri : InstTCE<(outs R32IRegs:$dst),"
7379 << "(ins R32IRegs:$c, R32IRegs:$T, i32imm:$F),"
7380 << "\"# SELECT_I32 PSEUDO!\","
7381 << "[(set R32IRegs:$dst,"
7382 << "(select R32IRegs:$c, R32IRegs:$T, i32MoveImm:$F))]>;"
7383 << std::endl << std::endl
7384
7385 << "def SELECT_I32ir : InstTCE<(outs R32IRegs:$dst),"
7386 << "(ins R32IRegs:$c, i32imm:$T, R32IRegs:$F),"
7387 << "\"# SELECT_I32 PSEUDO!\","
7388 << "[(set R32IRegs:$dst,"
7389 << "(select R32IRegs:$c, i32MoveImm:$T, R32IRegs:$F))]>;"
7390 << std::endl << std::endl
7391
7392 << "def SELECT_I32ii : InstTCE<(outs R32IRegs:$dst),"
7393 << "(ins R32IRegs:$c, i32imm:$T, i32imm:$F),"
7394 << "\"# SELECT_I32 PSEUDO!\","
7395 << "[(set R32IRegs:$dst,"
7396 << "(select R32IRegs:$c, i32MoveImm:$T, i32MoveImm:$F))]>;"
7397 << std::endl << std::endl
7398
7399 << "def SELECT_F32 : InstTCE<(outs FPRegs:$dst),"
7400 << "(ins GuardRegs:$c, FPRegs:$T, FPRegs:$F),"
7401 << "\"# SELECT_F32 PSEUDO!\","
7402 << "[(set FPRegs:$dst,"
7403 << "(select GuardRegs:$c, FPRegs:$T, FPRegs:$F))]>;"
7404 << std::endl << std::endl
7405
7406 << "def SELECT_F16 : InstTCE<(outs HFPRegs:$dst),"
7407 << "(ins GuardRegs:$c, HFPRegs:$T, HFPRegs:$F),"
7408 << "\"# SELECT_F16 PSEUDO!\","
7409 << "[(set HFPRegs:$dst, "
7410 << "(select GuardRegs:$c, HFPRegs:$T, HFPRegs:$F))]>;"
7411 << std::endl << std::endl;
7412
7413 os << "}" << std::endl << std::endl;
7414
7415 if (mach_.is64bit()) {
7416 os << "def : Pat<(i64 (select R64IRegs:$c, R64IRegs:$T, R64IRegs:$F)),"
7417 << "(SELECT_I64rr (MOVI64I1ss R64Regs:$c),"
7418 << "R64IRegs:$T, R64IRegs:$F)>;"
7419 << std::endl << std::endl;
7420 }
7421
7422 os << "def : Pat<(i32 (select R32IRegs:$c, R32IRegs:$T, R32IRegs:$F)),"
7423 << "(SELECT_I32rr (MOVI32I1rr R32Regs:$c),"
7424 << "R32IRegs:$T, R32IRegs:$F)>;"
7425 << std::endl << std::endl;
7426
7427 }
7428 } else {
7429 os << "// Has select instr!. " << std::endl;
7430 }
7431 std::map<TCEString, RegisterClass>::const_iterator it;
7432 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
7433 const RegisterClass& regClass = it->second;
7434 TCEString regClassName = regClass.name();
7435 ValueType valType = regClass.valueType();
7436 TCEString valTypeName = valType.valueTypeStr();
7437
7438 os << "def SELECT_" << valTypeName << " : InstTCE<(outs "
7439 << regClassName << ":$dst), (ins R1Regs:$c, " << regClassName
7440 << ":$T, " << regClassName << ":$F), \"\","
7441 << "[(set " << regClassName << ":$dst,"
7442 << "(select R1Regs:$c, " << regClassName << ":$T, " << regClassName
7443 << ":$F))]>;" << std::endl
7444 << std::endl;
7445
7446 opNames_["SELECT_" + valTypeName] = "CMOV_SELECT";
7447 }
7448}
sub
#define sub
Definition ConstantTransformer.cc:63
TDGen::getLLVMPatternWithConstants
TCEString getLLVMPatternWithConstants(const Operation &op, const std::string &operandTypes, const std::string &operand0, const std::string &operand1) const
Definition TDGen.cc:7756

References getLLVMPatternWithConstants(), hasConditionalMoves_, hasSelect_, TTAMachine::Machine::is64bit(), mach_, TDGenerator::RegisterClass::name(), OperationPool::operation(), opNames_, regs1bit_, sub, TDGenerator::RegisterClass::valueType(), TDGenerator::ValueType::valueTypeStr(), and vRegClasses_.

Referenced by writeInstrInfo().

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◆ createShortExtLoadPatterns()

void TDGen::createShortExtLoadPatterns ( std::ostream &  os)
protected

Definition at line 6691 of file TDGen.cc.

6691 {
6692 TCEString load = littleEndian_ ? "LD16" : "LDH";
6693 TCEString destSize = mach_.is64bit() ? "64" : "32";
6694 int bits = mach_.is64bit() ? 64 : 32;
6695 TCEString ANDOPC = mach_.is64bit() ? "AND64ssa" : "ANDrri";
6696 TCEString uload = littleEndian_ ? "LDU16" : "LDHU";
6697 TCEString EXTOP = mach_.is64bit() ? "SXH64" : "SXHW";
6698 TCEString EXTOPC = mach_.is64bit() ? "SXH64sr" : "SXHWrr";
6699 TCEString regSrcChar = mach_.is64bit() ? OT_REG_LONG : OT_REG_INT;
6700 TCEString dstTypeChar = OT_REG_INT;
6701 TCEString immSrcChar = mach_.is64bit() ? OT_IMM_LONG : OT_IMM_INT;
6702 TCEString loadOpcReg = load + dstTypeChar + regSrcChar;
6703 TCEString loadOpcImm = load + dstTypeChar + immSrcChar;
6704
6705 TCEString SHL = mach_.is64bit() ? "SHL" : "SHL64";
6706 TCEString SHR = mach_.is64bit() ? "SHR" : "SHR64";
6707 TCEString SHRU = mach_.is64bit() ? "SHRU" : "SHRU64ssa";
6708 TCEString SHLOPC = mach_.is64bit() ? "SHLrri" : "SHL64ssa";
6709 TCEString SHROPC = mach_.is64bit() ? "SHRrri" : "SHR64ssa";
6710 TCEString SHRUOPC = mach_.is64bit() ? "SHRUrri" : "SHRU64ssa";
6711 TCEString SHL4 = mach_.is64bit() ? "SHL4_32" : "SHL4_64";
6712 TCEString SHR4 = mach_.is64bit() ? "SHR4_32" : "SHR4_64";
6713 TCEString SHRU4 = mach_.is64bit() ? "SHRU4_32" : "SHRU4_64ssa";
6714
6715 if (mach_.hasOperation(load)) {
6716 if (!mach_.hasOperation(uload)) {
6717 // emulate zero ext with sing-ext and and
6718 os << "def : Pat<(i" << destSize
6719 << " (zextloadi16 ADDRrr:$addr)), "
6720 << "(" << ANDOPC << " (" << loadOpcReg
6721 << " ADDRrr:$addr), 65535)>;" << std::endl;
6722 os << "def : Pat<(i" << destSize
6723 << " (zextloadi16 ADDRri:$addr)), "
6724 << "(" << ANDOPC << " ("
6725 << loadOpcImm << " ADDRri:$addr), 65535)>;" << std::endl;
6726 }
6727 } else {
6728 if (!mach_.hasOperation(uload)) {
6729 std::cerr << "Warning: The architecture is missing any 16-bit loads."
6730 << std::endl;
6731 return;
6732 }
6733 loadOpcReg = uload + dstTypeChar + regSrcChar;
6734 loadOpcImm = uload + dstTypeChar + immSrcChar;
6735
6736 if (mach_.hasOperation(EXTOP)) {
6737 // use zextload + sext for sextload
6738 os << "def : Pat<(i" << destSize
6739 << " (sextloadi16 ADDRrr:$addr)), "
6740 << "(" << EXTOPC
6741 << " (" << loadOpcReg << " ADDRrr:$addr))>;" << std::endl;
6742 os << "def : Pat<(i" << destSize
6743 << " (sextloadi16 ADDRri:$addr)), "
6744 << "(" << EXTOPC
6745 << " (" << loadOpcImm << " ADDRri:$addr))>;" << std::endl;
6746 } else {
6747 if (mach_.hasOperation(SHL) && mach_.hasOperation(SHR)) {
6748 int sb = bits -16;
6749 os << "def : Pat<(i" << destSize
6750 << " (sextloadi16 ADDRrr:$addr)), "
6751 << "(" << SHROPC << " (" << SHLOPC << " ("
6752 << load << "rr ADDRrr:$addr), "
6753 << sb << "), " << sb << ")>;" << std::endl;
6754
6755 os << "def : Pat<(i" << destSize
6756 << " (sextloadi16 ADDRri:$addr)), "
6757 << "(" << SHROPC << " (" << SHLOPC << " ("
6758 << load << "ri ADDRri:$addr), "
6759 << sb << "), " << sb << ")>;" << std::endl;
6760 } else if (mach_.hasOperation(SHL4) &&
6761 mach_.hasOperation(SHR4)) {
6762 if (!mach_.is64bit()) {
6763 os << "def : Pat<(i32 (sextloadi16 ADDRrr:$addr)), "
6764 << "(SHR4_32rr (SHR4_32rr (SHR4_32rr (SHR4_32rr "
6765 << "(SHL4_32rr (SHL4_32rr (SHL4_32rr (SHL4_32rr ("
6766 << load << "rr ADDRrr:$addr)))))))))>;" << std::endl;
6767
6768 os << "def : Pat<(i32 (sextloadi16 ADDRri:$addr)), "
6769 << "(SHR4_32rr (SHR4_32rr (SHR4_32rr (SHR4_32rr "
6770 << "(SHL4_32rr (SHL4_32rr (SHL4_32rr (SHL4_32rr ("
6771 << load << "ri ADDRri:$addr)))))))))>;" << std::endl;
6772 } else {
6773 os << "def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), "
6774 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6775 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6776 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6777 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6778 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6779 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss ("
6780 << load << "rr ADDRrr:$addr)))))))))))))>;"
6781 << std::endl;
6782
6783 os << "def : Pat<(i64 (sextloadi8 ADDRri:$addr)), "
6784 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6785 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6786 << "(SHR4_64ss (SHR4_64ss (SHR4_64ss (SHR4_64ss "
6787 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6788 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss "
6789 << "(SHL4_64ss (SHL4_64ss (SHL4_64ss (SHL4_64ss ("
6790 << load << "ri ADDRri:$addr)))))))))))))>;"
6791 << std::endl;
6792 }
6793 } else {
6794 std::cerr << "Warning: no sign-extending 16-bit loads,"
6795 << " 16-bit sign extension instruction or suitable"
6796 << " shifts for sext-emulation in the processor."
6797 << " All code may not compile!" << std::endl;
6798 }
6799 }
6800 }
6801 // anyext
6802 os << "def : Pat<(i" << destSize << " (extloadi16 ADDRrr:$src)), ("
6803 << loadOpcReg << " ADDRrr:$src)>;" << std::endl
6804 << "def : Pat<(i" << destSize << " (extloadi16 ADDRri:$src)), ("
6805 << loadOpcImm << " ADDRri:$src)>;" << std::endl;
6806}

References TTAMachine::Machine::hasOperation(), TTAMachine::Machine::is64bit(), littleEndian_, mach_, OT_IMM_INT, OT_IMM_LONG, OT_REG_INT, and OT_REG_LONG.

Referenced by writeInstrInfo().

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◆ createTrivialDAG()

OperationDAG * TDGen::createTrivialDAG ( Operation &  op)
protected

Creates a dummy dag for an OSAL operation.

Parameters
opOperation to create OperationDAG for.
Returns
OperationDAG consisting of only one operation node referencing the given operation.

Definition at line 6093 of file TDGen.cc.

6093 {
6094
6095 OperationDAG* dag = new OperationDAG(op.impl());
6096 OperationNode* opNode = new OperationNode(op);
6097 dag->addNode(*opNode);
6098
6099 for (int i = 0; i < op.numberOfInputs() + op.numberOfOutputs(); i++) {
6100 const Operand& operand = op.operand(i + 1);
6101 TerminalNode* t = new TerminalNode(operand.index());
6102 dag->addNode(*t);
6103 if (operand.isInput()) {
6104 OperationDAGEdge* e = new OperationDAGEdge(1, operand.index());
6105 dag->connectNodes(*t, *opNode, *e);
6106 } else {
6107 OperationDAGEdge* e = new OperationDAGEdge(operand.index(), 1);
6108 dag->connectNodes(*opNode, *t, *e);
6109 }
6110 }
6111 return dag;
6112}
BoostGraph::addNode
virtual void addNode(Node &node)
BoostGraph::connectNodes
virtual void connectNodes(const Node &nTail, const Node &nHead, Edge &e)
Operation::impl
OperationPimpl & impl()
Definition Operation.hh:170

References BoostGraph< GraphNode, GraphEdge >::addNode(), BoostGraph< GraphNode, GraphEdge >::connectNodes(), Operation::impl(), Operand::index(), Operand::isInput(), Operation::numberOfInputs(), Operation::numberOfOutputs(), and Operation::operand().

Referenced by writeOperationDef(), and RISCVTDGen::writePatternDefinition().

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◆ createVectorMinMaxDef()

void TDGen::createVectorMinMaxDef ( const TCEString &  opName,
int  bits,
char  llvmTypeChar,
const TCEString &  postFix,
std::ostream &  os 
)
protected

Definition at line 6380 of file TDGen.cc.

6385 {
6386
6387 for (int elemCount=2; elemCount <= 1024; elemCount<<=1) {
6388 TCEString opName = baseOpName;
6389 opName << bits << "X" << elemCount << postFix;
6390 TCEString vecType = "v";
6391 vecType << elemCount << (TCEString)(llvmTypeChar) << bits;
6392 createMinMaxDef(opName, vecType, os);
6393 }
6394}
TDGen::createMinMaxDef
void createMinMaxDef(const TCEString &opName, const TCEString &valueName, std::ostream &os)
Definition TDGen.cc:6370

References createMinMaxDef().

Referenced by createMinMaxGenerator().

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◆ createVectorRVDRegNums()

void TDGen::createVectorRVDRegNums ( std::ostream &  os)
protectedvirtual

Definition at line 7022 of file TDGen.cc.

7022 {
7023 os <<
7024 "std::vector<unsigned>" << std::endl <<
7025 "GeneratedTCEPlugin::getVectorRVDRegNums() const {" << std::endl <<
7026 "std::vector<unsigned> res;" << std::endl;
7027
7028 std::set<TCEString> processedRegs;
7029 for (auto rcIt : vRegClasses_) {
7030 const RegisterClass& regClass = rcIt.second;
7031
7032 int width = regClass.valueType().width();
7033 if (regClass.numberOfRegisters() > 0) {
7034 const TCEString& name = regClass.registerInfo(0).regName_;
7035 if (processedRegs.find(name) == processedRegs.end() &&
7036 width > maxScalarWidth_) {
7037 processedRegs.insert(name);
7038
7039 os << "res.push_back(TCE::" << name << ");" << std::endl;
7040 }
7041 }
7042 }
7043 os << "return res;}" << std::endl;
7044}
TDGenerator::RegisterClass::registerInfo
RegisterInfo registerInfo(int index) const
Definition TDGen.cc:9084
TDGenerator::RegisterClass::numberOfRegisters
size_t numberOfRegisters() const
Definition TDGen.cc:9097
TDGenerator::RegisterInfo::regName_
TCEString regName_
Register name in GenRegisterInfo.td, e.g. "KLUDGE_REGISTER".
Definition TDGen.hh:669

References maxScalarWidth_, TDGenerator::RegisterClass::numberOfRegisters(), TDGenerator::RegisterClass::registerInfo(), TDGenerator::RegisterInfo::regName_, TDGenerator::RegisterClass::valueType(), vRegClasses_, and TDGenerator::ValueType::width().

Referenced by writeBackendCode().

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◆ dagNodeToString()

std::string TDGen::dagNodeToString ( const Operation &  op,
const OperationDAG &  dag,
const OperationDAGNode &  node,
bool  emulationPattern,
const std::string &  operandTypes,
const Operation *  emulatingOp = nullptr,
const OperationDAGNode *  successor = nullptr 
)
protected

Converts single OperationDAG node to llvm pattern fragment string.

Parameters
opOperation that the whole DAG is for.
dagWhole operation DAG.
nodeDAG node to return string for.
immOpIndex of an operand to define as an immediate or 0 if none.
emulationPatternTrue, if the returned string should be in emulation pattern format.
Returns
DAG node as a llvm .td string.

Definition at line 5506 of file TDGen.cc.

5509 {
5510 const OperationNode* oNode = dynamic_cast<const OperationNode*>(&node);
5511 if (oNode != NULL) {
5512 assert(
5513 dag.inDegree(*oNode) ==
5514 oNode->referencedOperation().numberOfInputs());
5515
5516 return operationNodeToString(
5517 op, dag, *oNode, emulationPattern, operandTypes);
5518 }
5519
5520 const TerminalNode* tNode = dynamic_cast<const TerminalNode*>(&node);
5521 if (tNode != NULL) {
5522 const Operand& operand = op.operand(tNode->operandIndex());
5523 if (dag.inDegree(*tNode) == 0) {
5524 // Input operand for the whole operation.
5525 assert(operand.isInput());
5526
5527 char operandType =
5528 operandTypes[operand.index()-1 + op.numberOfOutputs()];
5529 bool imm = (operandType == OT_IMM_INT ||
5530 operandType == OT_IMM_BOOL);
5531
5532 if (imm && !canBeImmediate(dag, *tNode)) {
5533 std::string msg =
5534 "Invalid immediate operand for " + op.name() +
5535 " operand #" + Conversion::toString(tNode->operandIndex());
5536 throw InvalidData(__FILE__, __LINE__, __func__, msg);
5537 }
5538
5539 if (emulationPattern) {
5540 assert(emulatingOp != nullptr);
5541 return operandToString(operand, false, operandType,
5542 immOperandDefs_[ImmInfo::key(
5543 *emulatingOp, operand)]);
5544 } else {
5545 return operandToString(operand, false, operandType,
5546 immOperandDefs_[ImmInfo::key(op, operand)]);
5547 }
5548 } else {
5549 // Output operand for the whole operation.
5550 assert(dag.inDegree(*tNode) == 1);
5551 assert(op.operand(tNode->operandIndex()).isOutput());
5552 assert(operand.isOutput());
5553 int globalOperandIndex =
5554 tNode->operandIndex() - op.numberOfInputs();
5555 assert(globalOperandIndex == 1);
5556
5557 const OperationDAGEdge& edge = dag.inEdge(node, 0);
5558 const OperationDAGNode& srcNode = dag.tailNode(edge);
5559
5560 // Multiple-output operation nodes not supported in the middle
5561 // of dag:
5562 assert(dag.outDegree(srcNode) == 1);
5563
5564 std::string dnString =
5565 dagNodeToString(
5566 op, dag, srcNode, emulationPattern, operandTypes,
5567 emulatingOp, successor);
5568
5569 bool needTrunc = (operandTypes[globalOperandIndex-1] ==
5570 OT_REG_BOOL &&
5571 operandTypes[1] != OT_REG_BOOL &&
5572 operandTypes[1] != OT_IMM_BOOL);
5573
5574 // handle setcc's without trunc
5575 // also loads and extends.
5576 if (needTrunc) {
5577 if (dnString.substr(0,4) == "(set" ||
5578 dnString.substr(0,5) == "(zext" ||
5579 dnString.substr(0,5) == "(load") {
5580 needTrunc = false;
5581 }
5582 }
5583
5584 if (needTrunc) {
5585 std::string pattern =
5586 "(set " + operandToString(
5587 operand, emulationPattern, operandTypes[0])
5588 + ", (trunc " + dnString + "))";
5589 return pattern;
5590 } else {
5591 std::string pattern =
5592 "(set " + operandToString(
5593 operand, emulationPattern, operandTypes[0])
5594 + ", " + dnString + ")";
5595 return pattern;
5596 }
5597 }
5598 }
5599
5600 // Constant values.
5601 const ConstantNode* cNode = dynamic_cast<const ConstantNode*>(&node);
5602 if (cNode != NULL) {
5603 return constantNodeString(op, dag, *cNode, operandTypes, successor);
5604 }
5605
5606 abortWithError("Unknown OperationDAG node type.");
5607 return "";
5608}
abortWithError
#define abortWithError(message)
Definition Application.hh:72
BoostGraph::inEdge
virtual Edge & inEdge(const Node &node, const int index) const
BoostGraph::tailNode
virtual Node & tailNode(const Edge &edge) const
ImmInfo::key
static ImmInfoKey key(const Operation &operation, int inputOperandId)
Definition ImmInfo.cc:57
Operand::isOutput
virtual bool isOutput() const
Definition Operand.cc:155
OperationNode::referencedOperation
Operation & referencedOperation() const
Definition OperationNode.cc:70
TDGen::operationNodeToString
std::string operationNodeToString(const Operation &op, const OperationDAG &dag, const OperationNode &node, bool emulationPattern, const std::string &operandTypes)
Definition TDGen.cc:5785
TDGen::canBeImmediate
bool canBeImmediate(const OperationDAG &dag, const TerminalNode &node)
Definition TDGen.cc:6123
TDGen::dagNodeToString
std::string dagNodeToString(const Operation &op, const OperationDAG &dag, const OperationDAGNode &node, bool emulationPattern, const std::string &operandTypes, const Operation *emulatingOp=nullptr, const OperationDAGNode *successor=nullptr)
Definition TDGen.cc:5506
TDGen::immOperandDefs_
std::map< ImmInfoKey, std::string > immOperandDefs_
Maps (operation, operand) pairs to i32 immediate operand definition names.
Definition TDGen.hh:436
TDGen::constantNodeString
std::string constantNodeString(const Operation &op, const OperationDAG &dag, const ConstantNode &node, const std::string &operandTypes, const OperationDAGNode *successor=nullptr)
Definition TDGen.cc:5611
TDGen::operandToString
virtual std::string operandToString(const Operand &operand, bool match, char operandType, const std::string &immDefName="")
Definition TDGen.cc:5870

References __func__, abortWithError, assert, canBeImmediate(), constantNodeString(), dagNodeToString(), immOperandDefs_, BoostGraph< GraphNode, GraphEdge >::inDegree(), Operand::index(), BoostGraph< GraphNode, GraphEdge >::inEdge(), Operand::isInput(), Operand::isOutput(), ImmInfo::key(), Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), Operation::operand(), TerminalNode::operandIndex(), operandToString(), operationNodeToString(), OT_IMM_BOOL, OT_IMM_INT, OT_REG_BOOL, BoostGraph< GraphNode, GraphEdge >::outDegree(), OperationNode::referencedOperation(), BoostGraph< GraphNode, GraphEdge >::tailNode(), and Conversion::toString().

Referenced by dagNodeToString(), operationNodeToString(), operationPattern(), subPattern(), and writeEmulationPattern().

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◆ emulatingOpNodeLLVMName()

std::string TDGen::emulatingOpNodeLLVMName ( const Operation &  op,
const OperationDAG &  dag,
const OperationNode &  node,
const std::string &  operandTypes 
)
protected

Returns an llvm name for an operation node in an emulation dag.

Parameters
opthe operation being emulated.
dagdag of the emulated operation
nodenode whose name is being asked
operandTypesstring containing oeprand types for the emulated op.

Definition at line 5674 of file TDGen.cc.

5676 {
5677 const Operation& operation = node.referencedOperation();
5678 std::string operationName = StringTools::stringToUpper(operation.name());
5679
5680
5681 int inputs = operation.numberOfInputs();
5682
5683 // Look at outgoing nodes. If operand goes to another op,
5684 // the value is in register.
5685 // if it's terminal, get the type from the paramete string.
5686 for (int i = 1 ; i < operation.numberOfOutputs() + 1; i++) {
5687 char c = 0;
5688 for (int e = 0; e < dag.outDegree(node); e++) {
5689 const OperationDAGEdge& edge = dag.outEdge(node, e);
5690 int dst = edge.srcOperand();
5691 if (dst == i + operation.numberOfInputs()) {
5692 TerminalNode* t =
5693 dynamic_cast<TerminalNode*>(
5694 &(dag.headNode(edge)));
5695 if (t != NULL) {
5696 int strIndex = t->operandIndex() -1 -
5697 op.numberOfInputs();
5698 assert((int)operandTypes.length() > strIndex &&
5699 strIndex >= 0);
5700 if (c != 0 && c != operandTypes[strIndex]) {
5701 throw InvalidData(__FILE__,__LINE__,__func__,
5702 "conflicting output types!");
5703 }
5704 c = operandTypes[strIndex];
5705 } else {
5706 Operand &operand =
5707 operation.operand(i+operation.numberOfInputs());
5708 char type = operandChar(operand);
5709 if (c != 0 && c!= type) {
5710 throw InvalidData(__FILE__,__LINE__,__func__,
5711 "conflicting output types!");
5712 }
5713 c = type;
5714 }
5715 }
5716 }
5717 if (c == 0) {
5718 throw InvalidData(__FILE__,__LINE__,__func__,"output not found.");
5719 }
5720 operationName += c;
5721 }
5722
5723 // Look at incoming nodes. If operand comes from another op,
5724 // the value is in register. If operand comes from constant,
5725 // it's immediate.
5726 // if it's terminal, get the type from the parm string.
5727 for (int i = 1; i < inputs + 1; i++) {
5728 Operand &operand = operation.operand(i);
5729 for (int e = 0; e < dag.inDegree(node); e++) {
5730 const OperationDAGEdge& edge = dag.inEdge(node, e);
5731 int dst = edge.dstOperand();
5732 if (dst == i) {
5733 if (dynamic_cast<OperationNode*>(&(dag.tailNode(edge)))) {
5734 operationName += operandChar(operand);
5735 } else {
5736 if (dynamic_cast<ConstantNode*>(
5737 &(dag.tailNode(edge)))) {
5738 if (operand.type() == Operand::SINT_WORD ||
5739 operand.type() == Operand::UINT_WORD) {
5740 operationName += OT_IMM_INT;
5741 } else if (operand.type() == Operand::RAW_DATA ||
5742 operand.type() == Operand::SLONG_WORD ||
5743 operand.type() == Operand::ULONG_WORD) {
5744 operationName += mach_.is64bit() ?
5745 OT_IMM_LONG : OT_IMM_INT;
5746 }
5747 } else {
5748 TerminalNode* t =
5749 dynamic_cast<TerminalNode*>(
5750 &(dag.tailNode(edge)));
5751 assert (t != NULL);
5752 int strIndex = t->operandIndex() -1 +
5753 op.numberOfOutputs();
5754 if ((int)operandTypes.length() <= strIndex ||
5755 strIndex <= 0) {
5756 std::cerr << "Invalid operand types length or"
5757 << "strIndex in operation:"
5758 << operation.name()
5759 << " OperandTypes string is: "
5760 << operandTypes
5761 << " strIndex is: " << strIndex
5762 << std::endl;
5763 assert(false);
5764 }
5765 operationName += operandTypes[strIndex];
5766 }
5767 }
5768 }
5769 }
5770 }
5771 return operationName;
5772}
Operand::SLONG_WORD
@ SLONG_WORD
Definition Operand.hh:66
Operand::ULONG_WORD
@ ULONG_WORD
Definition Operand.hh:67
Operand::SINT_WORD
@ SINT_WORD
Definition Operand.hh:59
Operand::UINT_WORD
@ UINT_WORD
Definition Operand.hh:60
StringTools::stringToUpper
static std::string stringToUpper(const std::string &source)
Definition StringTools.cc:143

References __func__, assert, OperationDAGEdge::dstOperand(), BoostGraph< GraphNode, GraphEdge >::headNode(), BoostGraph< GraphNode, GraphEdge >::inDegree(), BoostGraph< GraphNode, GraphEdge >::inEdge(), TTAMachine::Machine::is64bit(), mach_, Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), Operation::operand(), operandChar(), TerminalNode::operandIndex(), OT_IMM_INT, OT_IMM_LONG, BoostGraph< GraphNode, GraphEdge >::outDegree(), BoostGraph< GraphNode, GraphEdge >::outEdge(), Operand::RAW_DATA, OperationNode::referencedOperation(), Operand::SINT_WORD, Operand::SLONG_WORD, OperationDAGEdge::srcOperand(), StringTools::stringToUpper(), BoostGraph< GraphNode, GraphEdge >::tailNode(), Operand::type(), Operand::UINT_WORD, and Operand::ULONG_WORD.

Referenced by operationNodeToString().

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◆ gatherAllMachineOperations()

void TDGen::gatherAllMachineOperations ( )
protected

Gathers all machine op names and sorts them to vector and scalar operations.

Definition at line 997 of file TDGen.cc.

997 {
998 // Get all operation names to one container.
999 allOpNames_ = MachineInfo::getOpset(mach_);
1000
1001 OperationPool opPool;
1002 OperationDAGSelector::OperationSet::const_iterator it;
1003 for (it = allOpNames_.begin(); it != allOpNames_.end(); ++it) {
1004 TCEString opName = *it;
1005 Operation* op = &opPool.operation(opName.c_str());
1006
1007 if (op != &NullOperation::instance()) {
1008 if (op->isVectorOperation()) {
1009 vectorOps_.insert(std::make_pair(opName, op));
1010 } else {
1011 scalarOps_.insert(std::make_pair(opName, op));
1012 }
1013 }
1014 }
1015}
MachineInfo::getOpset
static OperationSet getOpset(const TTAMachine::Machine &mach)
Definition MachineInfo.cc:65
Operation::isVectorOperation
virtual bool isVectorOperation() const
Definition Operation.cc:222
TDGen::scalarOps_
std::map< TCEString, Operation * > scalarOps_
Contains all scalar operations (<Name, Operation>).
Definition TDGen.hh:523
TDGen::vectorOps_
std::map< TCEString, Operation * > vectorOps_
Contains all vector operations (<Name, Operation>).
Definition TDGen.hh:526

References allOpNames_, MachineInfo::getOpset(), NullOperation::instance(), Operation::isVectorOperation(), mach_, OperationPool::operation(), scalarOps_, and vectorOps_.

Referenced by writeRegisterInfo().

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◆ generateBackend() [1/2]

std::string TDGen::generateBackend ( ) const
virtual

Writes tce backend plugin code into a single string. Used for hash generation.

Reimplemented in RISCVTDGen.

Definition at line 486 of file TDGen.cc.

486 {
487 const std::string buffer = registerInfo_ + addressingModeDefs_
488 + operandDefs_ + instrInfo_ + instrFormats_ + callingConv_
489 + argRegsArray_ + backendCode_ + topLevelTD_;
490 return buffer;
491}
TDGen::operandDefs_
std::string operandDefs_
Definition TDGen.hh:471
TDGen::argRegsArray_
std::string argRegsArray_
Definition TDGen.hh:475
TDGen::addressingModeDefs_
std::string addressingModeDefs_
Definition TDGen.hh:470
TDGen::instrInfo_
std::string instrInfo_
Definition TDGen.hh:472
TDGen::instrFormats_
std::string instrFormats_
Definition TDGen.hh:473
TDGen::backendCode_
std::string backendCode_
Definition TDGen.hh:476
TDGen::callingConv_
std::string callingConv_
Definition TDGen.hh:474
TDGen::registerInfo_
std::string registerInfo_
Definition TDGen.hh:469
TDGen::topLevelTD_
std::string topLevelTD_
Definition TDGen.hh:477

References addressingModeDefs_, argRegsArray_, backendCode_, callingConv_, instrFormats_, instrInfo_, operandDefs_, registerInfo_, and topLevelTD_.

◆ generateBackend() [2/2]

void TDGen::generateBackend ( const std::string &  path) const
virtual

Generates all files required to build a tce backend plugin (excluding static plugin code included from include/llvm/TCE/).

Reimplemented in RISCVTDGen.

Definition at line 431 of file TDGen.cc.

431 {
432 std::ofstream regTD;
433 regTD.open((path + "/GenRegisterInfo.td").c_str());
434 regTD << registerInfo_;
435 regTD.close();
436
437 std::ofstream instrTD0;
438 instrTD0.open((path + "/GenInstrInfo0.td").c_str());
439 instrTD0 << addressingModeDefs_;
440 instrTD0.close();
441
442 std::ofstream operandTD;
443 operandTD.open((path + "/GenOperandInfo.td").c_str());
444 operandTD << operandDefs_;
445 operandTD.close();
446
447 std::ofstream instrTD;
448 instrTD.open((path + "/GenInstrInfo.td").c_str());
449 instrTD << instrInfo_;
450#ifdef DEBUG_TDGEN
451 writeInstrInfo(std::cerr);
452#endif
453 instrTD.close();
454
455 std::ofstream formatTD;
456 formatTD.open((path + "/GenTCEInstrFormats.td").c_str());
457 formatTD << instrFormats_;
458 formatTD.close();
459
460 std::ofstream ccTD;
461 ccTD.open((path + "/GenCallingConv.td").c_str());
462 ccTD << callingConv_;
463 ccTD.close();
464
465 std::ofstream argArr;
466 argArr.open((path + "/ArgRegs.hh").c_str());
467 argArr << argRegsArray_;
468 argArr.close();
469
470 std::ofstream pluginInc;
471 pluginInc.open((path + "/Backend.inc").c_str());
472 pluginInc << backendCode_;
473 pluginInc.close();
474
475 std::ofstream topLevelTD;
476 topLevelTD.open((path + "/TCE.td").c_str());
477 topLevelTD << topLevelTD_;
478 topLevelTD.close();
479}
TDGen::writeInstrInfo
void writeInstrInfo(std::ostream &o)
Definition TDGen.cc:3384

References addressingModeDefs_, argRegsArray_, backendCode_, callingConv_, instrFormats_, instrInfo_, operandDefs_, registerInfo_, topLevelTD_, and writeInstrInfo().

Referenced by LLVMBackend::createPlugin(), and LLVMBackend::pluginFilename().

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◆ generateLoadStoreCopyGenerator()

void TDGen::generateLoadStoreCopyGenerator ( std::ostream &  os)
protected

Generates implementations of getLoad() and getStore() to Backend.inc file.

Parameters
osOutput stream to the file.

Definition at line 6365 of file TDGen.cc.

6365 {
6366 genGeneratedTCEPlugin_getStore(os);
6367 genGeneratedTCEPlugin_getLoad(os);
6368}
TDGen::genGeneratedTCEPlugin_getStore
void genGeneratedTCEPlugin_getStore(std::ostream &o) const
Definition TDGen.cc:2839
TDGen::genGeneratedTCEPlugin_getLoad
void genGeneratedTCEPlugin_getLoad(std::ostream &o) const
Definition TDGen.cc:2939

References genGeneratedTCEPlugin_getLoad(), and genGeneratedTCEPlugin_getStore().

Referenced by writeBackendCode().

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◆ genGeneratedTCEPlugin_getAddOpcode()

void TDGen::genGeneratedTCEPlugin_getAddOpcode ( std::ostream &  o) const
protected

Definition at line 3285 of file TDGen.cc.

3285 {
3286 o << endl
3287 << "// Returns correct vector ADD opcode" << endl
3288 << "int GeneratedTCEPlugin::getAddOpcode("
3289 << "const EVT& vt) const {" << endl;
3290
3291 for (auto it = addOperations_.begin(); it != addOperations_.end(); ++it) {
3292 o << "\tif (vt == MVT::" << it->first
3293 << ") return TCE::" << it->second << ";" << endl;
3294 }
3295
3296 o << "\treturn -1;" << endl << "}" << endl;
3297}
TDGen::addOperations_
std::map< TCEString, TCEString > addOperations_
Contains machine's add instructions (<ValueType, InstrName>).
Definition TDGen.hh:579

References addOperations_.

Referenced by writeBackendCode().

◆ genGeneratedTCEPlugin_getConstantVectorShuffleOpcode()

void TDGen::genGeneratedTCEPlugin_getConstantVectorShuffleOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getExtractElemOpcode()

void TDGen::genGeneratedTCEPlugin_getExtractElemOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getGatherOpcode()

void TDGen::genGeneratedTCEPlugin_getGatherOpcode ( std::ostream &  o) const
protected

Definition at line 3255 of file TDGen.cc.

3255 {
3256 o << endl
3257 << "// Returns correct vector GATHER opcode" << endl
3258 << "int GeneratedTCEPlugin::getGatherOpcode("
3259 << "const EVT& vt) const {" << endl;
3260
3261 for (auto it = gatherOperations_.begin(); it != gatherOperations_.end();
3262 ++it) {
3263 o << "\tif (vt == MVT::" << it->first
3264 << ") return TCE::" << it->second << ";" << endl;
3265 }
3266
3267 o << "\treturn -1;" << endl << "}" << endl;
3268}
TDGen::gatherOperations_
std::map< TCEString, TCEString > gatherOperations_
Contains machine's GATHER instructions (<ValueType, InstrName>).
Definition TDGen.hh:577

References gatherOperations_.

◆ genGeneratedTCEPlugin_getIorOpcode()

void TDGen::genGeneratedTCEPlugin_getIorOpcode ( std::ostream &  o) const
protected

Definition at line 3315 of file TDGen.cc.

3315 {
3316 o << endl
3317 << "// Returns correct vector SHL opcode" << endl
3318 << "int GeneratedTCEPlugin::getIorOpcode("
3319 << "const EVT& vt) const {" << endl;
3320
3321 for (auto it = iorOperations_.begin(); it != iorOperations_.end(); ++it) {
3322 o << "\tif (vt == MVT::" << it->first
3323 << ") return TCE::" << it->second << ";" << endl;
3324 }
3325
3326 o << "\treturn -1;" << endl << "}" << endl;
3327}
TDGen::iorOperations_
std::map< TCEString, TCEString > iorOperations_
Contains machine's shl instructions (<ValueType, InstrName>).
Definition TDGen.hh:583

References iorOperations_.

Referenced by writeBackendCode().

◆ genGeneratedTCEPlugin_getLoad()

void TDGen::genGeneratedTCEPlugin_getLoad ( std::ostream &  o) const
protected

Generates implementation of getLoad() function.

Definition at line 2939 of file TDGen.cc.

2939 {
2940 TCEString prefix = "&"; // Address of -operator.
2941 TCEString rcpf = "RegsRegClass";
2942 TCEString rapf = "TCE::RARegRegClass";
2943
2944 TCEString loadB = littleEndian_ ? "LD8" : "LDQ";
2945 if (!mach_.hasOperation(loadB)) {
2946 loadB = littleEndian_ ? "LDU8" : "LDQU";
2947 if (!mach_.hasOperation(loadB)) {
2948 loadB="";
2949 }
2950 }
2951
2952 TCEString loadW = littleEndian_ ? "LD32" : "LDW";
2953 TCEString loadH = littleEndian_ ? "LD16" : "LDH";
2954 TCEString loadL = "LD64";
2955 if (!mach_.hasOperation(loadH)) {
2956 loadH = littleEndian_ ? "LDU16;" : "LDHU";
2957 if (!mach_.hasOperation(loadH)) {
2958 loadH="";
2959 }
2960 }
2961
2962 o << "int GeneratedTCEPlugin::getLoad(const TargetRegisterClass *rc)"
2963 << " const {" << endl;
2964
2965 o << "\tif (rc == " << prefix << rapf << ") return TCE::"
2966 << loadW << "RAr;" << endl;
2967
2968 if (!mach_.hasOperation(loadW) && mach_.hasOperation("LDU32")) {
2969 loadW = "LDU32";
2970 }
2971
2972 for (RegClassMap::const_iterator ri = regsInClasses_.begin();
2973 ri != regsInClasses_.end(); ri++) {
2974 if ((ri->first.find("R1") == 0 ||
2975 ri->first.find(TDGen::guardRegTemplateName) == 0) &&
2976 ri->first.find("R16") != 0 && loadB != "") {
2977 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2978 << rcpf <<") return TCE::" << loadB << "Br;" << endl;
2979 }
2980 if (ri->first.find("R32") == 0) {
2981 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2982 << rcpf << ") return TCE::" << loadW << "rr;" << endl;
2983
2984 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2985 << "I" << rcpf << ") return TCE::" << loadW << "rr;" << endl;
2986
2987 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2988 << "FP" << rcpf << ") return TCE::" << loadW << "fr;" << endl;
2989 if (loadH != "") {
2990 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2991 << "HFP" << rcpf << ") return TCE::" << loadH << "hr;" << endl;
2992 }
2993 }
2994 if (mach_.is64bit()) {
2995 if (ri->first.find("R64") == 0) {
2996 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2997 << rcpf << ") return TCE::" << loadL << "ss;" << endl;
2998
2999 o << "\tif (rc == " << prefix << "TCE::" << ri->first
3000 << "I" << rcpf << ") return TCE::" << loadL << "ss;" << endl;
3001
3002 o << "\tif (rc == " << prefix << "TCE::" << ri->first
3003 << "DFP" << rcpf << ") return TCE::" << loadL << "ds;" << endl;
3004
3005 }
3006 }
3007 }
3008
3009 if (use64bitForFP_) {
3010 o << "\tif (rc == &TCE::FPRegsRegClass) return TCE::LD64fs;"
3011 << std::endl;
3012
3013 o << "\tif (rc == &TCE::HFPRegsRegClass) return TCE::LD64hs;"
3014 << std::endl;
3015 } else {
3016 o << "\tif (rc == &TCE::FPRegsRegClass) return TCE::"
3017 << loadW << "fr;" << std::endl;
3018
3019 o << "\tif (rc == &TCE::HFPRegsRegClass) return TCE::"
3020 << loadW << "hr;" << std::endl;
3021 }
3022
3023 std::map<TCEString, RegisterClass>::const_iterator it;
3024 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
3025 const TCEString& vtStr = it->first;
3026 const RegisterClass& regClass = it->second;
3027
3028 std::map<TCEString, InstructionInfo>::const_iterator loadIt =
3029 registerLoads_.find(vtStr);
3030
3031 if (loadIt != registerLoads_.end()) {
3032 o << "\tif (rc == &TCE::" << regClass.name() << "RegClass) "
3033 << "return TCE::" << (loadIt->second).instrName_ << ";" << endl;
3034 } else {
3035 verbose("Warning: no load generated for RegisterClass " +
3036 regClass.name() + " to GeneratedTCEPlugin::getLoad");
3037 }
3038 }
3039
3040 o << "\tprintf(\"regclass of size %d \\n\", rc->MC->RegsSize);" << std::endl
3041 << "\tassert(0&&\"loading from stack to given regclass not supported."
3042 << " Bug in backend?\");"
3043 << endl
3044 << "} " << endl
3045 << endl;
3046}
TDGen::regsInClasses_
RegClassMap regsInClasses_
All registers in certain group.
Definition TDGen.hh:645
TDGen::registerLoads_
std::map< TCEString, TDGenerator::InstructionInfo > registerLoads_
All register load operations (<ValueType, InstrInfo>).
Definition TDGen.hh:540
TDGen::guardRegTemplateName
static const std::string guardRegTemplateName
Definition TDGen.hh:651

References guardRegTemplateName, TTAMachine::Machine::hasOperation(), TTAMachine::Machine::is64bit(), littleEndian_, mach_, TDGenerator::RegisterClass::name(), registerLoads_, regsInClasses_, use64bitForFP_, verbose(), and vRegClasses_.

Referenced by generateLoadStoreCopyGenerator().

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◆ genGeneratedTCEPlugin_getLoadOpcode()

void TDGen::genGeneratedTCEPlugin_getLoadOpcode ( std::ostream &  o) const
protected

Definition at line 3271 of file TDGen.cc.

3271 {
3272 o << endl
3273 << "// Returns correct load opcode" << endl
3274 << "int GeneratedTCEPlugin::getLoadOpcode("
3275 << "const EVT& vt) const {" << endl;
3276
3277 for (auto it = registerLoads_.begin(); it != registerLoads_.end(); ++it) {
3278 o << "\tif (vt == MVT::" << it->first
3279 << ") return TCE::" << it->second.instrName_ << ";" << endl;
3280 }
3281 o << "\treturn -1;" << endl << "}" << endl;
3282}

References registerLoads_.

Referenced by writeBackendCode().

◆ genGeneratedTCEPlugin_getShlOpcode()

void TDGen::genGeneratedTCEPlugin_getShlOpcode ( std::ostream &  o) const
protected

Definition at line 3300 of file TDGen.cc.

3300 {
3301 o << endl
3302 << "// Returns correct vector SHL opcode" << endl
3303 << "int GeneratedTCEPlugin::getShlOpcode("
3304 << "const EVT& vt) const {" << endl;
3305
3306 for (auto it = shlOperations_.begin(); it != shlOperations_.end(); ++it) {
3307 o << "\tif (vt == MVT::" << it->first
3308 << ") return TCE::" << it->second << ";" << endl;
3309 }
3310
3311 o << "\treturn -1;" << endl << "}" << endl;
3312}
TDGen::shlOperations_
std::map< TCEString, TCEString > shlOperations_
Contains machine's shl instructions (<ValueType, InstrName>).
Definition TDGen.hh:581

References shlOperations_.

Referenced by writeBackendCode().

◆ genGeneratedTCEPlugin_getStore()

void TDGen::genGeneratedTCEPlugin_getStore ( std::ostream &  o) const
protected

Generates implementation of getStore() function.

Definition at line 2839 of file TDGen.cc.

2839 {
2840 TCEString prefix = "&"; // Address of -operator.
2841 TCEString rcpf = "RegsRegClass";
2842 TCEString rapf = "TCE::RARegRegClass";
2843 TCEString storeB = littleEndian_ ? "ST8Brb;" : "STQBrb;";
2844 TCEString storeW = littleEndian_ ? "ST32" : "STW";
2845 TCEString storeH = littleEndian_ ? "ST16" : "STH";
2846 TCEString storeL = "ST64";
2847
2848 o << "#include <stdio.h>" << endl
2849 << "int GeneratedTCEPlugin::getStore(const TargetRegisterClass *rc)"
2850 << " const {" << endl;
2851
2852 o << "\tif (rc == " << prefix << rapf
2853 << ") return TCE::STWRArr;"
2854 << endl;
2855
2856 for (RegClassMap::const_iterator ri = regsInClasses_.begin();
2857 ri != regsInClasses_.end(); ri++) {
2858
2859 if ((ri->first.find("R1") == 0 ||
2860 ri->first.find(TDGen::guardRegTemplateName) == 0) &&
2861 ri->first.find("R16") != 0) {
2862 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2863 << rcpf << ") return TCE::" << storeB << endl;
2864 }
2865 if (ri->first.find("R32") == 0) {
2866 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2867 << rcpf << ") return TCE::" << storeW << "rr;" << endl;
2868
2869 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2870 << "I" << rcpf << ") return TCE::" << storeW << "rr;" << endl;
2871
2872 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2873 << "FP" << rcpf << ") return TCE::" << storeW << "fr;" << endl;
2874
2875 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2876 << "HFP" << rcpf << ") return TCE::" << storeH << "hr;" << endl;
2877 }
2878 if (mach_.is64bit()) {
2879 if (ri->first.find("R64") == 0) {
2880 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2881 << rcpf << ") return TCE::" << storeL << "ss;" << endl;
2882
2883 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2884 << "I" << rcpf << ") return TCE::" << storeL << "ss;"
2885 << endl;
2886
2887 o << "\tif (rc == " << prefix << "TCE::" << ri->first
2888 << "DFP" << rcpf << ") return TCE::" << storeL << "ds;"
2889 << endl;
2890 }
2891 // TODO: double support here?
2892 }
2893 }
2894
2895 if (use64bitForFP_) {
2896 o << "\tif (rc == &TCE::FPRegsRegClass) return TCE::ST64fs;"
2897 << std::endl;
2898
2899 o << "\tif (rc == &TCE::HFPRegsRegClass) return TCE::ST64hs;"
2900 << std::endl;
2901 } else {
2902 o << "\tif (rc == &TCE::FPRegsRegClass) return TCE::"
2903 << storeW << "fr;" << std::endl;
2904
2905 o << "\tif (rc == &TCE::HFPRegsRegClass) return TCE::"
2906 << storeW << "hr;" << std::endl;
2907 }
2908
2909 std::map<TCEString, RegisterClass>::const_iterator it;
2910 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
2911 const TCEString& vtStr = it->first;
2912 const RegisterClass& regClass = it->second;
2913
2914 std::map<TCEString, InstructionInfo>::const_iterator storeIt =
2915 registerStores_.find(vtStr);
2916
2917 if (storeIt != registerStores_.end()) {
2918 o << "\tif (rc == &TCE::" << regClass.name() << "RegClass) "
2919 << "return TCE::" << (storeIt->second).instrName_ << ";" << endl;
2920 } else {
2921 verbose("Warning: no store generated for RegisterClass " +
2922 regClass.name() + " to GeneratedTCEPlugin::getStore");
2923 }
2924 }
2925
2926 o << "\tstd::cerr << \"regclass id:\" <<rc->getID() << \"of size \" "
2927 << "<<rc->MC->RegsSize<< std::endl;" << std::endl;
2928 o << "\tassert(0&&\"Storing given regclass to stack not supported. "
2929 << "Bug in backend?\");"
2930 << endl
2931 << "} " << endl
2932 << endl;
2933}
TDGen::registerStores_
std::map< TCEString, TDGenerator::InstructionInfo > registerStores_
All register store operations (<ValueType, InstrInfo>).
Definition TDGen.hh:538

References guardRegTemplateName, TTAMachine::Machine::is64bit(), littleEndian_, mach_, TDGenerator::RegisterClass::name(), registerStores_, regsInClasses_, use64bitForFP_, verbose(), and vRegClasses_.

Referenced by generateLoadStoreCopyGenerator().

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◆ genGeneratedTCEPlugin_getVectorAndSameOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorAndSameOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorBroadcastOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorBroadcastOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorImmediateOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorImmediateOpcode ( std::ostream &  o) const
protected

Definition at line 3235 of file TDGen.cc.

3236 {
3237 backendCode << "int GeneratedTCEPlugin::getVectorImmediateOpcode(const "
3238 "EVT& vt) const {"
3239 << std::endl;
3240 for (auto it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
3241 const RegisterClass& regClass = it->second;
3242 TCEString regClassName = regClass.name();
3243 ValueType valType = regClass.valueType();
3244 TCEString valTypeName = valType.valueTypeStr();
3245 if (valType.width() <= 32) {
3246 TCEString opName = "MOVI" + valTypeName;
3247 backendCode << "\tif (vt == MVT::" << valTypeName
3248 << ") return TCE::" << opName << ";" << std::endl;
3249 }
3250 }
3251 backendCode << "\treturn -1;\n}" << endl;
3252}

References TDGenerator::RegisterClass::name(), TDGenerator::RegisterClass::valueType(), TDGenerator::ValueType::valueTypeStr(), vRegClasses_, and TDGenerator::ValueType::width().

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◆ genGeneratedTCEPlugin_getVectorIorSameOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorIorSameOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorPackOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorPackOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorSelectOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorSelectOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorShlSameOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorShlSameOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorShrSameOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorShrSameOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorShruSameOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorShruSameOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorShuffle1Opcode()

void TDGen::genGeneratedTCEPlugin_getVectorShuffle1Opcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorShuffle2Opcode()

void TDGen::genGeneratedTCEPlugin_getVectorShuffle2Opcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorValueType()

void TDGen::genGeneratedTCEPlugin_getVectorValueType ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_getVectorXorSameOpcode()

void TDGen::genGeneratedTCEPlugin_getVectorXorSameOpcode ( std::ostream &  o) const
protected

◆ genGeneratedTCEPlugin_isVectorRegisterMove()

void TDGen::genGeneratedTCEPlugin_isVectorRegisterMove ( std::ostream &  o) const
protected

◆ genTCEInstrInfo_copyPhys64bitReg()

void TDGen::genTCEInstrInfo_copyPhys64bitReg ( std::ostream &  o) const
protected

Definition at line 8396 of file TDGen.cc.

8396 {
8397 o << std::endl
8398 << "#include <llvm/CodeGen/MachineInstrBuilder.h>" << std::endl
8399 << "// copies 64-bit reg to a another" << std::endl
8400 << "bool TCEInstrInfo::copyPhys64bitReg(" << std::endl
8401 << "\tMachineBasicBlock& mbb," << std::endl
8402 << "\tMachineBasicBlock::iterator mbbi," << std::endl
8403 << "const DebugLoc& dl," << std::endl
8404 << "\tunsigned destReg, unsigned srcReg," << std::endl
8405 << "\tbool killSrc) const {" << std::endl
8406 << std::endl;
8407
8408 if (mach_.is64bit()) {
8409 o << "\tif (TCE::R64RegsRegClass.contains(destReg, srcReg)) {\n"
8410 << "\t\tBuildMI(mbb, mbbi, dl, get(TCE::MOV64rr), destReg)\n"
8411 << "\t\t\t.addReg(srcReg, getKillRegState(killSrc));" << std::endl
8412 << "\t\treturn true;" << std::endl
8413 << "}" << std::endl;
8414 }
8415 o << "\treturn false;" << std::endl
8416 << "}";
8417}

References TTAMachine::Machine::is64bit(), and mach_.

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◆ genTCEInstrInfoSIMD_copyPhysVectorReg()

void TDGen::genTCEInstrInfoSIMD_copyPhysVectorReg ( std::ostream &  o) const
protected

Generates implementation of copyPhysVectorReg().

Only the previously created vector register classes are added to the implementation to make LLVM compilation flow work.

Definition at line 3187 of file TDGen.cc.

3187 {
3188 o << endl
3189 << "#include <llvm/CodeGen/MachineInstrBuilder.h>" << endl
3190 << "// Copies a vector register to another" << endl
3191
3192 << "bool TCEInstrInfo::copyPhysVectorReg(" << endl
3193 << "\tMachineBasicBlock& mbb," << endl
3194 << "\tMachineBasicBlock::iterator mbbi," << endl
3195 << "const DebugLoc& dl," << endl
3196 << "\tMCRegister destReg, MCRegister srcReg," << endl
3197 << "\tbool killSrc) const {" << endl
3198 << endl;
3199
3200 std::map<TCEString, RegisterClass>::const_iterator it;
3201 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
3202 const RegisterClass& regClass = it->second;
3203
3204 o << "\tif (TCE::" << regClass.name()
3205 << "RegClass.contains(destReg, srcReg)) {" << endl
3206 << "\t\tBuildMI(mbb, mbbi, dl, get(TCE::"
3207 << "MOV" << regClass.name() << "), destReg)" << endl
3208 << "\t\t.addReg(srcReg, getKillRegState(killSrc));" << endl
3209 << "\t\treturn true;" << endl
3210 << "\t}" << endl;
3211 }
3212 o << "\treturn false;" << endl << "}" << endl;
3213}

References TDGenerator::RegisterClass::name(), and vRegClasses_.

Referenced by writeBackendCode().

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◆ genTCERegisterInfo_setReservedVectorRegs()

void TDGen::genTCERegisterInfo_setReservedVectorRegs ( std::ostream &  os) const
protected

Definition at line 4203 of file TDGen.cc.

4204 {
4205 os << "void TCERegisterInfo::setReservedVectorRegs("
4206 << "llvm::BitVector& reserved) const {" << std::endl;
4207
4208 std::set<TCEString> processedRegs;
4209 for (auto rcIt : vRegClasses_) {
4210 const RegisterClass& regClass = rcIt.second;
4211
4212 int width = regClass.valueType().width();
4213 if (regClass.numberOfRegisters() > 0) {
4214 const TCEString& name = regClass.registerInfo(0).regName_;
4215 if (processedRegs.find(name) == processedRegs.end() &&
4216 width > maxScalarWidth_) {
4217 processedRegs.insert(name);
4218 os << "reserved.set(TCE::" << name << ");" << std::endl;
4219 }
4220 }
4221 }
4222 os << "}" << std::endl;
4223}

References maxScalarWidth_, TDGenerator::RegisterClass::numberOfRegisters(), TDGenerator::RegisterClass::registerInfo(), TDGenerator::RegisterInfo::regName_, TDGenerator::RegisterClass::valueType(), vRegClasses_, and TDGenerator::ValueType::width().

Referenced by writeBackendCode().

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◆ genTCETargetLoweringSIMD_addVectorRegisterClasses()

void TDGen::genTCETargetLoweringSIMD_addVectorRegisterClasses ( std::ostream &  o) const
protected

Generates a function that adds existing register classes in lowering phase.

Definition at line 3053 of file TDGen.cc.

3054 {
3055 o << endl << "// Adds all vector classes to backend" << endl
3056 << "void TCETargetLowering::addVectorRegisterClasses() {" << endl;
3057 std::map<TCEString, RegisterClass>::const_iterator it;
3058 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
3059 const RegisterClass& regClass = it->second;
3060
3061 o << "\taddRegisterClass("
3062 << "MVT::" << regClass.valueType().valueTypeStr() << ", "
3063 << "&TCE::" << regClass.name() << "RegClass);"
3064 << endl;
3065 }
3066
3067 o << "}" << endl;
3068
3069 o << endl << "// Sets build and extract lowering" << endl
3070 << "void TCETargetLowering::addVectorLowerings() {" << endl;
3071
3072 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
3073 const RegisterClass& regClass = it->second;
3074
3075 o << "\tsetOperationAction(ISD::BUILD_VECTOR,"
3076 << "MVT::" << regClass.valueType().valueTypeStr() << ", "
3077 << "Custom);" << endl;
3078
3079 o << "\tsetOperationAction(ISD::EXTRACT_SUBVECTOR,"
3080 << "MVT::" << regClass.valueType().valueTypeStr() << ", "
3081 << "Expand);" << endl;
3082
3083 for (auto vt : ValueType::SUPPORTED_LLVM_VALUE_TYPES) {
3084 if (vRegClasses_.find(vt) == vRegClasses_.end()) {
3085 o << "\tsetTruncStoreAction(MVT::"
3086 << regClass.valueType().valueTypeStr()
3087 << ", MVT::" << vt << ", Expand);" << endl;
3088 }
3089 }
3090 }
3091 o << "}" << endl;
3092}

References TDGenerator::RegisterClass::name(), TDGenerator::ValueType::SUPPORTED_LLVM_VALUE_TYPES, TDGenerator::RegisterClass::valueType(), TDGenerator::ValueType::valueTypeStr(), and vRegClasses_.

Referenced by writeBackendCode().

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◆ genTCETargetLoweringSIMD_associatedVectorRegClass()

void TDGen::genTCETargetLoweringSIMD_associatedVectorRegClass ( std::ostream &  o) const
protected

Generates a function that returns correct reg class for a value type.

Definition at line 3098 of file TDGen.cc.

3099 {
3100 o << endl << "// Returns vector register class for given value type"
3101 << endl
3102 << "std::pair<unsigned, const TargetRegisterClass*> "
3103 << "TCETargetLowering::associatedVectorRegClass(const EVT& vt) "
3104 << "const {"
3105 << endl;
3106
3107 std::map<TCEString, RegisterClass>::const_iterator it;
3108 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
3109 const TCEString& vtStr = it->first;
3110 const RegisterClass& regClass = it->second;
3111
3112 o << "\tif (vt == MVT::" << vtStr << ") "
3113 << "return std::make_pair(0U, &TCE::"
3114 << regClass.name() << "RegClass);" << endl;
3115 }
3116
3117 o << "\treturn std::make_pair(0U, (TargetRegisterClass*)0);" << endl
3118 << "}" << endl;
3119}

References TDGenerator::RegisterClass::name(), and vRegClasses_.

Referenced by writeBackendCode().

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◆ genTCETargetLoweringSIMD_getSetCCResultVT()

void TDGen::genTCETargetLoweringSIMD_getSetCCResultVT ( std::ostream &  o) const
protected

Generates a function that returns correct return value type for comparisons.

In LLVM vector comparison operations result into boolean vectors, which have the same subword count as input vectors.

Definition at line 3128 of file TDGen.cc.

3128 {
3129 o << endl
3130 << "llvm::EVT TCETargetLowering::getSetCCResultVT(const EVT& vt) "
3131 << "const {"
3132 << endl;
3133
3134 int subwCount = 2;
3135 while (subwCount <= MAX_SUBW_COUNT) {
3136 TCEString boolVecVtStr = "v" + Conversion::toString(subwCount) + "i1";
3137 ValueType boolVecVt(boolVecVtStr);
3138
3139 if (!boolVecVt.isSupportedByLLVM()) {
3140 break;
3141 }
3142
3143 o << "\tif (vt.getVectorElementCount().getKnownMinValue() == "
3144 << Conversion::toString(subwCount) << ") return llvm::MVT::"
3145 << boolVecVtStr << ";" << endl;
3146 subwCount *= 2;
3147 }
3148
3149 o << "\treturn llvm::MVT::INVALID_SIMPLE_VALUE_TYPE;" << endl
3150 << "}" << endl;
3151}
TDGen::MAX_SUBW_COUNT
static const int MAX_SUBW_COUNT
Maximum number of subwords that any SIMD operation can have.
Definition TDGen.hh:488

References TDGenerator::ValueType::isSupportedByLLVM(), MAX_SUBW_COUNT, and Conversion::toString().

Referenced by writeBackendCode().

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◆ getLLVMPatternWithConstants()

TCEString TDGen::getLLVMPatternWithConstants ( const Operation &  op,
const std::string &  operandTypes,
const std::string &  operand0,
const std::string &  operand1 
) const
protected

Returns LLVM pattern for the expression with constant value(s) supported by target machine.

For example, for pattern (SUBrri (foo ...), 123) the method returns (SUBrrr (foo ...), (MOVI32ri 123)) if the target machine can not supply the constant "123" as an immediate.

The method should be called after all operation definitions have been created (after all calls to writeOperationDef()).

Return empty string if the given pattern can not be handled because:

  • Operation is not supported by target machine.
Parameters
opThe operation.
operandTypesThe preferred operand types.
operand0The pattern for the first operand or constant indicated by operandTypes.
operand1The pattern for the second operand or constant indicated by operandTypes.

Definition at line 7756 of file TDGen.cc.

7759 {
7760
7761 //TODO If operation is not supported, try to replace it with an emulation
7762 // pattern first and then deal with the new patterns with constant
7763 // operands (and take account possible infinite recursion).
7764 //TODO Cache the calculated results?
7765
7766 assert(op.numberOfInputs() == 2);
7767
7768 auto makePattern = [](
7769 const std::string& opc,
7770 const std::string& opdTypes,
7771 const std::string& operand0,
7772 const std::string& operand1) -> TCEString {
7773 return std::string("(") + opc + opdTypes + " " + operand0
7774 + ", " + operand1 + ")";
7775 };
7776
7777 std::string opc = StringTools::stringToUpper(op.name());
7778 const std::string outputOpdTypes = operandTypes.substr(
7779 0, op.numberOfOutputs());
7780 const std::string inputOpdTypes = operandTypes.substr(
7781 op.numberOfOutputs());
7782 assert(inputOpdTypes.size() == 2);
7783 const auto regOperandsOnly = operandTypesToRegisters(operandTypes);
7784 if (!opNames_.count(opc + regOperandsOnly)) {
7785 // Operation is not supported at all by the target machine.
7786 return "";
7787 }
7788
7789 if (opNames_.count(opc + operandTypes)) {
7790 // Supported as is.
7791 return makePattern(opc, operandTypes, operand0, operand1);
7792 }
7793
7794 std::vector<std::string> supportedOperandTypes;
7795 for (auto i = 0u; i < inputOpdTypes.size(); i++) {
7796 std::string oneInputChanged = inputOpdTypes;
7797 oneInputChanged[i] = operandTypeToRegister(oneInputChanged[i]);
7798 if (oneInputChanged == inputOpdTypes) continue;
7799 if (opNames_.count(opc + outputOpdTypes + oneInputChanged)) {
7800 supportedOperandTypes.push_back(oneInputChanged);
7801 }
7802 }
7803
7804 supportedOperandTypes.push_back(regOperandsOnly);
7805
7806 std::vector<const std::string*> inputOpdValues{&operand0, &operand1};
7807
7808 // Now legalize pattern by changing unsupported immediate operands with
7809 // immediate moves.
7810 for (const auto& supportedOpdType : supportedOperandTypes) {
7811
7812 // Loop throught immediate opd types. Check if constant is encodable
7813 // for the operation.
7814 bool isSupported = true;
7815 for (auto i = 0u; i < supportedOpdType.size(); i++) {
7816 auto& opdType = supportedOpdType.at(i);
7817 auto osalOpdIdx = i - op.numberOfInputs() + 1;
7818
7819 bool ok = false;
7820 switch (opdType) {
7821 default:
7822 ok = true; // Ok. Not immediate type.
7823 break;
7824 case OT_IMM_INT: {
7825 bool isOperandReference =
7826 inputOpdValues.at(i)->find(":$") != std::string::npos;
7827 if (isOperandReference) {
7828 // Size of the constant is not known, must expect the
7829 // worst.
7830 ok = false;
7831 break;
7832 }
7833 int64_t value = Conversion::toInt(
7834 *inputOpdValues.at(i));
7835 ok = immInfo_->canTakeImmediate(op, osalOpdIdx, value,
7836 32);
7837 }
7838 break;
7839 case OT_IMM_FP:
7840 ok = immInfo_->canTakeImmediateByWidth(
7841 op, osalOpdIdx, 32);
7842 break;
7843 case OT_IMM_HFP:
7844 ok = immInfo_->canTakeImmediateByWidth(
7845 op, osalOpdIdx, 16);
7846 break;
7847 case OT_IMM_BOOL:
7848 ok = immInfo_->canTakeImmediateByWidth(
7849 op, osalOpdIdx, 1);
7850 break;
7851 }
7852 if (!ok) {
7853 isSupported = false;
7854 break;
7855 }
7856 }
7857
7858 if (!isSupported) continue;
7859
7860 std::string result = std::string("(") + opc + outputOpdTypes
7861 + supportedOpdType + " ";
7862 if (supportedOpdType.at(0) == inputOpdTypes.at(0)) {
7863 result += *inputOpdValues.at(0);
7864 } else {
7865 result += getMovePattern(
7866 inputOpdTypes.at(0), *inputOpdValues.at(0));
7867 }
7868 for (auto i = 1u; i < supportedOpdType.size(); i++) {
7869 result += ", ";
7870 if (supportedOpdType.at(i) == inputOpdTypes.at(i)) {
7871 result += *inputOpdValues.at(i);
7872 } else {
7873 result += getMovePattern(
7874 inputOpdTypes.at(i), *inputOpdValues.at(i));
7875 }
7876 }
7877 result += ")";
7878 return result;
7879 }
7880
7881 return "";
7882}
Conversion::toInt
static int toInt(const T &source)
ImmInfo::canTakeImmediate
bool canTakeImmediate(const Operation &operation, int inputOperandId, int64_t value, int destWidth)
Definition ImmInfo.cc:252
ImmInfo::canTakeImmediateByWidth
bool canTakeImmediateByWidth(const Operation &operation, int inputOperandId, int bitWidth)
Definition ImmInfo.cc:275
TDGen::operandTypesToRegisters
std::string operandTypesToRegisters(const std::string &opdTypes) const
Definition TDGen.cc:7885
TDGen::operandTypeToRegister
char operandTypeToRegister(const char &opdType) const
Definition TDGen.cc:7894
TDGen::getMovePattern
TCEString getMovePattern(const char &opdType, const std::string &inputPattern) const
Definition TDGen.cc:7909
TDGen::OT_IMM_HFP
static const char OT_IMM_HFP
Definition TDGen.hh:506

References assert, ImmInfo::canTakeImmediate(), ImmInfo::canTakeImmediateByWidth(), getMovePattern(), immInfo_, Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), operandTypesToRegisters(), operandTypeToRegister(), opNames_, OT_IMM_BOOL, OT_IMM_FP, OT_IMM_HFP, OT_IMM_INT, StringTools::stringToUpper(), and Conversion::toInt().

Referenced by createSelectPatterns().

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◆ getMatchableOperationDAG()

const OperationDAG * TDGen::getMatchableOperationDAG ( const Operation &  op)
protected

Returns first operation DAG that can be used in LLVM pattern.

Operation DAGs are traversed in the order of trigger-semantics in the first .opp file found in path that defines the Operation.

This method does not transfer ownership.

Returns
The matchable operation DAG. Nullptr if could not find.

Definition at line 5361 of file TDGen.cc.

5362 {
5363
5364 // check if one of dags of operation is ok
5365 for (int i = 0; i < op.dagCount(); i++) {
5366 OperationDAG& dag = op.dag(i);
5367 if (op.dagError(i) != "") {
5368 std::cerr << "Broken dag in operation " << op.name()
5369 << op.dagCode(i) << std::endl;
5370 assert(0);
5371 }
5372
5373 if (operationDAGCanBeMatched(dag)) {
5374 return &dag;
5375 }
5376 }
5377 return nullptr;
5378}
Operation::dag
virtual OperationDAG & dag(int index) const
Definition Operation.cc:148
Operation::dagError
virtual TCEString dagError(int index) const
Definition Operation.cc:182
Operation::dagCode
virtual TCEString dagCode(int index) const
Definition Operation.cc:159
Operation::dagCount
virtual int dagCount() const
Definition Operation.cc:134
TDGen::operationDAGCanBeMatched
bool operationDAGCanBeMatched(const OperationDAG &op, std::set< std::string > *recursionCycleCheck=NULL, bool recursionHasStore=false)
Definition TDGen.cc:5315

References assert, Operation::dag(), Operation::dagCode(), Operation::dagCount(), Operation::dagError(), Operation::name(), and operationDAGCanBeMatched().

Referenced by operationNodeToString(), and writeOperationDef().

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◆ getMatchableOperationDAGs()

const std::vector< OperationDAG * > TDGen::getMatchableOperationDAGs ( const Operation &  op)
protected

Returns a vector of DAGs that can be used in LLVM pattern.

Operation DAGs are traversed in the order of trigger-semantics in the first .opp file found in path that defines the Operation.

This method does not transfer ownership.

Returns
The matchable operation DAGs. Empty if could not find.

Definition at line 5391 of file TDGen.cc.

5392 {
5393 std::vector<OperationDAG*> matchableDAGs;
5394 for (int i = 0; i < op.dagCount(); i++) {
5395 OperationDAG& dag = op.dag(i);
5396 if (op.dagError(i) != "") {
5397 std::cerr << "Broken dag in operation " << op.name()
5398 << op.dagCode(i) << std::endl;
5399 continue;
5400 }
5401
5402 if (operationDAGCanBeMatched(dag)) {
5403 matchableDAGs.push_back(&dag);
5404 }
5405 }
5406 return matchableDAGs;
5407}

References Operation::dag(), Operation::dagCode(), Operation::dagCount(), Operation::dagError(), Operation::name(), and operationDAGCanBeMatched().

Referenced by RISCVTDGen::writePatternDefinition().

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◆ getMovePattern()

TCEString TDGen::getMovePattern ( const char &  opdType,
const std::string &  inputPattern 
) const
protected

Definition at line 7909 of file TDGen.cc.

7910 {
7911
7912 TCEString pat = "(MOV";
7913 // Note: This listing is incomplete.
7914 switch (opdType) {
7915 case OT_IMM_INT: // Integer immediate.
7916 pat += std::string("I32") + operandTypeToRegister(opdType) + opdType;
7917 break;
7918 case OT_REG_INT: // Integer register.
7919 pat += std::string("I32") + operandTypeToRegister(opdType) + opdType;
7920 break;
7921 case OT_IMM_BOOL: // Boolean immediate.
7922 pat += "I1ri"; //TODO: this is inconsistent
7923 break;
7924 case OT_REG_BOOL: // Boolean register.
7925 pat += "I1rr"; //TODO: this is inconsistent
7926 break;
7927 case OT_IMM_FP: // Single precision floating point immediate.
7928 case OT_REG_FP: // -||- register.
7929 pat += std::string("F32") + operandTypeToRegister(opdType) + opdType;
7930 break;
7931 case OT_IMM_HFP: // Half precision floating point immediate.
7932 case OT_REG_HFP: // -||- register.
7933 pat += std::string("F16") + operandTypeToRegister(opdType) + opdType;
7934 break;
7935 // TODO: vector register and immediate types.
7936 default:
7937 assert(false && "Handling for a type not implemented");
7938 break;
7939 }
7940 pat += " " + inputPattern + ")";
7941 return pat;
7942}

References assert, operandTypeToRegister(), OT_IMM_BOOL, OT_IMM_FP, OT_IMM_HFP, OT_IMM_INT, OT_REG_BOOL, OT_REG_FP, OT_REG_HFP, and OT_REG_INT.

Referenced by getLLVMPatternWithConstants().

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◆ hasRawOperands()

bool TDGen::hasRawOperands ( const Operation &  op) const
protected

Checks if operation has operands of raw type.

Parameters
opOperation to be checked.
Returns
True, if operation has at least one operand of raw type.

Definition at line 1755 of file TDGen.cc.

1755 {
1756 for (int i = 1; i <= op.operandCount(); ++i) {
1757 const Operand& operand = op.operand(i);
1758 if (operand.type() == Operand::RAW_DATA && operand.isVector()) {
1759 return true;
1760 }
1761 }
1762 return false;
1763}

References Operand::isVector(), Operation::operand(), Operation::operandCount(), Operand::RAW_DATA, and Operand::type().

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◆ hasRegisterClassSupport() [1/2]

bool TDGen::hasRegisterClassSupport ( const Operation &  op) const
protected

Checks if all operands of the operation have a supporting register class.

Parameters
opOperation whose operands will be checked.
Returns
True, if all operands are supported by register classes.

Definition at line 1805 of file TDGen.cc.

1805 {
1806 for (int i = 1; i <= op.operandCount(); ++i) {
1807 const Operand& operand = op.operand(i);
1808
1809 if (operand.isVector()) {
1810 TCEString vtStr = ValueType::valueTypeStr(operand);
1811 if (vRegClasses_.find(vtStr) == vRegClasses_.end()) {
1812 return false;
1813 }
1814 }
1815 }
1816
1817 return true;
1818}

References Operand::isVector(), Operation::operand(), Operation::operandCount(), TDGenerator::ValueType::valueTypeStr(), and vRegClasses_.

Referenced by writeScalarOperationExploitations(), writeVectorBitwiseOperationDefs(), and writeVectorOperationDef().

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◆ hasRegisterClassSupport() [2/2]

bool TDGen::hasRegisterClassSupport ( const TDGenerator::ValueType &  vt) const
protected

Checks if the ValueType has a supporting register class.

Parameters
vtValueType to be checked.
Returns
True, if the value type is supported by a register class.

Definition at line 1827 of file TDGen.cc.

1827 {
1828 if (vRegClasses_.find(vt.valueTypeStr()) == vRegClasses_.end()) {
1829 return false;
1830 }
1831
1832 return true;
1833}

References TDGenerator::ValueType::valueTypeStr(), and vRegClasses_.

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◆ immediateOperandNameForEmulatedOperation()

std::string TDGen::immediateOperandNameForEmulatedOperation ( const OperationDAG &  dag,
const Operand &  operand 
)
protected

Returns corresponding immediate operand name for the emulated operation.

Parameters
dagThe emulation code of the emulated operation.
operandThe operand.
Returns
The operand immediate name if found. Otherwise return empty string.

Definition at line 7584 of file TDGen.cc.

7586 {
7587
7588 for (const auto& sourceNode : dag.rootNodes()) {
7589 const TerminalNode* sourceTerminal =
7590 dynamic_cast<TerminalNode*>(sourceNode);
7591
7592 if (sourceTerminal == nullptr) continue;
7593
7594 for (const auto& destEdge : dag.outEdges(*sourceTerminal)) {
7595 const OperationNode* opNode =
7596 dynamic_cast<OperationNode*>(&dag.headNode(*destEdge));
7597
7598 assert(opNode != nullptr &&
7599 "TerminalNode points to other than OperandNode.");
7600 const Operation& operation = opNode->referencedOperation();
7601 ImmInfoKey key = ImmInfo::key(operation, operand);
7602 if (immOperandDefs_.count(key)) {
7603 return immOperandDefs_.at(key);
7604 } else {
7605 return "";
7606 }
7607 }
7608 }
7609 return "";
7610}

References assert, BoostGraph< GraphNode, GraphEdge >::headNode(), immOperandDefs_, ImmInfo::key(), BoostGraph< GraphNode, GraphEdge >::outEdges(), OperationNode::referencedOperation(), and BoostGraph< GraphNode, GraphEdge >::rootNodes().

Referenced by writeEmulationPattern().

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◆ immediatePredicate()

std::string TDGen::immediatePredicate ( int64_t  lowerBoundInclusive,
uint64_t  upperBoundInclusive 
)
protected

Returns llvm predicate expression for short immediate constraint.

Definition at line 7560 of file TDGen.cc.

7562 {
7563
7564 // If can transport any 64-bit imm, no need for any checks.
7565 if (upperBoundInclusive == UINT64_MAX ||
7566 lowerBoundInclusive == INT64_MIN) {
7567 return std::string("(true)");
7568 }
7569
7570 return std::string("(")
7571 + Conversion::toString(lowerBoundInclusive) + "ll"
7572 + " <= Imm && Imm <= "
7573 + Conversion::toString(upperBoundInclusive) + "ll)";
7574}

References Conversion::toString().

Referenced by writeIntegerImmediateDefs(), and writeMoveImmediateDefs().

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◆ initializeBackendContents()

void TDGen::initializeBackendContents ( )
protected

Definition at line 394 of file TDGen.cc.

394 {
395 std::ostringstream registerInfoBuffer;
396 std::ostringstream addressingModeDefsBuffer;
397 std::ostringstream operandDefsBuffer;
398 std::ostringstream instrInfoBuffer;
399 std::ostringstream instrFormatsBuffer;
400 std::ostringstream callingConvBuffer;
401 std::ostringstream argRegsArrayBuffer;
402 std::ostringstream backendCodeBuffer;
403 std::ostringstream topLevelTDBuffer;
404
405 writeRegisterInfo(registerInfoBuffer);
406 writeAddressingModeDefs(addressingModeDefsBuffer);
407 writeOperandDefs(operandDefsBuffer);
408 writeInstrInfo(instrInfoBuffer);
409 writeInstrFormats(instrFormatsBuffer);
410 writeCallingConv(callingConvBuffer);
411 writeArgRegsArray(argRegsArrayBuffer);
412 writeBackendCode(backendCodeBuffer);
413 writeTopLevelTD(topLevelTDBuffer);
414
415 registerInfo_ = registerInfoBuffer.str();
416 addressingModeDefs_ = addressingModeDefsBuffer.str();
417 operandDefs_ = operandDefsBuffer.str();
418 instrInfo_ = instrInfoBuffer.str();
419 instrFormats_ = instrFormatsBuffer.str();
420 callingConv_ = callingConvBuffer.str();
421 argRegsArray_ = argRegsArrayBuffer.str();
422 backendCode_ = backendCodeBuffer.str();
423 topLevelTD_ = topLevelTDBuffer.str();
424}
TDGen::writeInstrFormats
void writeInstrFormats(std::ostream &o)
Definition TDGen.cc:4255
TDGen::writeAddressingModeDefs
void writeAddressingModeDefs(std::ostream &o)
Definition TDGen.cc:8419
TDGen::writeArgRegsArray
void writeArgRegsArray(std::ostream &os)
Definition TDGen.cc:6996
TDGen::writeOperandDefs
void writeOperandDefs(std::ostream &o)
Definition TDGen.cc:621
TDGen::writeTopLevelTD
void writeTopLevelTD(std::ostream &o)
Definition TDGen.cc:4231
TDGen::writeCallingConv
void writeCallingConv(std::ostream &os)
Definition TDGen.cc:6870
TDGen::writeBackendCode
void writeBackendCode(std::ostream &o)
Definition TDGen.cc:3997
TDGen::writeRegisterInfo
bool writeRegisterInfo(std::ostream &o)
Definition TDGen.cc:551

References addressingModeDefs_, argRegsArray_, backendCode_, callingConv_, instrFormats_, instrInfo_, operandDefs_, registerInfo_, topLevelTD_, writeAddressingModeDefs(), writeArgRegsArray(), writeBackendCode(), writeCallingConv(), writeInstrFormats(), writeInstrInfo(), writeOperandDefs(), writeRegisterInfo(), and writeTopLevelTD().

Referenced by TDGen().

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◆ isVectorBitwiseOperation()

bool TDGen::isVectorBitwiseOperation ( const Operation &  op) const
protected

Checks if the given operation is a bitwise operation.

Parameters
opOperation which is checked.
Returns
True, if operation is a bitwise operation.

Definition at line 1995 of file TDGen.cc.

1995 {
1996 abortWithError("WiP");
1997 return false;
1998}

References abortWithError.

Referenced by writeInstrInfo().

◆ isVectorLoadOperation()

bool TDGen::isVectorLoadOperation ( const Operation &  op) const
protected

Checks if the given operation is a vector load memory operation.

Parameters
opOperation which is checked.
Returns
True, if operation is a vector load memory operation.

Definition at line 1965 of file TDGen.cc.

1965 {
1966 abortWithError("WiP");
1967 return false;
1968}

References abortWithError.

Referenced by writeInstrInfo().

◆ isVectorStoreOperation()

bool TDGen::isVectorStoreOperation ( const Operation &  op) const
protected

Checks if the given operation is a vector store memory operation.

Parameters
opOperation which is checked.
Returns
True, if operation is a vector store memory operation.

Definition at line 1977 of file TDGen.cc.

1977 {
1978 abortWithError("WiP");
1979 return false;
1980}

References abortWithError.

Referenced by writeInstrInfo().

◆ isWrongEndianessVectorOp()

bool TDGen::isWrongEndianessVectorOp ( const Operation &  op) const
protected

Definition at line 1983 of file TDGen.cc.

1983 {
1984 abortWithError("WiP");
1985 return false;
1986}

References abortWithError.

◆ llvmOperationName()

TCEString TDGen::llvmOperationName ( const TCEString &  operationName) const
protectedvirtual

Returns llvm operation name for the given OSAL operation name, if any.

Definition at line 5109 of file TDGen.cc.

5109 {
5110
5111 TCEString opName = StringTools::stringToLower(operationName);
5112
5113 if (opName == "add") return "add";
5114 if (opName == "sub") return "sub";
5115 if (opName == "mul") return "mul";
5116 if (opName == "div") return "sdiv";
5117 if (opName == "divu") return "udiv";
5118 if (opName == "mod") return "srem";
5119 if (opName == "modu") return "urem";
5120
5121 if (opName == "add64") return "add";
5122 if (opName == "sub64") return "sub";
5123 if (opName == "mul64") return "mul";
5124 if (opName == "div64") return "sdiv";
5125 if (opName == "divu64") return "udiv";
5126 if (opName == "mod64") return "srem";
5127 if (opName == "modu64") return "urem";
5128
5129 if (opName == "shl") return "shl";
5130 if (opName == "shr") return "sra";
5131 if (opName == "shru") return "srl";
5132 if (opName == "rotl") return "rotl";
5133 if (opName == "rotr") return "rotr";
5134
5135 if (opName == "shl64") return "shl";
5136 if (opName == "shr64") return "sra";
5137 if (opName == "shru64") return "srl";
5138 if (opName == "rotl64") return "rotl";
5139 if (opName == "rotr64") return "rotr";
5140
5141 if (opName == "and") return "and";
5142 if (opName == "ior") return "or";
5143 if (opName == "xor") return "xor";
5144
5145 if (opName == "and64") return "and";
5146 if (opName == "ior64") return "or";
5147 if (opName == "xor64") return "xor";
5148
5149 if (opName == "eq") return "seteq";
5150 if (opName == "eq64") return "seteq";
5151 if (opName == "ne") return "setne";
5152 if (opName == "ne64") return "setne";
5153 if (opName == "lt") return "setlt";
5154 if (opName == "lt64") return "setlt";
5155 if (opName == "le") return "setle";
5156 if (opName == "le64") return "setle";
5157 if (opName == "gt") return "setgt";
5158 if (opName == "gt64") return "setgt";
5159 if (opName == "ge") return "setge";
5160 if (opName == "ltu") return "setult";
5161 if (opName == "ltu64") return "setult";
5162 if (opName == "leu") return "setule";
5163 if (opName == "leu64") return "setule";
5164 if (opName == "gtu") return "setugt";
5165 if (opName == "gtu64") return "setugt";
5166 if (opName == "geu") return "setuge";
5167 if (opName == "geu64") return "setuge";
5168
5169 if (opName == "eqf" || opName == "eqd") return "setoeq";
5170 if (opName == "nef" || opName == "ned") return "setone";
5171 if (opName == "ltf" || opName == "ltd") return "setolt";
5172 if (opName == "lef" || opName == "led") return "setole";
5173 if (opName == "gtf" || opName == "gtd") return "setogt";
5174 if (opName == "gef" || opName == "ged") return "setoge";
5175
5176 if (opName == "equf" || opName == "equd") return "setueq";
5177 if (opName == "neuf" || opName == "neud") return "setune";
5178 if (opName == "ltuf" || opName == "ltud") return "setult";
5179 if (opName == "leuf" || opName == "leud") return "setule";
5180 if (opName == "gtuf" || opName == "gtud") return "setugt";
5181 if (opName == "geuf" || opName == "geud") return "setuge";
5182
5183 if (opName == "ordf" || opName =="ordd") return "seto";
5184 if (opName == "uordf" || opName == "uordd") return "setuo";
5185
5186 if (opName == "addf") return "fadd";
5187 if (opName == "subf") return "fsub";
5188 if (opName == "mulf") return "fmul";
5189 if (opName == "divf") return "fdiv";
5190 if (opName == "absf") return "fabs";
5191 if (opName == "negf") return "fneg";
5192 if (opName == "sqrtf") return "fsqrt";
5193
5194 if (opName == "cif") return "sint_to_fp";
5195 if (opName == "cfi") return "fp_to_sint";
5196 if (opName == "cifu") return "uint_to_fp";
5197 if (opName == "cfiu") return "fp_to_uint";
5198
5199 if (opName == "cfh") return "fpround";
5200 if (opName == "chf") return "fpextend";
5201
5202 if (littleEndian_) {
5203 if (opName == "ld8") return "sextloadi8";
5204 if (opName == "ldu8") return "zextloadi8";
5205 if (opName == "ld16") return "sextloadi16";
5206 if (opName == "ldu16") return "zextloadi16";
5207 if (mach_.is64bit()) {
5208 if (opName == "ld32") return "sextloadi32";
5209 if (opName == "ldu32") return "zextloadi32";
5210 } else {
5211 if (opName == "ld32" || opName =="ldu32") return "load";
5212 }
5213 if (opName == "ld64") return "load";
5214
5215 //if (opName == "ldd") return "load";
5216
5217 if (opName == "st8") return "truncstorei8";
5218 if (opName == "st16") return "truncstorei16";
5219 if (opName == "st32") {
5220 if (mach_.is64bit()) {
5221 return "truncstorei32";
5222 } else {
5223 return "store";
5224 }
5225 }
5226
5227 if (opName == "st32") return "store";
5228 if (opName == "st64") return "store";
5229 //if (opName == "std") return "load";
5230 } else { // big-endian
5231 if (opName == "ldq") return "sextloadi8";
5232 if (opName == "ldqu") return "zextloadi8";
5233 if (opName == "ldh") return "sextloadi16";
5234 if (opName == "ldhu") return "zextloadi16";
5235 if (opName == "ldw") return "load";
5236 //if (opName == "ldd") return "load";
5237
5238 if (opName == "stq") return "truncstorei8";
5239 if (opName == "sth") return "truncstorei16";
5240 if (opName == "stw") return "store";
5241 //if (opName == "std") return "load";
5242 }
5243
5244 if (opName.length() >2 && opName.substr(0,2) == "sx") {
5245 return "sext_inreg";
5246 }
5247
5248 if (opName == "truncwh" || opName == "truncwb" || opName == "trunchb")
5249 return "trunc";
5250
5251 if (opName == "neg") return "ineg";
5252 if (opName == "not") return "not";
5253 if (opName == "cas") return "atomic_cmp_swap_32";
5254
5255 if (opName == "select") return "select";
5256
5257 // Unknown operation name.
5258 return "";
5259}
StringTools::stringToLower
static std::string stringToLower(const std::string &source)
Definition StringTools.cc:160

References TTAMachine::Machine::is64bit(), littleEndian_, mach_, and StringTools::stringToLower().

Referenced by writePortGuardedJumpDefPair().

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◆ llvmOperationPattern()

TCEString TDGen::llvmOperationPattern ( const Operation &  op,
char  operandType = ' ' 
) const
protectedvirtual

Returns LLVM operation pattern for given OSAL operation.

Parameters
opOperation for which the LLVM pattern should be returned.
Returns
Operation pattern in llvm.

Definition at line 4895 of file TDGen.cc.

4895 {
4896 TCEString opName = StringTools::stringToLower(op.name());
4897
4898 if (opName == "add") return "add %1%, %2%";
4899 if (opName == "add64") return "add %1%, %2%";
4900 if (opName == "sub") return "sub %1%, %2%";
4901 if (opName == "sub64") return "sub %1%, %2%";
4902 if (opName == "mul") return "mul %1%, %2%";
4903 if (opName == "mul64") return "mul %1%, %2%";
4904 if (opName == "div") return "sdiv %1%, %2%";
4905 if (opName == "divu") return "udiv %1%, %2%";
4906 if (opName == "div64") return "sdiv %1%, %2%";
4907 if (opName == "divu64") return "udiv %1%, %2%";
4908 if (opName == "mod") return "srem %1%, %2%";
4909 if (opName == "modu") return "urem %1%, %2%";
4910 if (opName == "mod64") return "srem %1%, %2%";
4911 if (opName == "modu64") return "urem %1%, %2%";
4912
4913 if (opName == "shl") return "shl %1%, %2%";
4914 if (opName == "shr") return "sra %1%, %2%";
4915 if (opName == "shru") return "srl %1%, %2%";
4916 if (opName == "rotl") return "rotl %1%, %2%";
4917 if (opName == "rotr") return "rotr %1%, %2%";
4918
4919
4920 if (opName == "shl64") return "shl %1%, %2%";
4921 if (opName == "shr64") return "sra %1%, %2%";
4922 if (opName == "shru64") return "srl %1%, %2%";
4923 if (opName == "rotl64") return "rotl %1%, %2%";
4924 if (opName == "rotr64") return "rotr %1%, %2%";
4925
4926 if (opName == "and") return "and %1%, %2%";
4927 if (opName == "ior") return "or %1%, %2%";
4928 if (opName == "xor") return "xor %1%, %2%";
4929
4930 if (opName == "and64") return "and %1%, %2%";
4931 if (opName == "ior64") return "or %1%, %2%";
4932 if (opName == "xor64") return "xor %1%, %2%";
4933
4934 if (opName == "eq") return "seteq %1%, %2%";
4935 if (opName == "eq64") return "seteq %1%, %2%";
4936 if (opName == "ne") return "setne %1%, %2%";
4937 if (opName == "ne64") return "setne %1%, %2%";
4938 if (opName == "lt") return "setlt %1%, %2%";
4939 if (opName == "lt64") return "setlt %1%, %2%";
4940 if (opName == "le") return "setle %1%, %2%";
4941 if (opName == "le64") return "setle %1%, %2%";
4942 if (opName == "gt") return "setgt %1%, %2%";
4943 if (opName == "gt64") return "setgt %1%, %2%";
4944 if (opName == "ge") return "setge %1%, %2%";
4945 if (opName == "ge64") return "setge %1%, %2%";
4946 if (opName == "ltu") return "setult %1%, %2%";
4947 if (opName == "ltu64") return "setult %1%, %2%";
4948 if (opName == "leu") return "setule %1%, %2%";
4949 if (opName == "leu64") return "setule %1%, %2%";
4950 if (opName == "gtu") return "setugt %1%, %2%";
4951 if (opName == "gtu64") return "setugt %1%, %2%";
4952 if (opName == "geu") return "setuge %1%, %2%";
4953 if (opName == "geu64") return "setuge %1%, %2%";
4954
4955 if (opName == "eqf" || opName == "eqd") return "setoeq %1%, %2%";
4956 if (opName == "nef" || opName == "ned") return "setone %1%, %2%";
4957 if (opName == "ltf" || opName == "ltd") return "setolt %1%, %2%";
4958 if (opName == "lef" || opName == "led") return "setole %1%, %2%";
4959 if (opName == "gtf" || opName == "gtd") return "setogt %1%, %2%";
4960 if (opName == "gef" || opName == "ged") return "setoge %1%, %2%";
4961
4962 if (opName == "equf" || opName == "equd") return "setueq %1%, %2%";
4963 if (opName == "neuf" || opName == "neud") return "setune %1%, %2%";
4964 if (opName == "ltuf" || opName == "ltud") return "setult %1%, %2%";
4965 if (opName == "leuf" || opName == "leud") return "setule %1%, %2%";
4966 if (opName == "gtuf" || opName == "gtud") return "setugt %1%, %2%";
4967 if (opName == "geuf" || opName == "geud") return "setuge %1%, %2%";
4968
4969 if (opName == "ordf" || opName == "ordd") return "seto %1%, %2%";
4970 if (opName == "uordf"|| opName == "uordd")return "setuo %1%, %2%";
4971
4972 if (opName == "addf" || opName == "addd") return "fadd %1%, %2%";
4973 if (opName == "subf" || opName == "subd") return "fsub %1%, %2%";
4974 if (opName == "mulf" || opName == "muld") return "fmul %1%, %2%";
4975 if (opName == "divf" || opName == "divd") return "fdiv %1%, %2%";
4976 if (opName == "absf" || opName == "absd") return "fabs %1%";
4977 if (opName == "negf" || opName == "negd") return "fneg %1%";
4978 if (opName == "sqrtf"|| opName == "sqrtd")return "fsqrt %1%";
4979
4980 if (opName == "cif") return "sint_to_fp %1%";
4981 if (opName == "cfi") return "fp_to_sint %1%";
4982 if (opName == "cifu") return "uint_to_fp %1%";
4983 if (opName == "cfiu") return "fp_to_uint %1%";
4984
4985 if (opName == "cld") return "sint_to_fp %1%";
4986 if (opName == "cdl") return "fp_to_sint %1%";
4987 if (opName == "cldu") return "uint_to_fp %1%";
4988 if (opName == "cdlu") return "fp_to_uint %1%";
4989
4990 if (opName == "cfh" || opName == "cdf") return "fpround %1%";
4991 if (opName == "chf") return "f32 (fpextend %1%)";
4992 if (opName == "cfd") return "f64 (fpextend %1%)";
4993
4994 if (opName == "cih") return "sint_to_fp %1%";
4995 if (opName == "chi") return "i32 (fp_to_sint %1%)";
4996 if (opName == "cihu") return "uint_to_fp %1%";
4997 if (opName == "chiu") return "i32 (fp_to_uint %1%)";
4998
4999 if (opName == "neuh") return "setune %1%, %2%";
5000 if (opName == "eqh") return "setoeq %1%, %2%";
5001 if (opName == "neh") return "setone %1%, %2%";
5002 if (opName == "lth") return "setolt %1%, %2%";
5003 if (opName == "leh") return "setole %1%, %2%";
5004 if (opName == "gth") return "setogt %1%, %2%";
5005 if (opName == "geh") return "setoge %1%, %2%";
5006
5007 if (opName == "ordh") return "seto %1%, %2%";
5008 if (opName == "uordh") return "setuo %1%, %2%";
5009
5010 if (opName == "addh") return "fadd %1%, %2%";
5011 if (opName == "subh") return "fsub %1%, %2%";
5012 if (opName == "mulh") return "fmul %1%, %2%";
5013 if (opName == "divh") return "fdiv %1%, %2%";
5014 if (opName == "absh") return "fabs %1%";
5015 if (opName == "negh") return "fneg %1%";
5016 if (opName == "sqrth") return "fsqrt %1%";
5017
5018 if (opName == "cih") return "sint_to_fp %1%";
5019 if (opName == "chi") return "fp_to_sint %1%";
5020 if (opName == "cihu") return "uint_to_fp %1%";
5021 if (opName == "chiu") return "fp_to_uint %1%";
5022
5023 if (opName == "csh") return "sint_to_fp %1%";
5024 if (opName == "cshu") return "uint_to_fp %1%";
5025 if (opName == "chs") return "fp_to_sint %1%";
5026 if (opName == "chsu") return "fp_to_uint %1%";
5027
5028 if (littleEndian_) {
5029 if (opName == "ld8") return "sextloadi8 %1%";
5030 if (opName == "ldu8") return "zextloadi8 %1%";
5031 if (opName == "ld16") return "sextloadi16 %1%";
5032 if (opName == "ldu16") return "zextloadi16 %1%";
5033 if (mach_.is64bit()) {
5034 if (opName == "ld32") return "sextloadi32 %1%";
5035 if (opName == "ldu32") return "zextloadi32 %1%";
5036 } else {
5037 if (opName == "ld32" || opName == "ldu32") return "load %1%";
5038 }
5039 if (opName == "ld64") return "load %1%";
5040 //if (opName == "ldd") return "load";
5041
5042 if (opName == "st8") return "truncstorei8 %2%, %1%";
5043 if (opName == "st16") return "truncstorei16 %2%, %1%";
5044 if (mach_.is64bit()) {
5045 if (opName == "st32") return "truncstorei32 %2%, %1%";
5046 } else {
5047 if (opName == "st32") return "store %2%, %1%";
5048 }
5049 if (opName == "st64") return "store %2%, %1%";
5050 } else {
5051 if (opName == "ldq") return "sextloadi8 %1%";
5052 if (opName == "ldqu") return "zextloadi8 %1%";
5053 if (opName == "ldh") return "sextloadi16 %1%";
5054 if (opName == "ldhu") return "zextloadi16 %1%";
5055 if (opName == "ldw") return "load %1%";
5056 //if (opName == "ldd") return "load";
5057
5058 if (opName == "stq") return "truncstorei8 %2%, %1%";
5059 if (opName == "sth") return "truncstorei16 %2%, %1%";
5060 if (opName == "stw") return "store %2%, %1%";
5061 //if (opName == "std") return "load";
5062 }
5063
5064 if (opName == "sxw64") {
5065 return "sext_inreg %1%, i32";
5066 }
5067
5068 if (opName == "sxb64") {
5069 return "sext_inreg %1%, i1";
5070 }
5071
5072 if (opName == "sxq64") {
5073 return "sext_inreg %1%, i8";
5074 }
5075 if (opName == "sxh64") {
5076 return "sext_inreg %1%, i16";
5077 }
5078
5079 if (opName == "sxhw") {
5080 return "sext_inreg %1%, i16";
5081 }
5082 if (opName == "sxqw") {
5083 return "sext_inreg %1%, i8";
5084 }
5085
5086 if (opName == "sxw")
5087 return mach_.is64bit() ? "sext_inreg %1%, i64": "sext_inreg %1%, i32";
5088
5089 if (opName == "sxbw") return "sext_inreg %1%, i1";
5090
5091 if (opName == "truncwh" || opName == "truncwb" || opName == "trunchb")
5092 return "trunc %1%";
5093
5094 if (opName == "neg") return "ineg %1%";
5095 if (opName == "not") return "not %1%";
5096
5097 if (opName == "cas") return "atomic_cmp_swap_32 %1%, %2%, %3%";
5098 if (opName == "select") return "select %3%, %1%, %2%";
5099
5100 // Unknown operation name.
5101 return "";
5102}

References TTAMachine::Machine::is64bit(), littleEndian_, mach_, Operation::name(), and StringTools::stringToLower().

Referenced by operationCanBeMatched(), operationNodeToString(), writeEmulationPattern(), writeOperationDef(), and RISCVTDGen::writePatternDefinition().

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◆ operandChar()

char TDGen::operandChar ( Operand &  operand)
protectedvirtual

Returns corresponding character for given operand type.

Parameters
operandOperand under inspection.
Returns
Corresponding character of operand type.

Definition at line 4755 of file TDGen.cc.

4755 {
4756 if (operand.isVector()) {
4757 if (operand.type() == Operand::BOOL) {
4758 return OT_VREG_BOOL;
4759 } else if (operand.type() == Operand::HALF_FLOAT_WORD) {
4760 return OT_VREG_HFP;
4761 } else if (operand.type() == Operand::FLOAT_WORD) {
4762 return OT_VREG_FP;
4763 } else {
4764 if (operand.elementWidth() == 1) {
4765 return OT_VREG_BOOL;
4766 } else if (operand.elementWidth() == 8) {
4767 return OT_VREG_INT8;
4768 } else if (operand.elementWidth() == 16) {
4769 return OT_VREG_INT16;
4770 } else {
4771 return OT_VREG_INT32;
4772 }
4773 }
4774 }
4775
4776 if (operand.type() == Operand::BOOL) {
4777 return OT_REG_BOOL;
4778 } else if (operand.type() == Operand::HALF_FLOAT_WORD) {
4779 return OT_REG_HFP;
4780 } else if (operand.type() == Operand::ULONG_WORD ||
4781 operand.type() == Operand::SLONG_WORD ||
4782 operand.type() == Operand::RAW_DATA) {
4783 return mach_.is64bit() ? OT_REG_LONG : OT_REG_INT;
4784 } else if (operand.type() != Operand::UINT_WORD &&
4785 operand.type() != Operand::SINT_WORD) {
4786 return OT_REG_FP;
4787 } else {
4788 return OT_REG_INT;
4789 }
4790}
Operand::FLOAT_WORD
@ FLOAT_WORD
Definition Operand.hh:61
Operand::HALF_FLOAT_WORD
@ HALF_FLOAT_WORD
Definition Operand.hh:63
TDGen::OT_VREG_INT32
static const char OT_VREG_INT32
Definition TDGen.hh:511
TDGen::OT_VREG_INT16
static const char OT_VREG_INT16
Definition TDGen.hh:510
TDGen::OT_VREG_FP
static const char OT_VREG_FP
Definition TDGen.hh:512
TDGen::OT_VREG_BOOL
static const char OT_VREG_BOOL
Definition TDGen.hh:508
TDGen::OT_VREG_HFP
static const char OT_VREG_HFP
Definition TDGen.hh:513
TDGen::OT_VREG_INT8
static const char OT_VREG_INT8
Definition TDGen.hh:509

References Operand::BOOL, Operand::elementWidth(), Operand::FLOAT_WORD, Operand::HALF_FLOAT_WORD, TTAMachine::Machine::is64bit(), Operand::isVector(), mach_, OT_REG_BOOL, OT_REG_FP, OT_REG_HFP, OT_REG_INT, OT_REG_LONG, OT_VREG_BOOL, OT_VREG_FP, OT_VREG_HFP, OT_VREG_INT16, OT_VREG_INT32, OT_VREG_INT8, Operand::RAW_DATA, Operand::SINT_WORD, Operand::SLONG_WORD, Operand::type(), Operand::UINT_WORD, and Operand::ULONG_WORD.

Referenced by createDefaultOperandTypeString(), emulatingOpNodeLLVMName(), operationCanBeMatched(), writeEmulationPattern(), writeOperationDef(), and RISCVTDGen::writePatternDefinition().

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◆ operandToString()

std::string TDGen::operandToString ( const Operand &  operand,
bool  match,
char  operandType,
const std::string &  immDefName = "" 
)
protectedvirtual

Returns LLVM .td format string for an operand.

Parameters
operandOperand to return string for.
matchTrue, if the string should be in the matching pattern format.
operandTypeCharacter that identifies the type of the operand.
Returns
Operand string to be used in a llvm .td pattern.
Todo:
Vector of pointers once supported. Change operand types for GATHER and SCATTER to be mem-data and mem-address, because that will direct the address operand into this if-clause.

Definition at line 5870 of file TDGen.cc.

5874 {
5875 int idx = operand.index();
5876
5877 if (operand.isVector() && !operand.isAddress()) {
5878 switch (operandType) {
5879 case OT_VREG_BOOL:
5880 case OT_VREG_INT8:
5881 case OT_VREG_INT16:
5882 case OT_VREG_INT32:
5883 case OT_VREG_FP:
5884 case OT_VREG_HFP: {
5885 TCEString regClass = associatedVectorRegisterClass(operand);
5886 return regClass + ":$op" + Conversion::toString(idx);
5887 }
5888 }
5889 }
5890
5891 // from TDGenSIMD: if (operand.isVector && operand.isAddress()
5892 /// @todo Vector of pointers once supported. Change operand types
5893 /// for GATHER and SCATTER to be mem-data and mem-address, because
5894 /// that will direct the address operand into this if-clause.
5895
5896 if (operand.isAddress()) {
5897 switch (operandType) {
5898 case OT_IMM_INT:
5899 case OT_IMM_LONG:
5900 if (match) {
5901 return "MEMri:$op" + Conversion::toString(idx);
5902 } else {
5903 return "ADDRri:$op" + Conversion::toString(idx);
5904 }
5905 case OT_REG_INT:
5906 case OT_REG_LONG:
5907 if (match) {
5908 return "MEMrr:$op" + Conversion::toString(idx);
5909 } else {
5910 return "ADDRrr:$op" + Conversion::toString(idx);
5911 }
5912 default:
5913 std::string msg =
5914 "invalid operation type for mem operand:";
5915 msg += operandType;
5916 throw InvalidData(__FILE__, __LINE__, __func__, msg);
5917 }
5918 } else if (operand.type() == Operand::SINT_WORD ||
5919 operand.type() == Operand::UINT_WORD ||
5920 operand.type() == Operand::RAW_DATA ||
5921 operand.type() == Operand::BOOL) {
5922
5923 // imm
5924 switch (operandType) {
5925 case OT_IMM_LONG:
5926 if (match) {
5927 return "i64imm:$op" + Conversion::toString(idx);
5928 } else {
5929 return "(i64 imm:$op" + Conversion::toString(idx) + ")";
5930 }
5931 case OT_IMM_INT:
5932 assert(!immDefName.empty() &&
5933 "No immediate operand defined for the operand.");
5934 return immDefName + ":$op" + Conversion::toString(idx);
5935 case OT_IMM_BOOL:
5936 if (match) {
5937 return "i1imm:$op" + Conversion::toString(idx);
5938 } else {
5939 return "(i1 imm:$op" + Conversion::toString(idx) + ")";
5940 }
5941 case OT_REG_INT:
5942 return mach_.is64bit() ?
5943 "R64IRegs:$op" + Conversion::toString(idx):
5944 "R32IRegs:$op" + Conversion::toString(idx);
5945 case OT_REG_LONG:
5946 return "R64IRegs:$op" + Conversion::toString(idx);
5947 case OT_REG_BOOL:
5948 return "R1Regs:$op" + Conversion::toString(idx);
5949 case OT_REG_FP:
5950 if (operand.type() == Operand::RAW_DATA) {
5951 return "FPRegs:$op" + Conversion::toString(idx);
5952 }
5953 /* fall through */
5954 case OT_REG_HFP:
5955 if (operand.type() == Operand::RAW_DATA) {
5956 return "HFPRegs:$op" + Conversion::toString(idx);
5957 }
5958 /* fall through */
5959 default:
5960 std::string msg =
5961 "invalid operation type for integer operand:";
5962 msg += operandType;
5963 throw InvalidData(__FILE__, __LINE__, __func__, msg);
5964 }
5965 } else if (operand.type() == Operand::FLOAT_WORD ) {
5966
5967 switch (operandType) {
5968 case OT_IMM_INT:
5969 case OT_IMM_FP:
5970 if (match) {
5971 return "f32imm:$op" + Conversion::toString(idx);
5972 } else {
5973 return "(f32 fpimm:$op" + Conversion::toString(idx) + ")";
5974 }
5975 case OT_REG_INT:
5976 case OT_REG_FP:
5977 return "FPRegs:$op" + Conversion::toString(idx);
5978
5979 default:
5980 std::string msg =
5981 "invalid operation type for float operand:";
5982 msg += operandType;
5983 throw InvalidData(__FILE__, __LINE__, __func__, msg);
5984 }
5985 } else if (operand.type() == Operand::HALF_FLOAT_WORD) {
5986
5987 switch (operandType) {
5988 case OT_IMM_INT:
5989 case OT_IMM_FP:
5990 case OT_IMM_HFP:
5991 if (match) {
5992 return "f16imm:$op" + Conversion::toString(idx);
5993 } else {
5994 return "(f16 fpimm:$op" + Conversion::toString(idx) + ")";
5995 }
5996 case OT_REG_INT:
5997 case OT_REG_HFP:
5998 return "HFPRegs:$op" + Conversion::toString(idx);
5999 default:
6000 std::string msg =
6001 "invalid operation type for half operand:";
6002 msg += operandType;
6003 throw InvalidData(__FILE__, __LINE__, __func__, msg);
6004 }
6005 } else if (operand.type() == Operand::DOUBLE_WORD) {
6006 // TODO: immediate check??
6007 return "R64DFPRegs:$op" + Conversion::toString(idx);
6008 } else if (operand.type() == Operand::SLONG_WORD ||
6009 operand.type() == Operand::ULONG_WORD) {
6010 if (operandType == OT_REG_BOOL) {
6011 return "R1Regs:$op" + Conversion::toString(idx);
6012 }
6013 if (operandType == OT_IMM_BOOL) {
6014 if (match) {
6015 return "i1imm:$op" + Conversion::toString(idx);
6016 } else {
6017 return "(i1 imm:$op" + Conversion::toString(idx) + ")";
6018 }
6019 }
6020 if (operandType == OT_IMM_LONG) {
6021 return match ?
6022 "i64imm:$op" + Conversion::toString(idx) :
6023 "(i64 imm:$op" + Conversion::toString(idx) + ")";
6024 }
6025 return mach_.is64bit() ?
6026 "R64IRegs:$op" + Conversion::toString(idx):
6027 "R32IRegs:$op" + Conversion::toString(idx);
6028 } else {
6029 std::cerr << "Unknown operand type: " << operandType << std::endl;
6030 assert(false && "Unknown operand type.");
6031 }
6032 abortWithError("Unknown operand type on osal? Should not get here.");
6033 return "";
6034}
Operand::DOUBLE_WORD
@ DOUBLE_WORD
Definition Operand.hh:62
TDGen::associatedVectorRegisterClass
TCEString associatedVectorRegisterClass(const Operand &operand) const
Definition TDGen.cc:1842

References __func__, abortWithError, assert, associatedVectorRegisterClass(), Operand::BOOL, Operand::DOUBLE_WORD, Operand::FLOAT_WORD, Operand::HALF_FLOAT_WORD, Operand::index(), TTAMachine::Machine::is64bit(), Operand::isAddress(), Operand::isVector(), mach_, OT_IMM_BOOL, OT_IMM_FP, OT_IMM_HFP, OT_IMM_INT, OT_IMM_LONG, OT_REG_BOOL, OT_REG_FP, OT_REG_HFP, OT_REG_INT, OT_REG_LONG, OT_VREG_BOOL, OT_VREG_FP, OT_VREG_HFP, OT_VREG_INT16, OT_VREG_INT32, OT_VREG_INT8, Operand::RAW_DATA, Operand::SINT_WORD, Operand::SLONG_WORD, Conversion::toString(), Operand::type(), Operand::UINT_WORD, and Operand::ULONG_WORD.

Referenced by dagNodeToString(), patInputs(), patOutputs(), and writeEmulationPattern().

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◆ operandTypesToRegisters()

std::string TDGen::operandTypesToRegisters ( const std::string &  opdTypes) const
protected

Definition at line 7885 of file TDGen.cc.

7885 {
7886 std::string result(opdTypes);
7887 for (char& type : result) {
7888 type = operandTypeToRegister(type);
7889 }
7890 return result;
7891}

References operandTypeToRegister().

Referenced by getLLVMPatternWithConstants().

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◆ operandTypeToRegister()

char TDGen::operandTypeToRegister ( const char &  opdType) const
protected

Definition at line 7894 of file TDGen.cc.

7894 {
7895 switch (opdType) {
7896 case OT_IMM_INT: return OT_REG_INT; // Integer immediate.
7897 case OT_IMM_BOOL: return OT_REG_BOOL; // Boolean immediate.
7898 case OT_IMM_FP: return OT_REG_FP; // 32-bit floating point immediate.
7899 case OT_IMM_HFP: return OT_REG_HFP; // 15-bi floating point immediate.
7900 // TODO: vector immediate types.
7901 default:
7902 break;
7903 }
7904 return opdType; // Return as is (should be register type).
7905}

References OT_IMM_BOOL, OT_IMM_FP, OT_IMM_HFP, OT_IMM_INT, OT_REG_BOOL, OT_REG_FP, OT_REG_HFP, and OT_REG_INT.

Referenced by getLLVMPatternWithConstants(), getMovePattern(), and operandTypesToRegisters().

◆ operationCanBeMatched()

bool TDGen::operationCanBeMatched ( const Operation &  op,
std::set< std::string > *  recursionCycleCheck = NULL,
bool  recursionHasStore = false 
)
protected

Check if operation can be matched with llvm pattern.

Check if operation has llvmOperationPatters or one of it's DAGs contain only operations, which can be matched.

Definition at line 5281 of file TDGen.cc.

5283 {
5284
5285 // LLVM does not support operations with >255 inputs.
5286 if (op.numberOfInputs() > 255) {
5287 return false;
5288 }
5289 // TODO: this should have been changed?
5290 char operandChar = mach_.is64bit() ? OT_REG_LONG : OT_REG_INT;
5291 // if operation has llvm pattern
5292 if (llvmOperationPattern(op,operandChar) != "") {
5293 return true;
5294 }
5295
5296 std::set<std::string> useSet;
5297 if (recursionCycleCheck != NULL) {
5298 useSet = *recursionCycleCheck;
5299 }
5300 useSet.insert(op.name());
5301
5302 // check if one of dags of operation is ok
5303 for (int i = 0; i < op.dagCount(); i++) {
5304 OperationDAG& dag = op.dag(i);
5305 if (operationDAGCanBeMatched(dag, &useSet, recursionHasStore)) {
5306 return true;
5307 }
5308 }
5309
5310 return false;
5311}
TDGen::llvmOperationPattern
virtual TCEString llvmOperationPattern(const Operation &op, char operandType=' ') const
Definition TDGen.cc:4895

References Operation::dag(), Operation::dagCount(), TTAMachine::Machine::is64bit(), llvmOperationPattern(), mach_, Operation::name(), Operation::numberOfInputs(), operandChar(), operationDAGCanBeMatched(), OT_REG_INT, and OT_REG_LONG.

Referenced by operationDAGCanBeMatched(), writeInstrInfo(), and RISCVTDGen::writePatternDefinition().

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◆ operationDAGCanBeMatched()

bool TDGen::operationDAGCanBeMatched ( const OperationDAG &  op,
std::set< std::string > *  recursionCycleCheck = NULL,
bool  recursionHasStore = false 
)
protected

Definition at line 5315 of file TDGen.cc.

5318 {
5319
5320 bool hasStore = false;
5321
5322 for (int j = 0; j < opDag.nodeCount(); j++) {
5323 OperationNode* opNode = dynamic_cast<OperationNode*>(&opDag.node(j));
5324 if (opNode) {
5325 Operation& refOp = opNode->referencedOperation();
5326 if (refOp.writesMemory()) {
5327 if (recursionHasStore || hasStore) {
5328 return false;
5329 } else {
5330 hasStore = true;
5331 }
5332 }
5333
5334 // check that the same operation is not used recursively
5335 if (recursionCycleCheck &&
5336 recursionCycleCheck->count(refOp.name()) != 0) {
5337 return false;
5338 }
5339
5340 // check if referenced op can be matched
5341 if (!operationCanBeMatched(refOp, recursionCycleCheck,
5342 hasStore)) {
5343 return false;
5344 }
5345 }
5346 }
5347 return true;
5348}
Operation::writesMemory
virtual bool writesMemory() const
Definition Operation.cc:252
TDGen::operationCanBeMatched
bool operationCanBeMatched(const Operation &op, std::set< std::string > *recursionCycleCheck=NULL, bool recursionHasStore=false)
Definition TDGen.cc:5281

References Operation::name(), BoostGraph< GraphNode, GraphEdge >::node(), BoostGraph< GraphNode, GraphEdge >::nodeCount(), operationCanBeMatched(), OperationNode::referencedOperation(), and Operation::writesMemory().

Referenced by getMatchableOperationDAG(), getMatchableOperationDAGs(), and operationCanBeMatched().

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◆ operationNodeToString()

std::string TDGen::operationNodeToString ( const Operation &  op,
const OperationDAG &  dag,
const OperationNode &  node,
bool  emulationPattern,
const std::string &  operandTypes 
)
protected

Converts OSAL dag operation node to llvm .td pattern fragment string.

Parameters
opOperation which this operation node is part of.
dagParent DAG of the operation node.
nodeNode to convert to string.
immOpIndex of an operand to define as immediate or 0 if none.
emulationPatternTrue, if the string should be in emulation pattern format.

Definition at line 5785 of file TDGen.cc.

5787 {
5788 const Operation& operation = node.referencedOperation();
5789
5790 std::string operationPat;
5791
5792 if (emulationPattern) {
5793 operationPat = emulatingOpNodeLLVMName(
5794 op, dag, node, operandTypes);
5795
5796 for (int i = 0; i < operation.numberOfInputs(); i++) {
5797 if (i > 0) {
5798 operationPat += ", ";
5799 } else {
5800 operationPat += " ";
5801 }
5802 operationPat =
5803 operationPat + "%" + Conversion::toString(i + 1) + "%";
5804 }
5805 } else {
5806 operationPat = llvmOperationPattern(operation, operandTypes[0]);
5807
5808 // generate pattern for operation if not llvmOperation (can match
5809 // custom op patterns)
5810 if (operationPat == "") {
5811 auto* dagToUse = getMatchableOperationDAG(operation);
5812 if (dagToUse) {
5813 return subPattern(operation, *dagToUse);
5814 } else {
5815 operationPat = tceOperationPattern(operation);
5816 }
5817 }
5818 }
5819
5820 if (operationPat == "") {
5821 std::string msg("Unknown operation node in dag: " +
5822 std::string(operation.name()));
5823
5824 throw InvalidData(__FILE__, __LINE__, __func__, msg);
5825 }
5826
5827 boost::format pattern(operationPat);
5828
5829 int inputs = operation.numberOfInputs();
5830#ifndef NDEBUG
5831 int outputs =
5832#endif
5833 operation.numberOfOutputs();
5834
5835 assert(outputs == 0 || outputs == 1);
5836
5837 for (int i = 1; i < inputs + 1; i++) {
5838 for (int e = 0; e < dag.inDegree(node); e++) {
5839 const OperationDAGEdge& edge = dag.inEdge(node, e);
5840 int dst = edge.dstOperand();
5841 if (dst == i) {
5842 const OperationDAGNode& in = dag.tailNode(edge);
5843 std::string dagNodeString = dagNodeToString(
5844 op, dag, in, emulationPattern, operandTypes,
5845 &operation, &node);
5846 try {
5847 pattern % dagNodeString;
5848 } catch(...) {
5849 TCEString msg = "Boost format threw exception! ";
5850 msg << "Input format: " << operationPat;
5851 throw InvalidData(__FILE__, __LINE__, __func__, msg);
5852 }
5853 }
5854 }
5855 }
5856
5857 return std::string("(") + pattern.str() + ")";
5858}
TDGen::subPattern
std::string subPattern(const Operation &op, const OperationDAG &dag)
Definition TDGen.cc:5468
TDGen::tceOperationPattern
std::string tceOperationPattern(const Operation &op)
Definition TDGen.cc:5266
TDGen::emulatingOpNodeLLVMName
std::string emulatingOpNodeLLVMName(const Operation &op, const OperationDAG &dag, const OperationNode &node, const std::string &operandTypes)
Definition TDGen.cc:5674
TDGen::getMatchableOperationDAG
const OperationDAG * getMatchableOperationDAG(const Operation &op)
Definition TDGen.cc:5361

References __func__, assert, dagNodeToString(), OperationDAGEdge::dstOperand(), emulatingOpNodeLLVMName(), getMatchableOperationDAG(), BoostGraph< GraphNode, GraphEdge >::inDegree(), BoostGraph< GraphNode, GraphEdge >::inEdge(), llvmOperationPattern(), Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), OperationNode::referencedOperation(), subPattern(), BoostGraph< GraphNode, GraphEdge >::tailNode(), tceOperationPattern(), and Conversion::toString().

Referenced by dagNodeToString().

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◆ operationPattern()

std::string TDGen::operationPattern ( const Operation &  op,
const OperationDAG &  dag,
const std::string &  operandTypes 
)
protected

Returns operation pattern in llvm .td format.

Parameters
opOperation to return pattern for.
dagOperation pattern's DAG.
immOpIndex of an operand to define as an immediate operand, or 0, if all operands should be in registers.
Returns
Pattern string.

Definition at line 5421 of file TDGen.cc.

5424 {
5425
5426 std::string retVal;
5427 for (OperationDAG::NodeSet::iterator i = dag.endNodes().begin();
5428 i != dag.endNodes().end(); ++i) {
5429 if (i != dag.endNodes().begin()) {
5430 retVal += ",";
5431 }
5432 const OperationDAGNode& res = **(i);
5433 retVal += dagNodeToString(op, dag, res, false, operandTypes);
5434 }
5435 return retVal;
5436}
OperationDAG::endNodes
const OperationDAG::NodeSet & endNodes() const
Definition OperationDAG.cc:137

References dagNodeToString(), and OperationDAG::endNodes().

Referenced by writeOperationDef(), and RISCVTDGen::writePatternDefinition().

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◆ orderEqualWidthRegistersToRoundRobin()

void TDGen::orderEqualWidthRegistersToRoundRobin ( )
protected

Sets registers to use round robin order in register allocation.

Starting from register index number 0, all same width registers having the same index number are pushed to a vector. Then, index is increased by one and same action is performed, index increased etc., until all registers of same width are pushed to the vector. Then, the vector is used to replace old register order.

For example, two register files R64_1 (register indices 0, 1, 2 and 3) and R64_2 (register indices 0, 1) are ordered as: R64_1(0), R64_2(0), R64_1(1), R64_2(1), R64_1(2), R64_1(3), and LLVM register allocator will use this order to allocate the registers.

Definition at line 1674 of file TDGen.cc.

1674 {
1675 std::vector<RegisterInfo> roundRobinOrder;
1676
1677 // Loop through every different group of register widths.
1678 std::map<int, std::vector<RegisterInfo>>::iterator it;
1679 for (it = registers_.begin(); it != registers_.end(); ++it) {
1680 roundRobinOrder.clear();
1681 std::vector<RegisterInfo>& registers = it->second;
1682
1683 unsigned i = 0;
1684 unsigned idx = 0;
1685
1686 // Loop until all registers of same width are reordered.
1687 while (roundRobinOrder.size() != registers.size()) {
1688 RegisterInfo& info = registers[i];
1689 if (info.regIndex_ == idx) {
1690 roundRobinOrder.push_back(info);
1691 }
1692
1693 if (i == registers.size() - 1) {
1694 i = 0;
1695 ++idx;
1696 } else {
1697 ++i;
1698 }
1699 }
1700
1701 registers = roundRobinOrder;
1702 }
1703}
TDGenerator::RegisterInfo::regIndex_
unsigned regIndex_
Register index in the register file.
Definition TDGen.hh:673

References TDGenerator::RegisterInfo::regIndex_, and registers_.

Referenced by analyzeMachineRegisters().

◆ patInputs()

std::string TDGen::patInputs ( const Operation &  op,
const std::string &  inputTypes 
)
protected

Returns llvm input definition list for an operation.

Parameters
opOperation to define inputs for.
Returns
String defining operation inputs in llvm .td format.

Definition at line 6043 of file TDGen.cc.

6043 {
6044
6045 std::string ins;
6046 for (int i = 0; i < op.numberOfInputs(); i++) {
6047 if (i > 0) {
6048 ins += ", ";
6049 }
6050
6051 char inputType = inputTypes[i + op.numberOfOutputs()];
6052 std::string immDef("");
6053 // NOTE: !op.operand(i+1).isAddress() is kludge fix for MEMri/ADDri
6054 // operands. They do not have immediate operand definitions (yet).
6055 if (inputType == OT_IMM_INT && !op.operand(i+1).isAddress()) {
6056 assert(immOperandDefs_.count(
6057 ImmInfo::key(op, op.operand(i+1)))
6058 && "Missing immediate operand definition for the operand.");
6059 immDef = immOperandDefs_[ImmInfo::key(op, op.operand(i+1))];
6060 }
6061 ins += operandToString(op.operand(i + 1), true, inputType, immDef);
6062 }
6063 return ins;
6064}

References assert, immOperandDefs_, Operand::isAddress(), ImmInfo::key(), Operation::numberOfInputs(), Operation::numberOfOutputs(), Operation::operand(), operandToString(), and OT_IMM_INT.

Referenced by writeOperationDef().

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◆ patOutputs()

std::string TDGen::patOutputs ( const Operation &  op,
const std::string &  operandTypes 
)
protected

Returns llvm output definition list for an operation.

Parameters
opOperation to define outputs for.
Returns
String defining operation outputs in llvm .td format.

Definition at line 6074 of file TDGen.cc.

6074 {
6075 std::string outs;
6076 for (int i = 0; i < op.numberOfOutputs(); i++) {
6077 assert(op.operand(op.numberOfInputs() + 1 + i).isOutput());
6078 outs += (i > 0) ? (",") : (" ");
6079 outs += operandToString(
6080 op.operand(op.numberOfInputs() + 1 + i), true, operandTypes[i]);
6081 }
6082 return outs;
6083}

References assert, Operand::isOutput(), Operation::numberOfInputs(), Operation::numberOfOutputs(), Operation::operand(), and operandToString().

Referenced by writeOperationDef().

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◆ saveAdditionalVectorOperationInfo()

void TDGen::saveAdditionalVectorOperationInfo ( const Operation &  op,
const TCEString &  valueTypes,
bool  isRegisterOp 
)
protected

Saves information of some operations.

Additional information of some operations is needed later, and thus, they need to be saved for later reference.

Parameters
opVector operation.
valueTypesOperand value type identifier characters.
isRegisterOpIf false, operation has immediate operands.

Definition at line 2246 of file TDGen.cc.

2247 {
2248 abortWithError("WiP");
2249}

References abortWithError.

Referenced by writeVectorOperationDef().

◆ subPattern()

std::string TDGen::subPattern ( const Operation &  op,
const OperationDAG &  dag 
)
protected

Return operation pattern is llvm .td format without outputs.

This pattern can be used as sub-pattern of bigger pattern. The operation must have only one output.

Parameters
opOperation to return pattern for.
dagOperation pattern's DAG.
Returns
Pattern string.

Definition at line 5468 of file TDGen.cc.

5470 {
5471
5472 if (dag.endNodes().size() != 1) {
5473 throw InvalidData(
5474 __FILE__,__LINE__,__func__,
5475 "Cannot create subpattern: not exactly 1 end node!");
5476 }
5477
5478 OperationDAG::NodeSet::iterator i = dag.endNodes().begin();
5479 const OperationDAGNode& res = **(i);
5480 OperationDAG::NodeSet preds = dag.predecessors(res);
5481 if (preds.size() != 1) {
5482 throw InvalidData(
5483 __FILE__,__LINE__,__func__,
5484 "Cannot create subpattern: not single data source for end node.");
5485 }
5486
5487 std::string operandTypes = createDefaultOperandTypeString(op);
5488 // TODO: what about immediate operands?
5489
5490 // TODO: size of the operand string?
5491 return dagNodeToString(
5492 op, dag, **(preds.begin()), false, operandTypes);
5493}
TDGen::createDefaultOperandTypeString
std::string createDefaultOperandTypeString(const Operation &op)
Definition TDGen.cc:5439

References __func__, createDefaultOperandTypeString(), dagNodeToString(), OperationDAG::endNodes(), and BoostGraph< GraphNode, GraphEdge >::predecessors().

Referenced by operationNodeToString().

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◆ subwordWidthOfRawData()

int TDGen::subwordWidthOfRawData ( const Operation &  op) const
protected

Returns subword width of vector operands of "raw" type.

Note
This function chooses the subword width based on subword width of the WIDEST "raw" data operand that can be found from the operation, since that approach works for current SIMD operation definitions. If this approach doesn't work for your operation, modify the function properly to fulfil your needs.
Parameters
opOperation that has raw operands.
Returns
Subword width of the raw vector operands.

Definition at line 1778 of file TDGen.cc.

1778 {
1779 int widestWidth = -1;
1780 int widestRawOperandIndex = -1;
1781 for (int i = 1; i <= op.operandCount(); ++i) {
1782 const Operand& operand = op.operand(i);
1783 if (operand.type() == Operand::RAW_DATA && operand.isVector()) {
1784 if (operand.width() > widestWidth) {
1785 widestWidth = operand.width();
1786 widestRawOperandIndex = i;
1787 }
1788 }
1789 }
1790
1791 if (widestRawOperandIndex >= 0) {
1792 return op.operand(widestRawOperandIndex).elementWidth();
1793 }
1794
1795 assert(false && "Invalid input operation.");
1796}
Operand::width
virtual int width() const
Definition Operand.cc:318

References assert, Operand::elementWidth(), Operand::isVector(), Operation::operand(), Operation::operandCount(), Operand::RAW_DATA, Operand::type(), and Operand::width().

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◆ supportedStackAccessOperations()

std::vector< std::string > TDGen::supportedStackAccessOperations ( const TTAMachine::Machine &  mach)
staticprotected

Returns OSAL operation names valid for stack accesses.

Parameters
machThe target machine.

Definition at line 7685 of file TDGen.cc.

7685 {
7686
7687 using namespace TTAMachine;
7688
7689 std::vector<std::string> opcodes;
7690
7691 auto collectMemoryOps = [](
7692 std::vector<std::string>& newOpcodes,
7693 const FunctionUnit& fu) -> void {
7694
7695 for (int i = 0; i < fu.operationCount(); i++) {
7696 const Operation& op = MachineInfo::osalOperation(*fu.operation(i));
7697 if (!op.readsMemory() && !op.writesMemory()) {
7698 continue;
7699 }
7700 newOpcodes.push_back(StringTools::stringToUpper(op.name()));
7701 }
7702 };
7703
7704 std::map<const AddressSpace*, std::set<const FunctionUnit*>>
7705 addrSpaceLsuMap;
7706 for (const FunctionUnit* fu : mach.functionUnitNavigator()) {
7707 if (fu->hasAddressSpace()) {
7708 addrSpaceLsuMap[fu->addressSpace()].insert(fu);
7709 }
7710 }
7711
7712 const int stackAddressSpaceId = 0;
7713 if (addrSpaceLsuMap.size() == 1) {
7714 // Only one data address space. Stack resides there.
7715 for (auto lsu : addrSpaceLsuMap.begin()->second) {
7716 collectMemoryOps(opcodes, *lsu);
7717 }
7718 } else {
7719 // Multiple data address spaces. Find LSUs having the stack address
7720 // space ID.
7721 for (auto asLsusPair : addrSpaceLsuMap) {
7722 if (asLsusPair.first->hasNumericalId(stackAddressSpaceId)) {
7723 for (auto lsu : asLsusPair.second) {
7724 collectMemoryOps(opcodes, *lsu);
7725 }
7726 break;
7727 }
7728 }
7729 }
7730
7731 return opcodes;
7732}
MachineInfo::osalOperation
static Operation & osalOperation(const TTAMachine::HWOperation &hwOp)
Definition MachineInfo.cc:794
Operation::readsMemory
virtual bool readsMemory() const
Definition Operation.cc:242

References TTAMachine::Machine::functionUnitNavigator(), Operation::name(), MachineInfo::osalOperation(), Operation::readsMemory(), StringTools::stringToUpper(), and Operation::writesMemory().

Referenced by writeBackendCode().

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◆ tceOperationPattern()

std::string TDGen::tceOperationPattern ( const Operation &  op)
protected

Pattern for tce generated custom op patterns.

Definition at line 5266 of file TDGen.cc.

5266 {
5267 std::string opList = "";
5268 for (int i = 0; i < op.numberOfInputs(); i++) {
5269 opList += " %" + Conversion::toString(i+1) + "%";
5270 }
5271 return op.name() + opList;
5272}

References Operation::name(), Operation::numberOfInputs(), and Conversion::toString().

Referenced by operationNodeToString().

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◆ verbose()

void TDGen::verbose ( const TCEString &  msg) const
protected

Prints debugging information if verbose switch is used.

Parameters
msgDebug message.

Definition at line 1862 of file TDGen.cc.

1862 {
1863 if (Application::verboseLevel() > Application::VERBOSE_LEVEL_DEFAULT) {
1864 Application::logStream() << msg << endl;
1865 }
1866}

References Application::logStream(), Application::VERBOSE_LEVEL_DEFAULT, and Application::verboseLevel().

Referenced by analyzeMachineVectorRegisterClasses(), genGeneratedTCEPlugin_getLoad(), genGeneratedTCEPlugin_getStore(), writeCallingConv(), and writeVectorOperationDef().

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◆ write16bitRegisterInfo()

void TDGen::write16bitRegisterInfo ( std::ostream &  o)
protected

Writes 16-bit register definitions to the output stream.

Definition at line 1211 of file TDGen.cc.

1211 {
1212 // --- Hardcoded reserved registers. ---
1213 writeRegisterDef(o, regs16bit_[0], "HIRES0", "R16", "", RESULT);
1214
1215 // -------------------------------------
1216
1217 for (unsigned i = 1; i < regs16bit_.size(); i++) {
1218 std::string regName = "H" + Conversion::toString(i);
1219 writeRegisterDef(o, regs16bit_[i], regName, "R16", "", GPR);
1220 }
1221
1222 o << std::endl;
1223
1224 // All 16-bit regs.
1225 for (RegClassMap::iterator ri = regsInClasses_.begin();
1226 ri != regsInClasses_.end(); ri++) {
1227 // go through all 1-bit RF classes
1228 if (ri->first.find("R16") == 0) {
1229 o << "def " << ri->first
1230 << "Regs : RegisterClass<\"TCE\", [i16], 32, (add ";
1231 o << ri->second[0];
1232 for (unsigned i = 1; i < ri->second.size(); i++) {
1233 o << " , " << ri->second[i];
1234 }
1235 o << ")>;" << std::endl;
1236 }
1237 }
1238 o << std::endl;
1239
1240 for (RegClassMap::iterator ri = regsInClasses_.begin();
1241 ri != regsInClasses_.end(); ri++) {
1242 // go through all 1-bit RF classes
1243 if (ri->first.find("R16") == 0) {
1244 o << "def " << ri->first
1245 << "IRegs : RegisterClass<\"TCE\", [i16], 32, (add ";
1246 o << ri->second[0];
1247 for (unsigned i = 1; i < ri->second.size(); i++) {
1248 o << " , " << ri->second[i];
1249 }
1250 o << ")>;" << std::endl;
1251 }
1252 }
1253 o << std::endl;
1254
1255 // floating-point-versions of these
1256
1257 for (RegClassMap::iterator ri = regsInClasses_.begin();
1258 ri != regsInClasses_.end(); ri++) {
1259 // go through all 1-bit RF classes
1260 if (ri->first.find("R16") == 0) {
1261 o << "def " << ri->first
1262 << "FPRegs : RegisterClass<\"TCE\", [f16], 32, (add ";
1263 o << ri->second[0];
1264 for (unsigned i = 1; i < ri->second.size(); i++) {
1265 o << " , " << ri->second[i];
1266 }
1267 o << ")>;" << std::endl;
1268 }
1269 }
1270
1271 o << std::endl;
1272}
TDGen::writeRegisterDef
void writeRegisterDef(std::ostream &o, const RegInfo &reg, const std::string regName, const std::string regTemplate, const std::string aliases, RegType type)
Definition TDGen.cc:503

References GPR, regs16bit_, regsInClasses_, RESULT, Conversion::toString(), and writeRegisterDef().

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◆ write1bitRegisterInfo()

void TDGen::write1bitRegisterInfo ( std::ostream &  o)
protected

Writes 1-bit register definitions to the output stream.

Definition at line 961 of file TDGen.cc.

961 {
962 if (regs1bit_.size() < 1) {
963 RegInfo reg = {"dummy1", 0};
964 std::string name = "I1DUMMY";
965 writeRegisterDef(o, reg, name, "R1", "", RESERVED);
966 } else {
967 for (unsigned i = 0; i < regs1bit_.size(); i++) {
968 std::string regName = "B" + Conversion::toString(i);
969 writeRegisterDef(o, regs1bit_[i], regName, "R1", "", GPR);
970 }
971 }
972
973 int stackSize = mach_.is64bit() ? 64 : 32;
974 for (RegClassMap::iterator ri = regsInClasses_.begin();
975 ri != regsInClasses_.end(); ri++) {
976 // go through all 1-bit RF classes
977 if (ri->first.find("R1") == 0) {
978 o << std::endl
979 << "def " << ri->first << "Regs : RegisterClass<\"TCE\", [i1]"
980 << ", " << stackSize << ", (add ";
981 o << ri->second[0];
982 for (unsigned i = 1; i < ri->second.size(); i++) {
983 o << " , " << ri->second[i];
984 }
985 o << ")> {" << std::endl
986 << " let Size=" << stackSize << ";" << std::endl
987 << "}" << std::endl;
988 }
989 }
990}

References GPR, TTAMachine::Machine::is64bit(), mach_, regs1bit_, regsInClasses_, RESERVED, Conversion::toString(), and writeRegisterDef().

Referenced by writeRegisterInfo().

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◆ write32bitRegisterInfo()

void TDGen::write32bitRegisterInfo ( std::ostream &  o)
protected

Definition at line 1021 of file TDGen.cc.

1021 {
1022
1023 std::string i32regs;
1024 size_t i = 0;
1025
1026 if (!mach_.is64bit()) {
1027 // --- Hardcoded reserved registers. ---
1028 writeRegisterDef(o, regs32bit_[0], "SP", "R32", "", RESERVED);
1029 writeRegisterDef(o, regs32bit_[1], "IRES0", "R32", "", RESULT);
1030 writeRegisterDef(o, regs32bit_[2], "FP", "R32", "", RESERVED);
1031
1032 if (prebypassStackIndeces_) {
1033 writeRegisterDef(
1034 o, regs32bit_[3], "KLUDGE_REGISTER", "R32", "", GPR);
1035 } else {
1036 writeRegisterDef(
1037 o, regs32bit_[3], "KLUDGE_REGISTER", "R32", "", RESERVED);
1038 }
1039
1040 i32regs = "SP, IRES0, FP, KLUDGE_REGISTER";
1041
1042 //after the loop, i will have the index of first non-special reg.
1043 for (i = 4;
1044 i < std::min((size_t)argRegCount_ + 3, regs32bit_.size());
1045 i++) {
1046 std::string regName = "A" + Conversion::toString(i);
1047 writeRegisterDef(o, regs32bit_[i], regName, "R32", "", ARGUMENT);
1048 i32regs += ", ";
1049 i32regs += regName;
1050 }
1051 }
1052
1053 if (regs32bit_.size() < 1) {
1054 RegInfo reg = { "dummy32", 0 };
1055 writeRegisterDef(o, reg, "dummy32", "R64", "", RESERVED);
1056 o << "def R32Regs : RegisterClass<\"TCE\", [i32,f32,f16,i1], 32, (add dummy32)>;"
1057 << std::endl;
1058 o << "def R32IRegs : RegisterClass<\"TCE\", [i32], 32, (add dummy32)>;"
1059 << std::endl;
1060 o << "def R32FPRegs : RegisterClass<\"TCE\", [f32], 32, (add dummy32)>;"
1061 << std::endl;
1062 o << "def R32HFPRegs : RegisterClass<\"TCE\", [f16], 32, (add dummy32)>;"
1063 << std::endl;
1064 }
1065
1066 // Generate data structure that contain registers grouped by their
1067 // physical RFs
1068 for (; i < regs32bit_.size(); i++) {
1069 std::string regName = "I" + Conversion::toString(i);
1070 writeRegisterDef(o, regs32bit_[i], regName, "R32", "", GPR);
1071
1072 if (!regsInRFClasses_.count(regs32bit_[i].rf)) {
1073 regsInRFClasses_[regs32bit_[i].rf] = std::vector<std::string>();
1074 }
1075 i32regs += ", ";
1076 i32regs += regName;
1077 regsInRFClasses_[regs32bit_[i].rf].push_back(regName);
1078 }
1079
1080 o << std::endl;
1081
1082 if (!mach_.is64bit()) {
1083 // Bypass registers
1084 for (size_t j = 0; j < 256; ++j) {
1085 std::string regName = "BP" + Conversion::toString(j);
1086
1087 o << "def " << regName << " : "
1088 << "R32<\"ByPass_Regs"
1089 << "\", []>, DwarfRegNum<"
1090 << "[" << dregNum_++ << "]>;"
1091 << std::endl;
1092 }
1093
1094 // Bypass register class
1095 o << "def R32_ByPass_Regs : RegisterClass<\"TCE\", [i32,f32,f16], 32, (add ";
1096 for (size_t j = 0; j < 256; ++j) {
1097 std::string regName = "BP" + Conversion::toString(j);
1098
1099 if (j != 0) {
1100 o << ", ";
1101 }
1102
1103 o << regName;
1104 }
1105
1106 o << ")>;" << std::endl;
1107 }
1108
1109
1110 for (RegClassMap::iterator
1111 it = regsInRFClasses_.begin(); it != regsInRFClasses_.end(); ++it) {
1112 o << "def R32_"
1113 << it->first
1114 << "_Regs : RegisterClass<\"TCE\", [i32,f32,f16], 32, (add ";
1115
1116 for (std::vector<std::string>::iterator r = it->second.begin();
1117 r != it->second.end(); ++r) {
1118 if (r != it->second.begin()) {
1119 o << ", ";
1120 }
1121
1122 o << *r;
1123 }
1124
1125 o << ")>;" << std::endl;
1126 }
1127
1128 o << std::endl;
1129
1130 // Register classes for all 32-bit registers.
1131 // TODO: why are these needed? same as integer classes below?
1132 for (RegClassMap::iterator ri = regsInClasses_.begin();
1133 ri != regsInClasses_.end(); ri++) {
1134 // go through all 1-bit RF classes
1135 if (ri->first.find("R32") == 0) {
1136
1137 o << "def " << ri->first << "Regs : RegisterClass<\"TCE\", [i32,f32,f16,i1], 32, (add ";
1138 o << ri->second[0];
1139 for (unsigned i = 1; i < ri->second.size(); i++) {
1140 o << " , " << ri->second[i];
1141 }
1142 o << ")>;" << std::endl;
1143 }
1144 }
1145 o << std::endl;
1146
1147 // Integer register classes for 32-bit registers
1148 for (RegClassMap::iterator ri = regsInClasses_.begin();
1149 ri != regsInClasses_.end(); ri++) {
1150 // go through all 32-bit RF classes
1151 if (ri->first.find("R32") == 0) {
1152 o << "def " << ri->first << "IRegs : RegisterClass<\"TCE\", [i32], 32, (add ";
1153 o << ri->second[0];
1154 for (unsigned i = 1; i < ri->second.size(); i++) {
1155 o << " , " << ri->second[i];
1156 }
1157 o << ")>;" << std::endl;
1158 }
1159 }
1160 o << std::endl;
1161
1162 // Floating point register classes for 32-bit registers
1163 for (RegClassMap::iterator ri = regsInClasses_.begin();
1164 ri != regsInClasses_.end(); ri++) {
1165 // go through all 32-bit RF classes
1166 if (ri->first.find("R32") == 0) {
1167
1168 o << "def " << ri->first << "FPRegs : RegisterClass<\"TCE\", [f32], 32, (add ";
1169 o << ri->second[0];
1170 for (unsigned i = 1; i < ri->second.size(); i++) {
1171 o << " , " << ri->second[i];
1172 }
1173 o << ")>;" << std::endl;
1174 }
1175 }
1176
1177 // Half-float register classes for 32-bit registers (TODO: 16-bit registers also?)
1178 for (RegClassMap::iterator ri = regsInClasses_.begin();
1179 ri != regsInClasses_.end(); ri++) {
1180 // go through all 32-bit RF classes
1181 if (ri->first.find("R32") == 0) {
1182 o << "def " << ri->first << "HFPRegs : RegisterClass<\"TCE\", [f16], 32, (add ";
1183 o << ri->second[0];
1184 for (unsigned i = 1; i < ri->second.size(); i++) {
1185 o << " , " << ri->second[i];
1186 }
1187 o << ")>;" << std::endl;
1188 }
1189 }
1190
1191// if (regs32bit_.size() <3) {
1192 if (mach_.is64bit()) { // for now. later try to use 32-b it regs for float.
1193 use64bitForFP_ = true;
1194 }
1195
1196 if (!use64bitForFP_) {
1197
1198 o << "def FPRegs : RegisterClass<\"TCE\", [f32], 32, (add "
1199 << i32regs << ")>;" << std::endl;
1200
1201 o << "def HFPRegs : RegisterClass<\"TCE\", [f16], 32, (add "
1202 << i32regs << ")>;" << std::endl;
1203 }
1204 o << std::endl;
1205}
TDGen::regsInRFClasses_
RegClassMap regsInRFClasses_
Definition TDGen.hh:647

References argRegCount_, ARGUMENT, dregNum_, GPR, TTAMachine::Machine::is64bit(), mach_, prebypassStackIndeces_, regs32bit_, regsInClasses_, regsInRFClasses_, RESERVED, RESULT, Conversion::toString(), use64bitForFP_, and writeRegisterDef().

Referenced by writeRegisterInfo().

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◆ write64bitMoveDefs()

void TDGen::write64bitMoveDefs ( std::ostream &  o)
protected

Definition at line 8378 of file TDGen.cc.

8378 {
8379 o << std::endl << "// 64-bit register->register move definitions."
8380 << std::endl << "let isAsCheapAsAMove = 1 in {" << std::endl;
8381
8382 o << "def MOV64rr : InstTCE<(outs R64Regs:$dst), (ins R64Regs:$src),"
8383 << " \"$src -> $dst;\", []>;" << std::endl;
8384
8385 o << "def PRED_TRUE_MOV64rr : InstTCE<(outs R64Regs:$dst), "
8386 << "(ins R1Regs:$pred, R64Regs:$src), \"$src -> $dst;\", []>;"
8387 << std::endl;
8388
8389 o << "def PRED_FALSE_MOV64rr : InstTCE<(outs R64Regs:$dst), "
8390 << "(ins R1Regs:$pred, R64Regs:$src), \"$src -> $dst;\", []>;"
8391 << std::endl;
8392
8393 o << "} // end of is as cheap as move" << std::endl;
8394}

◆ write64bitRegisterInfo()

void TDGen::write64bitRegisterInfo ( std::ostream &  o)
protected

Writes 64-bit register definitions to the output stream.

Definition at line 1363 of file TDGen.cc.

1363 {
1364
1365 // --- Hardcoded reserved registers. ---
1366 std::string i64regs;
1367 std::string f64regs;
1368 size_t i = 0;
1369
1370 if (mach_.is64bit()) {
1371 // --- Hardcoded reserved registers. ---
1372 writeRegisterDef(o, regs64bit_[0], "SP", "R64", "", RESERVED);
1373 writeRegisterDef(o, regs64bit_[1], "IRES0", "R64", "", RESULT);
1374 writeRegisterDef(o, regs64bit_[2], "FP", "R64", "", RESERVED);
1375 writeRegisterDef(
1376 o, regs64bit_[3], "KLUDGE_REGISTER", "R64", "", RESERVED);
1377 i64regs = "SP, IRES0, FP, KLUDGE_REGISTER";
1378
1379 //after the loop, i will have the index of first non-special reg.
1380 for (i = 4;
1381 i < std::min(argRegCount_ + 3, (unsigned int)regs64bit_.size());
1382 i++) {
1383 std::string regName = "A" + Conversion::toString(i);
1384 writeRegisterDef(o, regs64bit_[i], regName, "R64", "", ARGUMENT);
1385 i64regs += ", ";
1386 i64regs += regName;
1387 }
1388 } else {
1389
1390 if (regs64bit_.size() < 1) {
1391 RegInfo reg = { "DUMMY64", 0 };
1392 writeRegisterDef(o, reg, "DUMMY64", "R64", "", RESERVED);
1393 i64regs = "DUMMY64";
1394 }
1395
1396 }
1397
1398 // i already contains the correct starting index.
1399 for (; i < regs64bit_.size(); i++) {
1400 std::string intRegName = "L" + Conversion::toString(i);
1401 if (i != 0)
1402 i64regs += ", ";
1403 i64regs += intRegName;
1404 writeRegisterDef(o, regs64bit_[i], intRegName, "R64", "", GPR);
1405 }
1406
1407 if (mach_.is64bit()) {
1408 // Bypass registers
1409 for (size_t j = 0; j < 256; ++j) {
1410 std::string regName = "BP" + Conversion::toString(j);
1411
1412 o << "def " << regName << " : "
1413 << "R64<\"ByPass_Regs"
1414 << "\", []>, DwarfRegNum<"
1415 << "[" << dregNum_++ << "]>;"
1416 << std::endl;
1417 }
1418
1419 // Bypass register class
1420 o << "def R64_ByPass_Regs : RegisterClass<\"TCE\", [i64,i32,f64,f32,f16], 64, (add ";
1421 for (size_t j = 0; j < 256; ++j) {
1422 std::string regName = "BP" + Conversion::toString(j);
1423
1424 if (j != 0) {
1425 o << ", ";
1426 }
1427
1428 o << regName;
1429 }
1430
1431 o << ")>;" << std::endl;
1432 }
1433
1434 TCEString dataTypes64 = use64bitForFP_ ?
1435 "[i64,f64,f32,f16]" :
1436 "[i64,f64]";
1437
1438 o << std::endl
1439 << "def R64Regs : RegisterClass<\"TCE\", " << dataTypes64
1440 << ", 64, (add " << i64regs << ")> ;"
1441 << std::endl;
1442
1443 o << std::endl
1444 << "def R64IRegs : RegisterClass<\"TCE\", [i64], 64, (add "
1445 << i64regs << ")> ;"
1446 << std::endl;
1447
1448 o << std::endl
1449 << "def R64FPRegs : RegisterClass<\"TCE\", [f32], 64, (add "
1450 << i64regs << ")>;" << std::endl;
1451
1452 o << std::endl
1453 << "def R64HFPRegs : RegisterClass<\"TCE\", [f16], 64, (add "
1454 << i64regs << ")>;" << std::endl;
1455
1456 o << std::endl
1457 << "def R64DFPRegs : RegisterClass<\"TCE\", [f64], 64, (add "
1458 << i64regs << ")>;" << std::endl << std::endl;
1459
1460 if (use64bitForFP_) {
1461 o << "def FPRegs : RegisterClass<\"TCE\", [f32], 64, (add "
1462 << i64regs << ")>;" << std::endl << std::endl;
1463
1464 o << "def HFPRegs : RegisterClass<\"TCE\", [f16], 64, (add "
1465 << i64regs << ")>;" << std::endl << std::endl;
1466 }
1467}

References argRegCount_, ARGUMENT, dregNum_, GPR, TTAMachine::Machine::is64bit(), mach_, regs64bit_, RESERVED, RESULT, Conversion::toString(), use64bitForFP_, and writeRegisterDef().

Referenced by writeRegisterInfo().

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◆ write8bitRegisterInfo()

void TDGen::write8bitRegisterInfo ( std::ostream &  o)
protected

◆ writeAddressingModeDefs()

void TDGen::writeAddressingModeDefs ( std::ostream &  o)
protected

Definition at line 8419 of file TDGen.cc.

8419 {
8420 if (!mach_.is64bit()) {
8421 o << std::endl
8422 << "// Addressing modes." << std::endl
8423 << "def ADDRrr : ComplexPattern<i32, 2, \"SelectADDRrr\", [], []>;" << std::endl
8424 << "def ADDRri : ComplexPattern<i32, 2, \"SelectADDRri\", [frameindex], []>;" << std::endl
8425 << std::endl
8426 << "// Address operands" << std::endl
8427 << "def MEMrr : Operand<i32> {" << std::endl
8428 << "let PrintMethod = \"printMemOperand\";" << std::endl
8429 << "let MIOperandInfo = (ops R32IRegs, R32IRegs);" << std::endl
8430 << "}" << std::endl
8431 << "def MEMri : Operand<i32> {" << std::endl
8432 << "let PrintMethod = \"printMemOperand\";" << std::endl
8433 << "let MIOperandInfo = (ops R32IRegs, i32imm);" << std::endl
8434 << "}" << std::endl
8435 << std::endl
8436 << "// Branch targets have OtherVT type." << std::endl
8437 << "def brtarget : Operand<OtherVT>; " << std::endl
8438 << "def calltarget : Operand<i32>;" << std::endl;
8439
8440 o << "def SDT_TCECall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;" << std::endl;
8441 } else {
8442 o << std::endl
8443 << "// Addressing modes." << std::endl
8444 << "def ADDRrr : ComplexPattern<i64, 2, \"SelectADDRrr\", [], []>;" << std::endl
8445 << "def ADDRri : ComplexPattern<i64, 2, \"SelectADDRri\", [frameindex], []>;" << std::endl
8446 << std::endl
8447 << "// Address operands" << std::endl
8448 << "def MEMrr : Operand<i64> {" << std::endl
8449 << "let PrintMethod = \"printMemOperand\";" << std::endl
8450 << "let MIOperandInfo = (ops R64IRegs, R64IRegs);" << std::endl
8451 << "}" << std::endl
8452 << "def MEMri : Operand<i64> {" << std::endl
8453 << "let PrintMethod = \"printMemOperand\";" << std::endl
8454 << "let MIOperandInfo = (ops R64IRegs, i64imm);" << std::endl
8455 << "}" << std::endl
8456 << std::endl
8457 << "// Branch targets have OtherVT type." << std::endl
8458 << "def brtarget : Operand<OtherVT>; " << std::endl
8459 << "def calltarget : Operand<i64>;" << std::endl;
8460
8461 o << "def SDT_TCECall : SDTypeProfile<0, 1, [SDTCisVT<0, i64>]>;" << std::endl;
8462 }
8463}

References TTAMachine::Machine::is64bit(), and mach_.

Referenced by initializeBackendContents().

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◆ writeArgRegsArray()

void TDGen::writeArgRegsArray ( std::ostream &  os)
protected

Definition at line 6996 of file TDGen.cc.

6996 {
6997 os << "#ifndef ARGREGS_HH" << std::endl
6998 << "#define ARGREGS_HH" << std::endl << std::endl
6999 << "static const unsigned ArgRegs[] = { TCE::IRES0" << std::endl;
7000 for (unsigned int i = 4; i < (3 + argRegCount_); i++) {
7001 os << ",TCE::A" << i;
7002 }
7003 os << "};" << std::endl;
7004
7005 os << "static const int argRegCount = " << argRegCount_ <<";" << std::endl
7006 << "#endif" << std::endl;
7007}

References argRegCount_.

Referenced by initializeBackendContents().

◆ writeBackendCode()

void TDGen::writeBackendCode ( std::ostream &  o)
protected

Generates required function definitions for the backend plugin.

Parameters
oOutput stream to write the c++ code to.

Definition at line 3997 of file TDGen.cc.

3997 {
3998 // Register & operation info table initialization
3999
4000 o << "void" << std::endl
4001 << "GeneratedTCEPlugin::initialize() {" << std::endl;
4002
4003 // operation names
4004 std::map<std::string, std::string>::const_iterator iter =
4005 opNames_.begin();
4006
4007 for (; iter != opNames_.end(); iter++) {
4008 o << " opNames_[TCE::" << (*iter).first
4009 << "] = \"" << (*iter).second
4010 << "\";" << std::endl;
4011 }
4012
4013 for (iter = truePredOps_.begin(); iter != truePredOps_.end(); iter++) {
4014 o << " truePredOps_[TCE::" << (*iter).first
4015 << "] = TCE::" << (*iter).second
4016 << ";" << std::endl;
4017 }
4018
4019 for (iter = falsePredOps_.begin(); iter != falsePredOps_.end(); iter++) {
4020 o << " falsePredOps_[TCE::" << (*iter).first
4021 << "] = TCE::" << (*iter).second
4022 << ";" << std::endl;
4023 }
4024
4025 // Register names & indices
4026 std::map<std::string, RegInfo>::const_iterator rIter = regs_.begin();
4027 rIter = regs_.begin();
4028 for (; rIter != regs_.end(); rIter++) {
4029 const RegInfo& regInfo = rIter->second;
4030 o << " regNames_[TCE::" << (*rIter).first
4031 << "] = \"" << regInfo.rf
4032 << "\";" << std::endl;
4033
4034 o << " regIndices_[TCE::" << (*rIter).first
4035 << "] = " << regInfo.idx
4036 << ";" << std::endl;
4037
4038 TCEString ttaRegName = regInfo.rf + "." + std::to_string(regInfo.idx);
4039 o << " ttallvmRegMap_[\"" << ttaRegName << "\"] = "
4040 << "TCE::" << (*rIter).first << ";" << std::endl;
4041 }
4042
4043 // Supported stack access opcodes
4044 o << std::endl;
4045 for (std::string opName : supportedStackAccessOperations(mach_)) {
4046 o << " validStackAccessOperations_.insert(\"" << opName << "\");"
4047 << std::endl;
4048 }
4049
4050 // data address space
4051 const TTAMachine::Machine::FunctionUnitNavigator& nav =
4052 mach_.functionUnitNavigator();
4053 std::string asName = "";
4054 for (int i = 0; i < nav.count(); i++) {
4055 if (nav.item(i) != mach_.controlUnit() &&
4056 nav.item(i)->addressSpace() != NULL) {
4057 asName = nav.item(i)->addressSpace()->name();
4058 }
4059 }
4060
4061 if (asName == "") {
4062 std::string msg = "Couldn't determine data address space.";
4063 throw InvalidData(__FILE__, __LINE__, __func__, msg);
4064 }
4065 o << " dataASName_ = \"" << asName << "\";" << std::endl;
4066
4067 o << "}" << std::endl;
4068
4069
4070 bool hasSDIV = false;
4071 bool hasUDIV = false;
4072 bool hasSREM = false;
4073 bool hasUREM = false;
4074 bool hasMUL = false;
4075 bool hasROTL = false;
4076 bool hasROTR = false;
4077 bool hasSXHW = false;
4078 bool hasSXQW = false;
4079 bool hasSQRTF = false;
4080 bool hasSHR = false;
4081 bool hasSHRU = false;
4082 bool hasSHL = false;
4083 bool has8bitLoads = false;
4084 bool has16bitLoads = false;
4085// bool has32bitLoads = false; // used only for 64-bit system
4086
4087 const TTAMachine::Machine::FunctionUnitNavigator fuNav =
4088 mach_.functionUnitNavigator();
4089
4090 for (int i = 0; i < fuNav.count(); i++) {
4091 const TTAMachine::FunctionUnit* fu = fuNav.item(i);
4092 for (int o = 0; o < fu->operationCount(); o++) {
4093 const std::string opName =
4094 StringTools::stringToLower(fu->operation(o)->name());
4095
4096 if (mach_.is64bit()) {
4097 if (opName == "div64") hasSDIV = true;
4098 if (opName == "divu64") hasUDIV = true;
4099 if (opName == "mod64") hasSREM = true;
4100 if (opName == "modu64") hasUREM = true;
4101 if (opName == "mul64") hasMUL = true;
4102 if (opName == "rotl64") hasROTL = true;
4103 if (opName == "rotr64") hasROTR = true;
4104 if (opName == "sxh64") hasSXHW = true;
4105 if (opName == "sxq64") hasSXQW = true;
4106 if (opName == "shr64") hasSHR = true;
4107 if (opName == "shru64") hasSHRU = true;
4108 if (opName == "shl64") hasSHL = true;
4109 } else {
4110 if (opName == "div") hasSDIV = true;
4111 if (opName == "divu") hasUDIV = true;
4112 if (opName == "mod") hasSREM = true;
4113 if (opName == "modu") hasUREM = true;
4114 if (opName == "mul") hasMUL = true;
4115 if (opName == "rotl") hasROTL = true;
4116 if (opName == "rotr") hasROTR = true;
4117 if (opName == "sxhw") hasSXHW = true;
4118 if (opName == "sxqw") hasSXQW = true;
4119 if (opName == "shr") hasSHR = true;
4120 if (opName == "shru") hasSHRU = true;
4121 if (opName == "shl") hasSHL = true;
4122 }
4123 if (opName == "sqrtf") hasSQRTF = true;
4124
4125 if (littleEndian_) {
4126 if (opName == "ld16" || opName == "ldu16") {
4127 has16bitLoads = true;
4128 } else if(opName == "ld8" || opName == "ldu8") {
4129 has8bitLoads = true;
4130// } else if (opName == "ld32" || opName == "ldu32") {
4131// has32bitLoads = true;
4132 }
4133 } else {
4134 if (opName == "ldh" || opName == "ldhu") {
4135 has16bitLoads = true;
4136 } else if (opName == "ldq" || opName == "ldqu") {
4137 has8bitLoads = true;
4138// } else if (opName == "ldw") {
4139// has32bitLoads = true;
4140 }
4141 }
4142 }
4143 }
4144
4145 o << "bool GeneratedTCEPlugin::hasSDIV() const { return "
4146 << hasSDIV << "; }" << std::endl
4147 << "bool GeneratedTCEPlugin::hasUDIV() const { return "
4148 << hasUDIV << "; }" << std::endl
4149 << "bool GeneratedTCEPlugin::hasSREM() const { return "
4150 << hasSREM << "; }" << std::endl
4151 << "bool GeneratedTCEPlugin::hasUREM() const { return "
4152 << hasUREM << "; }" << std::endl
4153 << "bool GeneratedTCEPlugin::hasMUL() const { return "
4154 << hasMUL << "; }" << std::endl
4155 << "bool GeneratedTCEPlugin::hasROTL() const { return "
4156 << hasROTL << "; }" << std::endl
4157 << "bool GeneratedTCEPlugin::hasROTR() const { return "
4158 << hasROTR << "; }" << std::endl
4159 << "bool GeneratedTCEPlugin::hasSXHW() const { return "
4160 << hasSXHW << "; }" << std::endl
4161 << "bool GeneratedTCEPlugin::hasSXQW() const { return "
4162 << hasSXQW << "; }" << std::endl
4163 << "bool GeneratedTCEPlugin::hasSQRTF() const { return "
4164 << hasSQRTF << "; }" << std::endl
4165 << "bool GeneratedTCEPlugin::hasSHR() const { return "
4166 << hasSHR << "; }" << std::endl
4167 << "bool GeneratedTCEPlugin::hasSHL() const { return "
4168 << hasSHL << "; }" << std::endl
4169 << "bool GeneratedTCEPlugin::hasSHRU() const { return "
4170 << hasSHRU << ";}" << std::endl
4171 << "bool GeneratedTCEPlugin::has8bitLoads() const { return "
4172 << has8bitLoads << ";}" << std::endl
4173 << "bool GeneratedTCEPlugin::has16bitLoads() const { return "
4174 << has16bitLoads << ";}" << std::endl;
4175// << "bool GeneratedTCEPlugin::has32bitLoads() const { return "
4176// << has32bitLoads << ";}" << std::endl
4177
4178 o << "int GeneratedTCEPlugin::maxVectorSize() const { return "
4179 << maxVectorSize_ << "; }" << std::endl;
4180
4181 // create dummy version here
4182 genTCERegisterInfo_setReservedVectorRegs(o);
4183
4184 generateLoadStoreCopyGenerator(o);
4185 createMinMaxGenerator(o);
4186 createParamDRegNums(o);
4187 createVectorRVDRegNums(o);
4188 createEndiannesQuery(o);
4189 createConstantMaterializationQuery(o);
4190 writeGetPointerAdjustmentQuery(o);
4191 createBranchAnalysis(o);
4192
4193 genTCETargetLoweringSIMD_addVectorRegisterClasses(o);
4194 genTCETargetLoweringSIMD_associatedVectorRegClass(o);
4195 genTCETargetLoweringSIMD_getSetCCResultVT(o);
4196 genTCEInstrInfoSIMD_copyPhysVectorReg(o);
4197 genGeneratedTCEPlugin_getLoadOpcode(o);
4198 genGeneratedTCEPlugin_getAddOpcode(o);
4199 genGeneratedTCEPlugin_getShlOpcode(o);
4200 genGeneratedTCEPlugin_getIorOpcode(o);
4201}
TDGen::genTCETargetLoweringSIMD_addVectorRegisterClasses
void genTCETargetLoweringSIMD_addVectorRegisterClasses(std::ostream &o) const
Definition TDGen.cc:3053
TDGen::supportedStackAccessOperations
static std::vector< std::string > supportedStackAccessOperations(const TTAMachine::Machine &mach)
Definition TDGen.cc:7685
TDGen::genGeneratedTCEPlugin_getShlOpcode
void genGeneratedTCEPlugin_getShlOpcode(std::ostream &o) const
Definition TDGen.cc:3300
TDGen::genTCETargetLoweringSIMD_associatedVectorRegClass
void genTCETargetLoweringSIMD_associatedVectorRegClass(std::ostream &o) const
Definition TDGen.cc:3098
TDGen::falsePredOps_
std::map< std::string, std::string > falsePredOps_
Definition TDGen.hh:612
TDGen::truePredOps_
std::map< std::string, std::string > truePredOps_
Definition TDGen.hh:611
TDGen::createConstantMaterializationQuery
void createConstantMaterializationQuery(std::ostream &os)
Definition TDGen.cc:6501
TDGen::generateLoadStoreCopyGenerator
void generateLoadStoreCopyGenerator(std::ostream &os)
Definition TDGen.cc:6365
TDGen::createMinMaxGenerator
virtual void createMinMaxGenerator(std::ostream &os)
Definition TDGen.cc:6398
TDGen::genGeneratedTCEPlugin_getLoadOpcode
void genGeneratedTCEPlugin_getLoadOpcode(std::ostream &o) const
Definition TDGen.cc:3271
TDGen::createVectorRVDRegNums
virtual void createVectorRVDRegNums(std::ostream &os)
Definition TDGen.cc:7022
TDGen::regs_
std::map< std::string, RegInfo > regs_
Map of generated llvm register names to physical register in the machine.
Definition TDGen.hh:603
TDGen::createEndiannesQuery
void createEndiannesQuery(std::ostream &os)
Definition TDGen.cc:6487
TDGen::genTCEInstrInfoSIMD_copyPhysVectorReg
void genTCEInstrInfoSIMD_copyPhysVectorReg(std::ostream &o) const
Definition TDGen.cc:3187
TDGen::createParamDRegNums
void createParamDRegNums(std::ostream &os)
Definition TDGen.cc:7010
TDGen::genGeneratedTCEPlugin_getIorOpcode
void genGeneratedTCEPlugin_getIorOpcode(std::ostream &o) const
Definition TDGen.cc:3315
TDGen::genTCERegisterInfo_setReservedVectorRegs
void genTCERegisterInfo_setReservedVectorRegs(std::ostream &os) const
Definition TDGen.cc:4203
TDGen::writeGetPointerAdjustmentQuery
void writeGetPointerAdjustmentQuery(std::ostream &os) const
Definition TDGen.cc:7522
TDGen::createBranchAnalysis
void createBranchAnalysis(std::ostream &os)
Definition TDGen.cc:7970
TDGen::genGeneratedTCEPlugin_getAddOpcode
void genGeneratedTCEPlugin_getAddOpcode(std::ostream &o) const
Definition TDGen.cc:3285
TDGen::genTCETargetLoweringSIMD_getSetCCResultVT
void genTCETargetLoweringSIMD_getSetCCResultVT(std::ostream &o) const
Definition TDGen.cc:3128
TTAMachine::FunctionUnit::operation
virtual HWOperation * operation(const std::string &name) const
Definition FunctionUnit.cc:363
TTAMachine::FunctionUnit::operationCount
virtual int operationCount() const
Definition FunctionUnit.cc:419
TTAMachine::HWOperation::name
const std::string & name() const
Definition HWOperation.cc:141
TTAMachine::Machine::functionUnitNavigator
virtual FunctionUnitNavigator functionUnitNavigator() const
Definition Machine.cc:380
TTAMachine::Machine::controlUnit
virtual ControlUnit * controlUnit() const
Definition Machine.cc:345

References __func__, TTAMachine::Machine::controlUnit(), TTAMachine::Machine::Navigator< ComponentType >::count(), createBranchAnalysis(), createConstantMaterializationQuery(), createEndiannesQuery(), createMinMaxGenerator(), createParamDRegNums(), createVectorRVDRegNums(), falsePredOps_, TTAMachine::Machine::functionUnitNavigator(), generateLoadStoreCopyGenerator(), genGeneratedTCEPlugin_getAddOpcode(), genGeneratedTCEPlugin_getIorOpcode(), genGeneratedTCEPlugin_getLoadOpcode(), genGeneratedTCEPlugin_getShlOpcode(), genTCEInstrInfoSIMD_copyPhysVectorReg(), genTCERegisterInfo_setReservedVectorRegs(), genTCETargetLoweringSIMD_addVectorRegisterClasses(), genTCETargetLoweringSIMD_associatedVectorRegClass(), genTCETargetLoweringSIMD_getSetCCResultVT(), TDGen::RegInfo::idx, TTAMachine::Machine::is64bit(), TTAMachine::Machine::Navigator< ComponentType >::item(), littleEndian_, mach_, maxVectorSize_, TTAMachine::HWOperation::name(), TTAMachine::FunctionUnit::operation(), TTAMachine::FunctionUnit::operationCount(), opNames_, regs_, TDGen::RegInfo::rf, StringTools::stringToLower(), supportedStackAccessOperations(), truePredOps_, and writeGetPointerAdjustmentQuery().

Referenced by initializeBackendContents().

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◆ writeBooleanStorePatterns()

void TDGen::writeBooleanStorePatterns ( std::ostream &  os)
protected

Writes special store patterns for i1 types.

Definition at line 4568 of file TDGen.cc.

4568 {
4569 std::string storeOp("");
4570 auto storeOps = littleEndian_
4571 ? std::vector<std::string>{"ST8ri", "ST8rr"}
4572 : std::vector<std::string>{"STQri", "STQrr"};
4573 for (auto op : storeOps) {
4574 if (opNames_.count(op)) {
4575 storeOp = op;
4576 break;
4577 }
4578 }
4579 if (storeOp.empty()) return;
4580
4581 // TODO: is this 32 correct for 64-bit ADFs?
4582 auto storeConstBit = [=](const std::string& bitVal) -> std::string {
4583 return std::string("(") + storeOp + " ADDRrr:$addr, " +
4584 (storeOp.back() == 'i' ? "(i32 " : "(MOVI32ri ") + bitVal +
4585 "))";
4586 };
4587
4588 // Patterns to avoid i1 "true" values to be emitted as -1, which breaks
4589 // on, for example, BZ and BNZ if the condition is loaded later, inverted
4590 // using XOR and finally the result is bypassed: this results the -1 to be
4591 // converted to -2, which is interpreted still as true.
4592 os << "def : Pat<(store (i1 -1), ADDRrr:$addr), " << std::endl
4593 << " " << storeConstBit("1") << ">;" << std::endl;
4594 os << "def : Pat<(store (i1 1), ADDRrr:$addr), " << std::endl
4595 << " " << storeConstBit("1") << ">;" << std::endl;
4596 os << "def : Pat<(store (i1 0), ADDRrr:$addr), " << std::endl
4597 << " " << storeConstBit("0") << ">;" << std::endl;
4598}

References littleEndian_, and opNames_.

Referenced by writeInstrInfo().

◆ writeBroadcastDefs()

void TDGen::writeBroadcastDefs ( std::ostream &  o,
Operation &  op,
int  vectorLen 
)
protected

◆ writeCallDef()

void TDGen::writeCallDef ( std::ostream &  o)
protected

Writes .td pattern for the call instruction(s) to the output stream.

Definition at line 3955 of file TDGen.cc.

3955 {
3956 o << "let ";
3957
3958 if (!argRegNames_.empty()) {
3959 o << "Uses = [";
3960 for (unsigned i = 0; i < argRegNames_.size(); i++) {
3961 if (i > 0) o << ", ";
3962 o << argRegNames_[i];
3963 }
3964 o << "],";
3965 }
3966
3967 o << "hasDelaySlot = 1, isCall = 1,";
3968 o << "Defs = [";
3969
3970 writeCallDefRegs(o);
3971
3972 o << "] in {" << std::endl;
3973 o << "def CALL : InstTCE<(outs), (ins calltarget:$dst),";
3974 o << "\"$dst -> call.1;\", []>;" << std::endl;
3975
3976 o << "def CALL_MEMrr : InstTCE<(outs), (ins MEMrr:$ptr),";
3977 o << "\"$ptr -> call.1;\", [(call ADDRrr:$ptr)]>;" << std::endl;
3978
3979 o << "def CALL_MEMri : InstTCE<(outs), (ins MEMri:$ptr),";
3980 o << "\"$ptr -> call.1;\", [(call ADDRri:$ptr)]>;" << std::endl;
3981 o << "}" << std::endl;
3982
3983 o << "def : Pat<(call tglobaladdr:$dst), (CALL tglobaladdr:$dst)>;"
3984 << std::endl;
3985
3986 o << "def : Pat<(call texternalsym:$dst), (CALL texternalsym:$dst)>;"
3987 << std::endl;
3988
3989}
TDGen::argRegNames_
std::vector< std::string > argRegNames_
Definition TDGen.hh:605
TDGen::writeCallDefRegs
virtual void writeCallDefRegs(std::ostream &o)
Definition TDGen.cc:3580

References argRegNames_, and writeCallDefRegs().

Referenced by writeControlFlowInstrDefs().

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◆ writeCallDefRegs()

void TDGen::writeCallDefRegs ( std::ostream &  o)
protectedvirtual

Definition at line 3580 of file TDGen.cc.

3580 {
3581 for (unsigned i = 0; i < resRegNames_.size(); i++) {
3582 if (i > 0) o << ", ";
3583 o << resRegNames_[i];
3584 }
3585 for (unsigned i = 0; i < gprRegNames_.size(); i++) {
3586 o << ", " << gprRegNames_[i];
3587 }
3588
3589 // call dest may call others which may mess up these
3590 for (unsigned i = 0; i < argRegNames_.size(); i++) {
3591 o << ", " << argRegNames_[i];
3592 }
3593
3594 std::map<int, std::vector<RegisterInfo>>::const_iterator it;
3595 for (it = registers_.begin(); it != registers_.end(); ++it) {
3596 int regsWidth = it->first;
3597
3598 const std::vector<RegisterInfo>& regs = it->second;
3599 TCEString baseClass = baseClasses_.find(regsWidth)->second;
3600
3601 for (size_t i = 0; i < regs.size(); ++i) {
3602 // Don't declare <=32b registers again, it has been done in TDGen.
3603 if (regsWidth > maxScalarWidth_) {
3604 RegisterInfo reg = regs[i];
3605 o << ", " << reg.regName_;
3606 }
3607 }
3608 }
3609}
TDGen::gprRegNames_
std::vector< std::string > gprRegNames_
Definition TDGen.hh:607
TDGen::resRegNames_
std::vector< std::string > resRegNames_
Definition TDGen.hh:606

References argRegNames_, baseClasses_, gprRegNames_, maxScalarWidth_, registers_, TDGenerator::RegisterInfo::regName_, and resRegNames_.

Referenced by writeCallDef().

◆ writeCallingConv()

void TDGen::writeCallingConv ( std::ostream &  os)
protected

Writes details about function arguments and returns values.

Parameters
oOutput stream to the file.

Definition at line 6870 of file TDGen.cc.

6870 {
6871 writeCallingConvLicenceText(os);
6872
6873 int bits = mach_.is64bit() ? 64 : 32;
6874 int bytes = mach_.is64bit() ? 8 : 4;
6875 // Function return value types.
6876 os << "// Function return value types." << endl;
6877 os << "def RetCC_TCE : CallingConv<[" << endl;
6878 if (mach_.is64bit()) {
6879 os << " CCIfType<[i1], CCPromoteToType<i64>>," << endl
6880 << " CCIfType<[i32], CCPromoteToType<i64>>," << endl
6881 << " CCIfType<[i64], CCAssignToReg<[IRES0]>>," << endl
6882 << " CCIfType<[f64], CCAssignToReg<[IRES0]>>," << endl << endl;
6883 } else {
6884 os << " CCIfType<[i1], CCPromoteToType<i32>>," << endl;
6885 os << " CCIfType<[i32], CCAssignToReg<[IRES0]>>," << endl;
6886 }
6887
6888 os << " CCIfType<[f16], CCAssignToReg<[IRES0]>>," << endl
6889 << " CCIfType<[f32], CCAssignToReg<[IRES0]>>," << endl << endl;
6890
6891 os << " // Vector value types." << endl;
6892 std::map<TCEString, RegisterClass>::const_iterator rcIt;
6893 for (rcIt = vRegClasses_.begin(); rcIt != vRegClasses_.end(); ++rcIt) {
6894 const TCEString& vtStr = rcIt->first;
6895 const RegisterClass& regClass = rcIt->second;
6896
6897 if (regClass.numberOfRegisters() > 0) {
6898 os << " CCIfType<[" << vtStr << "], CCAssignToReg<[";
6899 if (regClass.valueType().width() <= bits) {
6900 os << "IRES0";
6901 } else {
6902 os << regClass.registerInfo(0).regName_;
6903 }
6904 os << "]>>," << endl;
6905 } else {
6906 verbose("ValueType " + vtStr + " can not be a return value");
6907 }
6908 }
6909
6910 os << " CCAssignToStack<" << bytes << ", " << bytes << ">" << endl
6911 << "]>;" << endl << endl;
6912
6913 // Function argument value types.
6914 os << "// Function argument value types." << endl;
6915 os << "def CC_TCE : CallingConv<[" << endl;
6916 if (mach_.is64bit()) {
6917 os << " CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>," << endl
6918 << " CCIfType<[i64], CCAssignToReg<[IRES0]>>," << endl << endl;
6919
6920 for (unsigned int i = 4; i < (3 + argRegCount_); i++) {
6921 os << " CCIfType<[i64], CCAssignToReg<[A" << i << "]>>," << endl;
6922 }
6923
6924 } else {
6925 os << " CCIfType<[i1, i8, i16], CCPromoteToType<i32>>," << endl
6926 << " CCIfType<[i32], CCAssignToReg<[IRES0]>>," << endl << endl;
6927
6928 for (unsigned int i = 4; i < (3 + argRegCount_); i++) {
6929 os << " CCIfType<[i32], CCAssignToReg<[A" << i << "]>>," << endl;
6930 }
6931 }
6932
6933 if (mach_.is64bit()) {
6934 os << " // 64-bit integer values get stored in stack slots that are"
6935 << endl
6936 << " // 8 bytes insize and 8-byte aligned." << endl
6937 << " CCIfType<[i64, f64, f32], CCAssignToStack<8, 8>>,"
6938 << endl << endl;
6939 } else {
6940 os << " // Integer values get stored in stack slots that are" << endl
6941 << " // 4 bytes insize and 4-byte aligned." << endl
6942 << " CCIfType<[i32, f32], CCAssignToStack<4, 4>>," << endl << endl;
6943 }
6944 os << " // Double values get stored in stack slots that are" << endl
6945 << " // 8 bytes in size and 8-byte aligned." << endl
6946 << " CCIfType<[f64], CCAssignToStack<8, 8>>";
6947
6948 if (vRegClasses_.size() > 0) {
6949 os << ",";
6950 }
6951 os << endl << endl;
6952
6953 os << " // Vector value types." << endl;
6954 for (rcIt = vRegClasses_.begin(); rcIt != vRegClasses_.end(); ++rcIt) {
6955 const TCEString& vtStr = rcIt->first;
6956 const RegisterClass& regClass = rcIt->second;
6957
6958 int byteAlignment = regClass.alignment() / 8;
6959 if (byteAlignment < bytes) {
6960 byteAlignment = bytes;
6961 }
6962
6963 os << " CCIfType<[" << vtStr << "], CCAssignToStack<"
6964 << byteAlignment << ", " << byteAlignment << ">>";
6965 if (rcIt != --vRegClasses_.end()) {
6966 os << ",";
6967 }
6968 os << endl;
6969 }
6970
6971 os << "]>;" << endl;
6972}
TDGen::writeCallingConvLicenceText
void writeCallingConvLicenceText(std::ostream &os)
Definition TDGen.cc:6975

References TDGenerator::RegisterClass::alignment(), argRegCount_, TTAMachine::Machine::is64bit(), mach_, TDGenerator::RegisterClass::numberOfRegisters(), TDGenerator::RegisterClass::registerInfo(), TDGenerator::RegisterInfo::regName_, TDGenerator::RegisterClass::valueType(), verbose(), vRegClasses_, TDGenerator::ValueType::width(), and writeCallingConvLicenceText().

Referenced by initializeBackendContents().

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◆ writeCallingConvLicenceText()

void TDGen::writeCallingConvLicenceText ( std::ostream &  os)
protected

Definition at line 6975 of file TDGen.cc.

6975 {
6976 os << "//===- GenCallingConv.td - Calling Conventions TCE ---------*- "
6977 << "tablegen -*-===//" << std::endl
6978 << "// " << std::endl
6979 << "// The LLVM Compiler Infrastructure" << std::endl
6980 << "//" << std::endl
6981 << "// This file is distributed under the University of "
6982 << "Illinois Open Source" << std::endl
6983 << "// License. See LICENSE.TXT for details." << std::endl
6984 << "// " << std::endl
6985 << "//===--------------------------------------------------------"
6986 << "--------------===//" << std::endl
6987 << "//" << std::endl
6988 << "// This describes the calling conventions for the TCE "
6989 << "architectures." << std::endl
6990 << "//" << std::endl
6991 << "//===--------------------------------------------------------"
6992 << "--------------===//" << std::endl << std::endl;
6993}

Referenced by writeCallingConv().

◆ writeCallSeqStart()

void TDGen::writeCallSeqStart ( std::ostream &  os)
protected

Definition at line 7944 of file TDGen.cc.

7944 {
7945
7946 bool is64bit = mach_.is64bit();
7947
7948 if (!is64bit) {
7949 os << "def SDT_TCECallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,"
7950 << "SDTCisVT<1, i32> ]>;" << std::endl << std::endl;
7951 } else {
7952 os << "def SDT_TCECallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i64>,"
7953 << "SDTCisVT<1, i64> ]>;" << std::endl << std::endl;
7954 }
7955 os << "def callseq_start : SDNode<\"ISD::CALLSEQ_START\", "
7956 << "SDT_TCECallSeqStart, [SDNPHasChain, SDNPOutGlue]>;" << std::endl
7957 << std::endl
7958 << "let Defs = [SP], Uses = [SP] in {" << std::endl
7959 << "def ADJCALLSTACKDOWN : Pseudo<(outs),";
7960 if (!is64bit) {
7961 os << "(ins i32imm:$amt1, i32imm:$amt2),";
7962 } else {
7963 os << "(ins i64imm:$amt1, i64imm:$amt2),";
7964 }
7965 os << "\"# ADJCALLSTACKDOWN $amt1, $amt2\","
7966 << "[(callseq_start timm:$amt1, timm:$amt2)]>;}"
7967 << std::endl << std::endl;
7968}

References TTAMachine::Machine::is64bit(), and mach_.

Referenced by writeInstrInfo().

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◆ writeCondBranchDefs()

void TDGen::writeCondBranchDefs ( std::ostream &  os)
protected

Writes instructions definitions and patterns for conditional branches.

Definition at line 3661 of file TDGen.cc.

3661 {
3662
3663 auto cuOpset = MachineInfo::getOpset(*mach_.controlUnit());
3664
3665 if (MachineInfo::supportsBoolRegisterGuardedJumps(mach_)) {
3666
3667 os << std::endl << "let isTerminator = 1, isBranch = 1 in {" << std::endl;
3668
3669 if (cuOpset.count("JUMP") && opNames_.count("TCEBRCOND") == 0) {
3670 writeInstrDef(os, "TCEBRCOND", "",
3671 "GuardRegs:$gr, brtarget:$dst",
3672 "? $gr $dst -> jump.1;",
3673 "(brcond GuardRegs:$gr, bb:$dst)");
3674 os << std::endl;
3675 opNames_["TCEBRCOND"] = "?jump";
3676 }
3677
3678 if (cuOpset.count("JUMP") && opNames_.count("TCEBRICOND") == 0) {
3679 writeInstrDef(os, "TCEBRICOND", "",
3680 "GuardRegs:$gr, brtarget:$dst",
3681 "! $gr $dst -> jump.1;",
3682 "(brcond (not GuardRegs:$gr), bb:$dst)");
3683 opNames_["TCEBRICOND"] = "!jump";
3684 }
3685 os << "}" << std::endl;
3686
3687 // generate brcc pseudo jumps. these are split in llvmtcebuilder into
3688 // separate comparison and jump.
3689 } else if (MachineInfo::supportsPortGuardedJumps(mach_)) {
3690
3691 if (!writePortGuardedJumpDefPair(os, "EQ", "NE")) {
3692 abortWithError("Required eq/ne op not found. please add to adf.");
3693 }
3694 if (!writePortGuardedJumpDefPair(os, "GT", "LE")) {
3695 abortWithError("Required gt/le op not found. please add to adf.");
3696 }
3697 if (!writePortGuardedJumpDefPair(os, "GTU", "LEU")) {
3698 abortWithError("Required gtu/leu op not found. please add to adf.");
3699 }
3700
3701 // floating point ops are optional.
3702 writePortGuardedJumpDefPair(os, "EQF", "NEF", true);
3703 writePortGuardedJumpDefPair(os, "LEF", "GTF", true);
3704 writePortGuardedJumpDefPair(os, "LTF", "GEF", true);
3705
3706 if (MachineInfo::supportsPortGuardedJump(mach_, false, "AND")) {
3707 writeInstrDef(os, "AND_JUMP", "",
3708 "R32IRegs:$cmp1, R32IRegs:$cmp2, brtarget:$dst", "",
3709 "(brcond (and R32IRegs:$cmp1, R32IRegs:$cmp2), bb:$dst)");
3710 } else {
3711 std::cerr << "Missing AND operation as true-guard source to jump." << std::endl;
3712 assert(false);
3713 }
3714
3715 if (MachineInfo::supportsPortGuardedJump(mach_, false, "IOR")) {
3716 writeInstrDef(os, "IOR_JUMP", "",
3717 "R32IRegs:$cmp1, R32IRegs:$cmp2, brtarget:$dst", "",
3718 "(brcond (or R32IRegs:$cmp1, R32IRegs:$cmp2), bb:$dst)");
3719 } else {
3720 std::cerr << "Missing IOR operation as true-guard source to jump." << std::endl;
3721 assert(false);
3722 }
3723
3724 os << std::endl << "let isTerminator = 1, isBranch = 1 in {" << std::endl;
3725
3726 // dummy br(i)cond ops
3727 writeInstrDef(os, "TCEBRCOND", "",
3728 "GuardRegs:$gr, brtarget:$dst",
3729 "? $gr $dst -> jump.1;",
3730 "");
3731 os << std::endl;
3732
3733 writeInstrDef(os, "TCEBRICOND", "",
3734 "GuardRegs:$gr, brtarget:$dst",
3735 "? $gr $dst -> jump.1;",
3736 "");
3737 os << std::endl;
3738
3739
3740 os << "}" << std::endl;
3741
3742 os << "def: Pat<(brcc SETLT, R32IRegs:$cmp1, R32IRegs:$cmp2, bb:$dst),"
3743 << " (GT_JUMP R32IRegs:$cmp2, R32IRegs:$cmp1, brtarget:$dst)>;" << std::endl;
3744
3745
3746 os << "def: Pat<(brcc SETGE, R32IRegs:$cmp1, R32IRegs:$cmp2, bb:$dst),"
3747 << " (LE_JUMP R32IRegs:$cmp2, R32IRegs:$cmp1, brtarget:$dst)>;" << std::endl;
3748
3749 os << "def: Pat<(brcc SETULT, R32IRegs:$cmp1, R32IRegs:$cmp2, bb:$dst),"
3750 << " (GTU_JUMP R32IRegs:$cmp2, R32IRegs:$cmp1, brtarget:$dst)>;" << std::endl;
3751
3752
3753 os << "def: Pat<(brcc SETUGE, R32IRegs:$cmp1, R32IRegs:$cmp2, bb:$dst),"
3754 << " (LEU_JUMP R32IRegs:$cmp2, R32IRegs:$cmp1, brtarget:$dst)>;" << std::endl;
3755
3756
3757 opNames_["AND_JUMP"] = "and+?jump";
3758 opNames_["IOR_JUMP"] = "ior+?jump";
3759
3760 // conditional jumps without guard.
3761 } else {
3762
3763 os << std::endl << "let isTerminator = 1, isBranch = 1 in {" << std::endl;
3764
3765 if (cuOpset.count("BNZ1")) {
3766 // TODO: Check if has R1 regs or not!
3767
3768 writeInstrDef(os, "TCEBRCOND", "", "R32IRegs:$gr, brtarget:$dst",
3769 "", "(brcond R32IRegs:$gr, bb:$dst)");
3770 os << std::endl;
3771 opNames_["TCEBRCOND"] = "BNZ1";
3772 } else {
3773 if (cuOpset.count("BNZ")) {
3774 writeInstrDef(os, "TCEBRCOND", "", "R32IRegs:$gr, brtarget:$dst",
3775 "", "(brcond R32IRegs:$gr, bb:$dst)");
3776 os << std::endl;
3777 opNames_["TCEBRCOND"] = "BNZ";
3778 } else {
3779 std::cerr << "Does not have guarded jumps or neither bnz or bnz1" << std::endl;
3780 }
3781 }
3782
3783 if (cuOpset.count("BZ1")) {
3784 // TODO: Check if has R1 regs or not!
3785
3786 writeInstrDef(os, "TCEBRICOND", "", "R32IRegs:$gr, brtarget:$dst",
3787 "", "(brcond (not R32IRegs:$gr), bb:$dst)");
3788 os << std::endl;
3789 opNames_["TCEBRICOND"] = "BZ1";
3790 } else {
3791 if (cuOpset.count("BZ")) {
3792 writeInstrDef(os, "TCEBRICOND", "", "R32IRegs:$gr, brtarget:$dst",
3793 "", "(brcond (not R32IRegs:$gr), bb:$dst)");
3794 os << std::endl;
3795 opNames_["TCEBRICOND"] = "BZ";
3796 } else {
3797 std::cerr << "Does not have guarded jumps or neither bz or bz1" << std::endl;
3798 }
3799 }
3800
3801 if (cuOpset.count("BEQ")) {
3802 writeInstrDef(os, "TCEBREQrr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3803 "", "(brcond (i32 (seteq R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3804 opNames_["TCEBREQrr"] = "BEQ";
3805 writeInstrDef(os, "TCEBREQri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3806 "", "(brcond (i32 (seteq R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3807 opNames_["TCEBREQri"] = "BEQ";
3808 }
3809
3810 if (cuOpset.count("BNE")) {
3811 writeInstrDef(os, "TCEBRNErr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3812 "", "(brcond (i32 (setne R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3813 opNames_["TCEBRNErr"] = "BNE";
3814 writeInstrDef(os, "TCEBRNEri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3815 "", "(brcond (i32 (setne R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3816 opNames_["TCEBRNEri"] = "BNE";
3817 }
3818
3819 if (cuOpset.count("BGT")) {
3820 writeInstrDef(os, "TCEBRGTrr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3821 "", "(brcond (i32 (setgt R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3822 opNames_["TCEBRGTrr"] = "BGT";
3823 writeInstrDef(os, "TCEBRGTri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3824 "", "(brcond (i32 (setgt R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3825 opNames_["TCEBRGTri"] = "BGT";
3826 }
3827
3828 if (cuOpset.count("BGTU")) {
3829 writeInstrDef(os, "TCEBRGTUrr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3830 "", "(brcond (i32 (setugt R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3831 opNames_["TCEBRGTUrr"] = "BGTU";
3832 writeInstrDef(os, "TCEBRGTUri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3833 "", "(brcond (i32 (setugt R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3834 opNames_["TCEBRGTUri"] = "BGTU";
3835 }
3836
3837 if (cuOpset.count("BLT")) {
3838 writeInstrDef(os, "TCEBRLTrr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3839 "", "(brcond (i32 (setlt R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3840 opNames_["TCEBRLTrr"] = "BLT";
3841 writeInstrDef(os, "TCEBRLTri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3842 "", "(brcond (i32 (setlt R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3843 opNames_["TCEBRLTri"] = "BLT";
3844 }
3845
3846 if (cuOpset.count("BLTU")) {
3847 writeInstrDef(os, "TCEBRLTUrr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3848 "", "(brcond (i32 (setult R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3849 opNames_["TCEBRLTUrr"] = "BLTU";
3850 writeInstrDef(os, "TCEBRLTUri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3851 "", "(brcond (i32 (setult R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3852 opNames_["TCEBRLTUri"] = "BLTU";
3853 }
3854
3855 if (cuOpset.count("BLE")) {
3856 writeInstrDef(os, "TCEBRLErr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3857 "", "(brcond (i32 (setle R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3858 opNames_["TCEBRLErr"] = "BLE";
3859 writeInstrDef(os, "TCEBRLEri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3860 "", "(brcond (i32 (setle R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3861 opNames_["TCEBRLEri"] = "BLE";
3862 }
3863
3864 if (cuOpset.count("BLEU")) {
3865 writeInstrDef(os, "TCEBRLEUrr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3866 "", "(brcond (i32 (setule R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3867 opNames_["TCEBRLEUrr"] = "BLEU";
3868 writeInstrDef(os, "TCEBRLEUri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3869 "", "(brcond (i32 (setule R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3870 opNames_["TCEBRLEUri"] = "BLEU";
3871 }
3872
3873 if (cuOpset.count("BGE")) {
3874 writeInstrDef(os, "TCEBRGErr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3875 "", "(brcond (i32 (setge R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3876 opNames_["TCEBRGErr"] = "BGE";
3877 writeInstrDef(os, "TCEBRGEri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3878 "", "(brcond (i32 (setge R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3879 opNames_["TCEBRGEri"] = "BGE";
3880 }
3881
3882 if (cuOpset.count("BGEU")) {
3883 writeInstrDef(os, "TCEBRGEUrr", "", "R32IRegs:$c1, R32IRegs:$c2, brtarget:$dst",
3884 "", "(brcond (i32 (setuge R32IRegs:$c1, R32IRegs:$c2)), bb:$dst)");
3885 opNames_["TCEBRGEUrr"] = "BGEU";
3886 writeInstrDef(os, "TCEBRGEUri", "", "R32IRegs:$c1, i32imm:$c2, brtarget:$dst",
3887 "", "(brcond (i32 (setuge R32IRegs:$c1, i32MoveImm:$c2)), bb:$dst)");
3888 opNames_["TCEBRGEUri"] = "BGEU";
3889 }
3890
3891 os << "}" << std::endl;
3892 }
3893}
MachineInfo::supportsPortGuardedJump
static bool supportsPortGuardedJump(const TTAMachine::Machine &machine, bool inverted, const TCEString &opName)
Definition MachineInfo.cc:703
TDGen::writePortGuardedJumpDefPair
bool writePortGuardedJumpDefPair(std::ostream &os, const TCEString &tceop1, const TCEString &tceop2, bool fp=false)
Definition TDGen.cc:3897
TDGen::writeInstrDef
void writeInstrDef(std::ostream &o, const std::string &instrDefName, const std::string &outs, const std::string &ins, const std::string &asmString, const std::string &pattern)
Definition TDGen.cc:4626

References abortWithError, assert, TTAMachine::Machine::controlUnit(), MachineInfo::getOpset(), mach_, opNames_, MachineInfo::supportsBoolRegisterGuardedJumps(), MachineInfo::supportsPortGuardedJump(), MachineInfo::supportsPortGuardedJumps(), writeInstrDef(), and writePortGuardedJumpDefPair().

Referenced by writeControlFlowInstrDefs().

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◆ writeConstShiftPat()

void TDGen::writeConstShiftPat ( std::ostream &  os,
const TCEString &  nodeName,
const TCEString &  opNameBase,
int  i 
)
protected

Definition at line 8577 of file TDGen.cc.

8579 {
8580
8581 if (!mach_.is64bit()) {
8582 TCEString opName = opNameBase; opName << i << "_32rr";
8583 if (opNames_.find(opName) != opNames_.end()) {
8584 os << "def : Pat<(i32 (" << nodeName
8585 << " R32IRegs:$val, (i32 " << i << "))), ("
8586 << opName << " R32IRegs:$val)>;" << std::endl;
8587 }
8588 } else {
8589 TCEString opName = opNameBase; opName << i << "_64rr";
8590 if (opNames_.find(opName) != opNames_.end()) {
8591 os << "def : Pat<(i64 (" << nodeName
8592 << " R64IRegs:$val, (i64 " << i << "))), ("
8593 << opName << " R64IRegs:$val)>;" << std::endl;
8594 }
8595 }
8596}

References TTAMachine::Machine::is64bit(), mach_, and opNames_.

Referenced by createConstShiftPatterns().

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◆ writeControlFlowInstrDefs()

void TDGen::writeControlFlowInstrDefs ( std::ostream &  os)
protected

Writes control flow instructions definitions and patterns

Definition at line 3616 of file TDGen.cc.

3616 {
3617
3618 writeCondBranchDefs(os);
3619
3620 writeCallDef(os);
3621}
TDGen::writeCallDef
void writeCallDef(std::ostream &o)
Definition TDGen.cc:3955
TDGen::writeCondBranchDefs
void writeCondBranchDefs(std::ostream &os)
Definition TDGen.cc:3661

References writeCallDef(), and writeCondBranchDefs().

Referenced by writeInstrInfo().

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◆ writeEmulationPattern()

void TDGen::writeEmulationPattern ( std::ostream &  o,
const Operation &  op,
const OperationDAG &  dag 
)
protected

Writes operation emulation pattern in .td format to an output stream.

Parameters
oOutput stream to write the definition to.
opEmulated operation.
dagEmulation pattern.

Definition at line 4800 of file TDGen.cc.

4803 {
4804
4805 char operandCh = mach_.is64bit() ? OT_REG_LONG : OT_REG_INT;
4806
4807 const OperationDAGNode* res = *(dag.endNodes().begin());
4808 if (dag.endNodes().empty()) {
4809 std::cerr << "end nodes of dag for operation: " << op.name()
4810 << " is empty!" << std::endl;
4811 assert(false);
4812 }
4813
4814 const OperationNode* opNode = dynamic_cast<const OperationNode*>(res);
4815 if (opNode == NULL) {
4816 assert(dag.inDegree(*res) == 1);
4817 const OperationDAGEdge& edge = dag.inEdge(*res, 0);
4818 res = dynamic_cast<OperationNode*>(&dag.tailNode(edge));
4819 assert(res != NULL);
4820 }
4821
4822 int inputCount = op.numberOfInputs();
4823
4824 bool ok = true;
4825 std::string llvmPat = llvmOperationPattern(op, operandCh);
4826 if (llvmPat == "") {
4827 std::cerr << "unknown op: " << op.name() << std::endl;
4828 }
4829 assert(llvmPat != "" && "Unknown operation to emulate.");
4830
4831 boost::format match1(llvmPat);
4832
4833 int outputs = op.numberOfOutputs();
4834
4835 std::string operandTypes;
4836 for (int i = 0; i < outputs; i++) {
4837 operandTypes += operandChar(op.operand(i+inputCount + 1));
4838 }
4839
4840 for (int i = 0; i < op.numberOfInputs(); i++) {
4841 char inputType = operandChar(op.operand(i+1));
4842
4843 std::string immDef = immediateOperandNameForEmulatedOperation(
4844 dag, op.operand(i + 1));
4845
4846 operandTypes += inputType;
4847 match1 % operandToString(op.operand(i + 1), false, inputType, immDef);
4848 }
4849 if (ok) {
4850 o << "def : Pat<(" << match1.str() << "), "
4851 << dagNodeToString(op, dag, *res, true, operandTypes)
4852 << ">;" << std::endl;
4853
4854 // need to generate emulation patterns for boolean out
4855 // for these comparison operations.
4856 if (op.name() == "LTF" || op.name() == "LTUF" ||
4857 op.name() == "EQF" || op.name() == "EQUF" ||
4858 op.name() == "GEF" || op.name() == "GEUF" ||
4859 op.name() == "LEF" || op.name() == "LEUF" ||
4860 op.name() == "GTF" || op.name() == "GTUF" ||
4861 op.name() == "NEF" || op.name() == "NEUF" ||
4862 op.name() == "EQ" || op.name() == "NE" ||
4863 op.name() == "EQ64" || op.name() == "NE64" ||
4864 op.name() == "GE" ||op.name() == "GEU" ||
4865 op.name() == "GE64" ||op.name() == "GEU64" ||
4866 op.name() == "GT" || op.name() == "GTU" ||
4867 op.name() == "GT64" || op.name() == "GTU64" ||
4868 op.name() == "LE" || op.name() == "LEU" ||
4869 op.name() == "LE64" || op.name() == "LEU64" ||
4870 op.name() == "LT" || op.name() == "LTU" ||
4871 op.name() == "LT64" || op.name() == "LTU64" ||
4872 op.name() == "LTD" || op.name() == "LTUD" ||
4873 op.name() == "EQD" || op.name() == "EQUD" ||
4874 op.name() == "GED" || op.name() == "GEUD" ||
4875 op.name() == "LED" || op.name() == "LEUD" ||
4876 op.name() == "GTD" || op.name() == "GTUD" ||
4877 op.name() == "NED" || op.name() == "NEUD" ||
4878 op.name() == "ORDD" || op.name() == "UORDD" ||
4879 op.name() == "ORDF" || op.name() == "UORDF") {
4880 std::string boolOperandTypes = operandTypes;
4881 boolOperandTypes[0] = 'b';
4882 o << "def : Pat<(" << match1.str() << "), "
4883 << dagNodeToString(op, dag, *res, true, boolOperandTypes)
4884 << ">;" << std::endl;
4885 }
4886 }
4887}
TDGen::immediateOperandNameForEmulatedOperation
std::string immediateOperandNameForEmulatedOperation(const OperationDAG &, const Operand &operand)
Definition TDGen.cc:7584

References assert, dagNodeToString(), OperationDAG::endNodes(), immediateOperandNameForEmulatedOperation(), BoostGraph< GraphNode, GraphEdge >::inDegree(), BoostGraph< GraphNode, GraphEdge >::inEdge(), TTAMachine::Machine::is64bit(), llvmOperationPattern(), mach_, Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), Operation::operand(), operandChar(), operandToString(), OT_REG_INT, OT_REG_LONG, and BoostGraph< GraphNode, GraphEdge >::tailNode().

Referenced by writeInstrInfo().

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◆ writeGetPointerAdjustmentQuery()

void TDGen::writeGetPointerAdjustmentQuery ( std::ostream &  os) const
protected

Writes query method for retrieving LLVM instruction for pointer adjustment and suitable offset value.

Some machines may not SUBrri definition (second operand can not take an immediate) and, therefore, pointer adjustments must use other operation for it.

Definition at line 7522 of file TDGen.cc.

7522 {
7523
7524 TCEString ADDIMM = mach_.is64bit() ? "ADD64ssa" : "ADDrri";
7525 TCEString SUBIMM = mach_.is64bit() ? "SUB64ssa" : "SUBrri";
7526
7527
7528
7529 boost::format queryTmpl(
7530 "// <MI opcode, adjusted offset>\n"
7531 "std::tuple<int, int> GeneratedTCEPlugin::getPointerAdjustment(\n"
7532 " int offset) const {\n"
7533 " if (offset > 0) // Adjust pointer up.\n"
7534 " return std::make_tuple(TCE::%1%, offset);\n"
7535 " else\n"
7536 " return std::make_tuple(TCE::%2%, %3%);\n"
7537 "}\n");
7538
7539 // Prefer non-negative offset
7540 if (opNames_.count(SUBIMM)) {
7541 os << queryTmpl % ADDIMM % SUBIMM % "-offset" << std::endl;
7542 return;
7543 } else if (opNames_.count("ADDrri")) {
7544 os << queryTmpl % ADDIMM % ADDIMM % "offset" << std::endl;
7545 return;
7546 }
7547
7548 THROW_EXCEPTION(
7549 InvalidData,
7550 "The machine is missing ADD or SUB operation with direct\n"
7551 "immediate source for pointer adjustment operations.");
7552 return;
7553}
THROW_EXCEPTION
#define THROW_EXCEPTION(exceptionType, message)
Exception wrapper macro that automatically includes file name, line number and function name where th...
Definition Exception.hh:39
ADDIMM
#define ADDIMM
Definition TCEFrameInfo.cc:62

References ADDIMM, TTAMachine::Machine::is64bit(), mach_, opNames_, SUBIMM, and THROW_EXCEPTION.

Referenced by writeBackendCode().

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◆ writeGuardRegisterClassInfo()

void TDGen::writeGuardRegisterClassInfo ( std::ostream &  o)
protected

Writes register class for registers usable as guard.

Call this after all regular register definitions are written (after all calls to writeRegisterDef());

Definition at line 2008 of file TDGen.cc.

2008 {
2009
2010 int bits = mach_.is64bit() ? 64 : 32;
2011 o << std::endl
2012 << "// #################################" << std::endl
2013 << "// Register class definitions for guards" << std::endl;
2014
2015 if (llvmGuardRegs_.empty()) {
2016 o << "// No guard registers in this machine" << std::endl;
2017 RegInfo reg = {"noGuardReg", 0};
2018 std::string name = "NOGUARD";
2019 writeRegisterDef(o, reg, name, "R1", "", RESERVED);
2020 o << "def " << guardRegTemplateName
2021 << "Regs : RegisterClass<\"TCE\", [i1], " << bits << ", (add "
2022 << name << ")>;" << std::endl;
2023 return;
2024 }
2025
2026 o << "def " << guardRegTemplateName
2027 << "Regs : RegisterClass<\"TCE\", [i1], " << bits << ", (add ";
2028 bool firstItem = true;
2029 for (auto& regDef : llvmGuardRegs_) {
2030 if (firstItem) {
2031 o << regDef;
2032 firstItem = false;
2033 continue;
2034 }
2035 o << ", " << regDef;
2036 }
2037 o << ")> {" << std::endl;
2038 o << " let Size=" << bits << ";" << std::endl;
2039 o << "}" << std::endl;
2040 o << "// #################################" << std::endl << std::endl;
2041}
TDGen::llvmGuardRegs_
std::vector< std::string > llvmGuardRegs_
The LLVM register defs used as guards.
Definition TDGen.hh:599

References guardRegTemplateName, TTAMachine::Machine::is64bit(), llvmGuardRegs_, mach_, RESERVED, and writeRegisterDef().

Referenced by writeRegisterInfo().

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◆ writeHWLoopDef()

void TDGen::writeHWLoopDef ( std::ostream &  os)
protected

Writes hwloop instructions and patterns.

Definition at line 3627 of file TDGen.cc.

3627 {
3628 os << std::endl << "// Hardware loop instructions" << std::endl;
3629 if (mach_.controlUnit()->hasOperation("hwloop")) {
3630 os << "let isTerminator=1 in {" << std::endl
3631 << " def HWLOOPii : InstTCE<(outs), (ins i32imm0:$rIter, "
3632 "i32imm0:$rInstr), \"\", []>;"
3633 << std::endl
3634 << " def HWLOOPri : InstTCE<(outs), (ins i32imm0:$rIter, "
3635 "i32imm0:$rInstr), \"\", []>;"
3636 << std::endl
3637 << "}" << std::endl
3638 << "def : Pat<(int_set_loop_iterations i32imm0:$rIter), "
3639 "(HWLOOPii i32imm0:$rIter, 0)>;"
3640 << std::endl
3641 << "def : Pat<(int_set_loop_iterations R32IRegs:$rIter), "
3642 "(HWLOOPri R32IRegs:$rIter, 0)>;"
3643 << std::endl;
3644 opNames_["HWLOOPii"] = "hwloop";
3645 opNames_["HWLOOPri"] = "hwloop";
3646 }
3647
3648 // Write loop jump pseudo
3649 os << "let isTerminator = 1 in {" << std::endl
3650 << " def LJUMP : InstTCE<(outs), (ins brtarget:$dst), \"\", []>;"
3651 << std::endl
3652 << "}" << std::endl
3653 << std::endl;
3654 opNames_["LJUMP"] = "PSEUDO";
3655}
TTAMachine::FunctionUnit::hasOperation
virtual bool hasOperation(const std::string &name) const
Definition FunctionUnit.cc:330

References TTAMachine::Machine::controlUnit(), TTAMachine::FunctionUnit::hasOperation(), mach_, and opNames_.

Referenced by writeInstrInfo().

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◆ writeImmediateDef()

void TDGen::writeImmediateDef ( std::ostream &  o,
const std::string &  defName,
const std::string &  operandType,
const std::string &  predicate 
)
protectedvirtual

Writes single immediate operand definitions to the stream.

Parameters
oThe output stream.
defNameThe name of the immediate operand definition.
operandTypeThe target type (i.e "i32").
predicateThe predicate expression without return statement or ';' at the end.

Definition at line 4610 of file TDGen.cc.

4614 {
4615
4616 o << "def " << defName << " : Operand<" << operandType
4617 << "> , ImmLeaf<" << operandType << ", [{" << std::endl
4618 << " return " << predicate << ";}]>;" << std::endl;
4619}

Referenced by createConstantMaterializationPatterns(), writeIntegerImmediateDefs(), and writeMoveImmediateDefs().

◆ writeInstrDef()

void TDGen::writeInstrDef ( std::ostream &  o,
const std::string &  instrDefName,
const std::string &  outs,
const std::string &  ins,
const std::string &  asmString,
const std::string &  pattern 
)
protected

Writes LLVM instruction definition in TCE format to the stream.

Definition at line 4626 of file TDGen.cc.

4632 {
4633
4634 o << "def " << instrDefName << " : InstTCE<" << std::endl
4635 << " (outs " << outs << ")," << std::endl
4636 << " (ins " << ins << ")," << std::endl
4637 << " \"" << asmString << "\", " << std::endl
4638 << " [" << pattern << "]>;" << std::endl;
4639}

Referenced by writeCondBranchDefs(), and writePortGuardedJumpDefPair().

◆ writeInstrFormats()

void TDGen::writeInstrFormats ( std::ostream &  o)
protected

Writes details about instruction formatting

Parameters
oOutput stream to the file.

Definition at line 4255 of file TDGen.cc.

4255 {
4256 o << "//" << endl;
4257 o << "// TCE Instruction formats." << endl;
4258 o << "//" << endl;
4259 o << "// Only one simple format is currently available" << endl;
4260 o << "//" << endl;
4261 o << "// Automatically generated file, do not edit!" << endl;
4262 o << "//" << endl;
4263 o << "" << endl;
4264 o << "class InstTCE<dag outOps, dag inOps, string asmstr," << endl;
4265 o << " list<dag> pattern = []," << endl;
4266 o << " InstrItinClass itin = IT_FU>" << endl;
4267 o << " : Instruction {" << endl;
4268 o << " let Namespace = \"TCE\";" << endl;
4269 o << " dag InOperandList = inOps;" << endl;
4270 o << " dag OutOperandList = outOps;" << endl;
4271 o << " let AsmString = asmstr;" << endl;
4272 o << " let Pattern = pattern;" << endl;
4273 o << " let Itinerary = itin;" << endl;
4274 o << "}" << endl;
4275 o << "" << endl;
4276 o << "class Pseudo<dag outOps, dag inOps," << endl;
4277 o << " string asmstr, list<dag> pattern>" << endl;
4278 o << " : InstTCE<outOps, inOps, asmstr, pattern>;" << endl;
4279}

Referenced by initializeBackendContents().

◆ writeInstrInfo()

void TDGen::writeInstrInfo ( std::ostream &  os)
protected

Writes all machine instructions to instruction info .td file.

Parameters
osOutput stream to the file.
Note
This todo marking is from TDGenSIMD

Definition at line 3384 of file TDGen.cc.

3384 {
3385
3386 writeCallSeqStart(os);
3387
3388 OperationDAGSelector::OperationSet opNames;
3389 OperationDAGSelector::OperationSet requiredOps =
3390 LLVMBackend::llvmRequiredOpset(true, littleEndian_, mach_.is64bit());
3391
3392 const TTAMachine::Machine::FunctionUnitNavigator fuNav =
3393 mach_.functionUnitNavigator();
3394
3395 OperationPool opPool;
3396
3397 for (int i = 0; i < fuNav.count(); i++) {
3398 const TTAMachine::FunctionUnit* fu = fuNav.item(i);
3399 for (int o = 0; o < fu->operationCount(); o++) {
3400 const std::string opName = fu->operation(o)->name();
3401 opNames.insert(StringTools::stringToUpper(opName));
3402 }
3403 }
3404
3405 if (littleEndian_) {
3406 if (mach_.is64bit()) {
3407 opNames_["ST64fa"] = "ST64";
3408 opNames_["ST64fs"] = "ST64";
3409 opNames_["ST64ha"] = "ST64";
3410 opNames_["ST64hs"] = "ST64";
3411 opNames_["ST64da"] = "ST64";
3412 opNames_["ST64ds"] = "ST64";
3413
3414 opNames_["LD64fa"] = "LD64";
3415 opNames_["LD64fs"] = "LD64";
3416 opNames_["LD64ha"] = "LD64";
3417 opNames_["LD64hs"] = "LD64";
3418 opNames_["LD64da"] = "LD64";
3419 opNames_["LD64ds"] = "LD64";
3420 }
3421
3422 if (mach_.hasOperation("LD32")) {
3423 opNames_["LD32fr"] = "LD32";
3424 opNames_["LD32fi"] = "LD32";
3425
3426 opNames_["LD32hr"] = "LD32";
3427 opNames_["LD32hi"] = "LD32";
3428
3429 } else if (mach_.hasOperation("LDU32")) {
3430 opNames_["LD32fr"] = "LDU32";
3431 opNames_["LD32fi"] = "LDU32";
3432
3433 opNames_["LD32hr"] = "LDU32";
3434 opNames_["LD32hi"] = "LDU32";
3435 }
3436 opNames_["ST32fr"] = "ST32";
3437 opNames_["ST32fi"] = "ST32";
3438
3439 opNames_["ST32hr"] = "ST32";
3440 opNames_["ST32hi"] = "ST32";
3441
3442 opNames_["ST16hr"] = "ST16";
3443 opNames_["ST16hi"] = "ST16";
3444 } else {
3445 opNames_["LDWfr"] = "LDW";
3446 opNames_["LDWfi"] = "LDW";
3447 opNames_["LDWhr"] = "LDW";
3448 opNames_["LDWhi"] = "LDW";
3449
3450 opNames_["STWfr"] = "STW";
3451 opNames_["STWfi"] = "STW";
3452
3453 opNames_["STWhr"] = "STW";
3454 opNames_["STWhi"] = "STW";
3455 opNames_["STHhr"] = "STH";
3456 opNames_["STHhi"] = "STH";
3457 }
3458
3459 // Some global/address immediate if conversion fails
3460 // so commented out.
3461 // TODO: ^ up-to-date comment? ^
3462 if (hasConditionalMoves_) {
3463
3464 if (mach_.is64bit()) {
3465 truePredOps_["MOV64ss"] = "PRED_TRUE_MOV64ss";
3466 falsePredOps_["MOV64ss"] = "PRED_FALSE_MOV64ss";
3467 }
3468
3469 truePredOps_["MOVI32rr"] = "PRED_TRUE_MOVI32rr";
3470 falsePredOps_["MOVI32rr"] = "PRED_FALSE_MOVI32rr";
3471 truePredOps_["MOVI1rr"] = "PRED_TRUE_MOVI1rr";
3472 falsePredOps_["MOVI1rr"] = "PRED_FALSE_MOVI1rr";
3473 }
3474
3475 OperationDAGSelector::OperationSet::const_iterator iter = opNames.begin();
3476 for (; iter != opNames.end(); iter++) {
3477 OperationDAGSelector::OperationSet::iterator r =
3478 requiredOps.find(*iter);
3479 if (r != requiredOps.end()) {
3480 requiredOps.erase(r);
3481 }
3482 Operation& op = opPool.operation((*iter).c_str());
3483 bool skipPattern = false;
3484
3485 if (&op == &NullOperation::instance()) {
3486 continue;
3487 }
3488
3489 // TODO: Allow multioutput (remove last or)
3490 if (!operationCanBeMatched(op)) {
3491 // TODO: write opeation def without graphs
3492 if (&op != &NullOperation::instance()) {
3493 skipPattern = true;
3494 if (Application::verboseLevel() > 0) {
3495 Application::logStream()
3496 << "Skipped writing operation pattern for "
3497 << op.name() << endl;
3498 }
3499 } else {
3500 // NULL op - ignore
3501 continue;
3502 }
3503 }
3504
3505 // TODO: remove this. For now MIMO operation patterns are not
3506 // supported by tablegen.
3507 if (op.numberOfOutputs() > 1) {
3508 skipPattern = true;
3509 continue;
3510 }
3511
3512 if (op.isVectorOperation()) {
3513 if (isVectorLoadOperation(op) || isVectorStoreOperation(op)) {
3514 writeVectorMemoryOperationDefs(os, op, skipPattern);
3515 } else if (isVectorBitwiseOperation(op)) {
3516 writeVectorBitwiseOperationDefs(os, op, skipPattern);
3517 } else {
3518 writeVectorOperationDefs(os, op, skipPattern);
3519 }
3520 } else {
3521 writeOperationDefs(os, op, skipPattern);
3522 }
3523 }
3524
3525 writeVectorRegisterMoveDefs(os);
3526 writeScalarToVectorDefs(os);
3527 writeVectorBitConversions(os);
3528 writeScalarOperationExploitations(os);
3529 writeVectorLoadStoreOperationExploitations(os);
3530 writeVectorTruncStoreDefs(os);
3531 writeVectorImmediateWriteDefs(os);
3532
3533 // Call operations.
3534 writeControlFlowInstrDefs(os);
3535
3536 // Hardware loop instructions
3537 writeHWLoopDef(os);
3538
3539 // Emulated operations.
3540 for (iter = requiredOps.begin(); iter != requiredOps.end(); iter++) {
3541 const Operation& op = opPool.operation((*iter).c_str());
3542
3543 if (&op == &NullOperation::instance()) {
3544 std::string msg = "Required OP '" + *iter + "' not found.";
3545 throw InvalidData(__FILE__, __LINE__, __func__, msg);
3546 }
3547
3548 const OperationDAGSelector::OperationDAGList emulationDAGs =
3549 OperationDAGSelector::findDags(op.name(), allOpNames_, immInfo_);
3550
3551 if (emulationDAGs.empty()) {
3552 if (Application::verboseLevel() >
3553 Application::VERBOSE_LEVEL_DEFAULT) {
3554 Application::logStream() << "Warning: Operation '" << *iter
3555 << "' not supported." << endl;
3556 }
3557 } else {
3558 /// @note This todo marking is from TDGenSIMD
3559 // TODO: write all dags of operation (first as normal, the rest
3560 // as pattern)
3561 writeEmulationPattern(os, op, emulationDAGs.smallestNodeCount());
3562 }
3563 }
3564
3565 createByteExtLoadPatterns(os);
3566 createShortExtLoadPatterns(os);
3567 if (mach_.is64bit()) {
3568 create32BitExtLoadPatterns(os);
3569 }
3570
3571 writeBooleanStorePatterns(os);
3572
3573 writeMiscPatterns(os);
3574 createSelectPatterns(os);
3575 createConstantMaterializationPatterns(os);
3576 createConstShiftPatterns(os);
3577 createBoolAndHalfLoadPatterns(os);
3578}
LLVMBackend::llvmRequiredOpset
static OperationDAGSelector::OperationSet llvmRequiredOpset(bool includeFloatOps, bool isLittleEndian, bool bits64)
Definition LLVMBackend.cc:151
OperationDAGSelector::OperationSet
TCETools::CIStringSet OperationSet
Definition OperationDAGSelector.hh:88
OperationDAGSelector::findDags
static OperationDAGList findDags(const std::string &opName, OperationSet opSet, const ImmInfo *immInfo=nullptr)
Definition OperationDAGSelector.cc:57
TDGen::writeVectorLoadStoreOperationExploitations
void writeVectorLoadStoreOperationExploitations(std::ostream &o)
Definition TDGen.cc:2704
TDGen::writeVectorBitwiseOperationDefs
void writeVectorBitwiseOperationDefs(std::ostream &o, Operation &op, bool skipPattern)
Definition TDGen.cc:2657
TDGen::createSelectPatterns
virtual void createSelectPatterns(std::ostream &os)
Definition TDGen.cc:7065
TDGen::isVectorStoreOperation
bool isVectorStoreOperation(const Operation &op) const
Definition TDGen.cc:1977
TDGen::writeHWLoopDef
void writeHWLoopDef(std::ostream &o)
Definition TDGen.cc:3627
TDGen::writeBooleanStorePatterns
void writeBooleanStorePatterns(std::ostream &os)
Definition TDGen.cc:4568
TDGen::writeControlFlowInstrDefs
void writeControlFlowInstrDefs(std::ostream &os)
Definition TDGen.cc:3616
TDGen::isVectorLoadOperation
bool isVectorLoadOperation(const Operation &op) const
Definition TDGen.cc:1965
TDGen::writeScalarToVectorDefs
void writeScalarToVectorDefs(std::ostream &o) const
Definition TDGen.cc:2388
TDGen::isVectorBitwiseOperation
bool isVectorBitwiseOperation(const Operation &op) const
Definition TDGen.cc:1995
TDGen::writeCallSeqStart
void writeCallSeqStart(std::ostream &os)
Definition TDGen.cc:7944
TDGen::createByteExtLoadPatterns
void createByteExtLoadPatterns(std::ostream &os)
Definition TDGen.cc:6531
TDGen::writeVectorImmediateWriteDefs
void writeVectorImmediateWriteDefs(std::ostream &instrInfoTD)
Definition TDGen.cc:3216
TDGen::writeVectorMemoryOperationDefs
void writeVectorMemoryOperationDefs(std::ostream &o, Operation &op, bool skipPattern)
Definition TDGen.cc:2261
TDGen::createConstantMaterializationPatterns
virtual void createConstantMaterializationPatterns(std::ostream &os)
Definition TDGen.cc:7458
TDGen::writeVectorOperationDefs
void writeVectorOperationDefs(std::ostream &o, Operation &op, bool skipPattern)
Definition TDGen.cc:2164
TDGen::writeVectorTruncStoreDefs
void writeVectorTruncStoreDefs(std::ostream &o) const
Definition TDGen.cc:2318
TDGen::writeVectorRegisterMoveDefs
void writeVectorRegisterMoveDefs(std::ostream &o)
Definition TDGen.cc:2270
TDGen::createShortExtLoadPatterns
void createShortExtLoadPatterns(std::ostream &os)
Definition TDGen.cc:6691
TDGen::writeVectorBitConversions
void writeVectorBitConversions(std::ostream &o) const
Definition TDGen.cc:2418
TDGen::writeOperationDefs
void writeOperationDefs(std::ostream &o, Operation &op, bool skipPattern)
Definition TDGen.cc:4312
TDGen::writeScalarOperationExploitations
void writeScalarOperationExploitations(std::ostream &o)
Definition TDGen.cc:2475
TDGen::writeMiscPatterns
void writeMiscPatterns(std::ostream &o)
Definition TDGen.cc:8465
TDGen::createBoolAndHalfLoadPatterns
void createBoolAndHalfLoadPatterns(std::ostream &os)
Definition TDGen.cc:8608
TDGen::create32BitExtLoadPatterns
void create32BitExtLoadPatterns(std::ostream &os)
Definition TDGen.cc:6808
TDGen::writeEmulationPattern
void writeEmulationPattern(std::ostream &o, const Operation &op, const OperationDAG &dag)
Definition TDGen.cc:4800
TDGen::createConstShiftPatterns
void createConstShiftPatterns(std::ostream &os)
Definition TDGen.cc:8599

References __func__, allOpNames_, TTAMachine::Machine::Navigator< ComponentType >::count(), create32BitExtLoadPatterns(), createBoolAndHalfLoadPatterns(), createByteExtLoadPatterns(), createConstantMaterializationPatterns(), createConstShiftPatterns(), createSelectPatterns(), createShortExtLoadPatterns(), falsePredOps_, OperationDAGSelector::findDags(), TTAMachine::Machine::functionUnitNavigator(), hasConditionalMoves_, TTAMachine::Machine::hasOperation(), immInfo_, NullOperation::instance(), TTAMachine::Machine::is64bit(), isVectorBitwiseOperation(), isVectorLoadOperation(), Operation::isVectorOperation(), isVectorStoreOperation(), TTAMachine::Machine::Navigator< ComponentType >::item(), littleEndian_, LLVMBackend::llvmRequiredOpset(), Application::logStream(), mach_, TTAMachine::HWOperation::name(), Operation::name(), Operation::numberOfOutputs(), OperationPool::operation(), TTAMachine::FunctionUnit::operation(), operationCanBeMatched(), TTAMachine::FunctionUnit::operationCount(), opNames_, OperationDAGSelector::OperationDAGList::smallestNodeCount(), StringTools::stringToUpper(), truePredOps_, Application::VERBOSE_LEVEL_DEFAULT, Application::verboseLevel(), writeBooleanStorePatterns(), writeCallSeqStart(), writeControlFlowInstrDefs(), writeEmulationPattern(), writeHWLoopDef(), writeMiscPatterns(), writeOperationDefs(), writeScalarOperationExploitations(), writeScalarToVectorDefs(), writeVectorBitConversions(), writeVectorBitwiseOperationDefs(), writeVectorImmediateWriteDefs(), writeVectorLoadStoreOperationExploitations(), writeVectorMemoryOperationDefs(), writeVectorOperationDefs(), writeVectorRegisterMoveDefs(), and writeVectorTruncStoreDefs().

Referenced by generateBackend(), and initializeBackendContents().

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◆ writeIntegerImmediateDefs()

void TDGen::writeIntegerImmediateDefs ( std::ostream &  o,
const ImmInfo &  iivs 
)
protected

Writes unique immediate operands (ImmLeafs) for all operations that can have short immediates to transported to theirs operands.

The names of the immediate operands are stored in i32immOperandDefs_ map. Note: operations, that can not have short immediates to be trasported at all, do not entry in the map.

Parameters
oThe output stream.
iivsThe immediate info.

Definition at line 649 of file TDGen.cc.

651 {
652
653 TCEString immDefBaseName = mach_.is64bit() ? "i64imm" : "i32imm";
654 TCEString immDefType = mach_.is64bit() ? "i64" : "i32";
655 int bits = mach_.is64bit() ? 64 : 32;
656 using ImmBounds = std::pair<int64_t, int64_t>;
657
658 OperationPool opPool;
659 std::set<const Operation*> opset;
660 for (auto& iiv : iivs) {
661 const Operation& op = opPool.operation(iiv.first.first.c_str());
662 if (&op == &NullOperation::instance())
663 continue;
664 opset.insert(&op);
665 }
666
667 std::map<ImmBounds, std::string> immediateClasses;
668 int immId = 0;
669 for (auto op : opset) {
670 // Divide input operands into groups that can be swapped together.
671 // Commutative instructions with immediate operands in the patterns
672 // are defined having the immediate operands as last operands
673 // (e.g. ADDrri). For these a combined ImmLeaf is created (union of
674 // each of ImmLeaf of the inputs).
675 std::vector<std::set<int>> inputGroups;
676 for (int opdIdx = 1; opdIdx < op->numberOfInputs() + 1; opdIdx++) {
677 const Operand& opd = op->operand(opdIdx);
678
679 bool alreadyGrouped = false;
680 for (auto& group : inputGroups) {
681 if (group.count(opdIdx)) {
682 alreadyGrouped = true;
683 break;
684 }
685 }
686 if (alreadyGrouped) continue;
687
688 inputGroups.push_back(std::set<int>());
689 inputGroups.back().insert(opdIdx);
690 for (int otherOpdIdx : opd.swap()) {
691 inputGroups.back().insert(otherOpdIdx);
692 }
693 }
694
695 // For each input operand group assign an ImmLeaf operand definition.
696 // The names of ImmLeaf definitions are stored in immOperandDefs_,
697 // which is accessed using operation and operand as the key.
698 for (auto group : inputGroups) {
699 ImmBounds widestImmBound;
700 for (auto idx : group) {
701 // Determine max transportable immediate value range.
702 if (iivs.count(*op, idx)) {
703 // perform union
704 ImmBounds immBound = iivs.immediateValueBounds(
705 *op, idx, bits);
706 widestImmBound.first = std::min(
707 widestImmBound.first, immBound.first);
708 widestImmBound.second = std::max(
709 widestImmBound.second, immBound.second);
710 }
711 // Can not transport immediates at all.
712 if (widestImmBound == ImmBounds()) continue;
713
714 // immediateClasses stores unique encountered immediate value
715 // ranges.
716 if (immediateClasses.count(widestImmBound) == 0) {
717 std::string immDefName = std::string("i32imm")
718 + Conversion::toString(immId);
719 if (!mach_.is64bit()) {
720 immediateClasses[widestImmBound] = immDefName;
721 }
722 writeImmediateDef(
723 o, immDefName, "i32", immediatePredicate(
724 widestImmBound.first, widestImmBound.second));
725
726 immDefName = std::string("i64imm")
727 + Conversion::toString(immId);
728
729 if (mach_.is64bit()) {
730 immediateClasses[widestImmBound] = immDefName;
731 }
732
733 writeImmediateDef(
734 o, immDefName, "i64", immediatePredicate(
735 widestImmBound.first, widestImmBound.second));
736
737 immId++;
738
739 }
740 immOperandDefs_[ImmInfo::key(*op, idx)] =
741 immediateClasses.at(widestImmBound);
742 }
743 }
744 }
745}
TDGen::immediatePredicate
std::string immediatePredicate(int64_t lowerBoundInclusive, uint64_t upperBoundInclusive)
Definition TDGen.cc:7560

References ImmInfo::count(), immediatePredicate(), ImmInfo::immediateValueBounds(), immOperandDefs_, NullOperation::instance(), TTAMachine::Machine::is64bit(), ImmInfo::key(), mach_, OperationPool::operation(), Operand::swap(), Conversion::toString(), and writeImmediateDef().

Referenced by writeOperandDefs().

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◆ writeMiscPatterns()

void TDGen::writeMiscPatterns ( std::ostream &  o)
protected

Definition at line 8465 of file TDGen.cc.

8465 {
8466 if (!mach_.is64bit()) {
8467 o << "// zero extending moves used in some patterns" << std::endl
8468 << "def ANDext : InstTCE<(outs R32IRegs:$dst), (ins R1Regs:$src, i32imm:$val), \"\", []>;" << std::endl
8469 << "def PRED_TRUE_ANDext : InstTCE<(outs R32IRegs:$dst),"
8470 << " (ins R1Regs:$pred, R1Regs:$src, i32imm:$val), \"\", []>;" << std::endl
8471 << "def PRED_FALSE_ANDext : InstTCE<(outs R32IRegs:$dst),"
8472 << " (ins R1Regs:$pred, R1Regs:$src, i32imm:$val),\"\", []>;" << std::endl
8473 << "def XORbicmp: InstTCE<(outs R1Regs:$dst),"
8474 << " (ins R1Regs:$src, i32imm:$val), \"\", []>;" << std::endl
8475 << "def PRED_TRUE_XORbicmp: InstTCE<(outs R1Regs:$dst),"
8476 << " (ins R1Regs:$pred, R1Regs:$src, i32imm:$val), \"\", []>;" << std::endl
8477 << "def PRED_FALSE_XORbicmp: InstTCE<(outs R1Regs:$dst),"
8478 << " (ins R1Regs:$pred, R1Regs:$src, i32imm:$val), \"\", []>;" << std::endl;
8479
8480 o << "def: Pat <(i32 (anyext R1Regs:$src)), (ANDext R1Regs:$src, 1)>;" << std::endl
8481 << "def: Pat <(i32 (zext R1Regs:$src)), (ANDext R1Regs:$src, 1)>;" << std::endl;
8482
8483 o << "// select of 1 or 0." << std::endl
8484 << "def : Pat<(i32 (select R1Regs:$c, (i32 1), (i32 0))),"
8485 << " (ANDext R1Regs:$c, 1)>;" << std::endl;
8486
8487 o << std::endl
8488 << "def: Pat <(i32 (sext R1Regs:$src)), (SUBrir 0,(ANDext R1Regs:$src, 1))>;"
8489 << std::endl;
8490
8491 o << "// ------ Shift (emulation) patterns. " << std::endl
8492 << "def: Pat <(i32 (shl R32IRegs:$val, (i32 1))),"
8493 << " (ADDrrr R32Regs:$val, R32Regs:$val)>;" << std::endl
8494 << "def: Pat <(i32 (TCESHLConst R32IRegs:$val, (i32 1))),"
8495 << " (ADDrrr R32IRegs:$val, R32IRegs:$val)>;" << std::endl;
8496
8497 o << "// ----- Global addresses, constant pool entries ------" << std::endl
8498 << "def TCEGlobalAddr : SDNode<\"TCEISD::GLOBAL_ADDR\", SDTIntUnaryOp>;" << std::endl
8499 << "def TCEConstPool : SDNode<\"TCEISD::CONST_POOL\", SDTIntUnaryOp>;" << std::endl
8500 << "def : Pat<(TCEGlobalAddr tglobaladdr:$in), (MOVI32ri tglobaladdr:$in)>;" << std::endl
8501 << "def : Pat<(TCEGlobalAddr tconstpool:$in), (MOVI32ri tconstpool:$in)>;" << std::endl
8502 << "def : Pat<(TCEConstPool tglobaladdr:$in), (MOVI32ri tglobaladdr:$in)>;" << std::endl
8503 << "def : Pat<(TCEConstPool tconstpool:$in), (MOVI32ri tconstpool:$in)>;" << std::endl;
8504
8505
8506 o << "// some peephole patterns." << std::endl
8507 << "// 1-bit select with imm values - xor or mov." << std::endl
8508 << "def : Pat<(i1 (select R1Regs:$c, (i1 0), (i1 -1))), (XORbbj R1Regs:$c, 1)>;" << std::endl
8509 << "def : Pat<(i1 (select R1Regs:$c, (i1 -1), (i1 0))), (MOVI1rr R1Regs:$c)>;" << std::endl
8510 << "def : Pat<(i1 (select R1Regs:$c, (i1 -1), R1Regs:$F)), (IORbbb R1Regs:$c, R1Regs:$F)>;" << std::endl
8511 << "def : Pat<(i1 (select R1Regs:$c, R1Regs:$T, (i1 0))), (ANDbbb R1Regs:$c, R1Regs:$T)>;" << std::endl;
8512
8513 o << "// 1-bit comparison between booleans - xor or xnor(implemented with 2 xors)" << std::endl
8514 << "def : Pat<(i1 (setne R1Regs:$op1, R1Regs:$op2)), (XORbbb R1Regs:$op1, R1Regs:$op2)>;" << std::endl
8515 << "// TODO: should the temp values be converted to i32? usually more i32 regs." << std::endl
8516 << "def : Pat<(i1 (seteq R1Regs:$op1, R1Regs:$op2)), (XORbbj (XORbbb R1Regs:$op1, R1Regs:$op2), 1)>;" << std::endl;
8517
8518 o << "def TCEBlockAddress : SDNode<\"TCEISD::BLOCK_ADDR\", SDTIntUnaryOp>;" << std::endl
8519 << "def : Pat<(TCEBlockAddress tblockaddress:$src1), (MOVI32ri tblockaddress:$src1)>;" << std::endl;
8520
8521 } else {
8522 o << "// zero extending moves used in some patterns" << std::endl
8523 << "def ANDext : InstTCE<(outs R64IRegs:$dst),"
8524 << " (ins R1Regs:$src, i64imm:$val), \"\", []>;" << std::endl
8525 << "def PRED_TRUE_ANDext : InstTCE<(outs R64IRegs:$dst),"
8526 << " (ins R1Regs:$pred, R1Regs:$src, i64imm:$val), \"\", []>;" << std::endl
8527 << "def PRED_FALSE_ANDext : InstTCE<(outs R64IRegs:$dst),"
8528 << " (ins R1Regs:$pred, R1Regs:$src, i64imm:$val),\"\", []>;" << std::endl
8529 << "def XORbicmp: InstTCE<(outs R1Regs:$dst),"
8530 << " (ins R1Regs:$src, i64imm:$val), \"\", []>;" << std::endl
8531 << "def PRED_TRUE_XORbicmp: InstTCE<(outs R1Regs:$dst),"
8532 << " (ins R1Regs:$pred, R1Regs:$src, i64imm:$val), \"\", []>;" << std::endl
8533 << "def PRED_FALSE_XORbicmp: InstTCE<(outs R1Regs:$dst),"
8534 << " (ins R1Regs:$pred, R1Regs:$src, i64imm:$val), \"\", []>;" << std::endl;
8535
8536 o << "def: Pat <(i64 (anyext R1Regs:$src)), (ANDext R1Regs:$src, 1)>;" << std::endl
8537 << "def: Pat <(i64 (zext R1Regs:$src)), (ANDext R1Regs:$src, 1)>;" << std::endl;
8538
8539 o << "// select of 1 or 0." << std::endl
8540 << "def : Pat<(i64 (select R1Regs:$c, (i64 1), (i64 0))), (ANDext R1Regs:$c, 1)>;" << std::endl;
8541
8542 o << std::endl
8543 << "def: Pat <(i64 (sext R1Regs:$src)), (SUB64sas 0,(ANDext R1Regs:$src, 1))>;"
8544 << std::endl;
8545
8546 o << "// ------ Shift (emulation) patterns. " << std::endl
8547 << "def: Pat <(i64 (shl R64IRegs:$val, (i64 1))),"
8548 << " (ADD64sss R64Regs:$val, R64Regs:$val)>;" << std::endl
8549 << "def: Pat <(i64 (TCESHLConst R64IRegs:$val, (i64 1))),"
8550 << " (ADD64sss R64IRegs:$val, R64IRegs:$val)>;" << std::endl;
8551
8552 o << "// ----- Global addresses, constant pool entries ------" << std::endl
8553 << "def TCEGlobalAddr : SDNode<\"TCEISD::GLOBAL_ADDR\", SDTIntUnaryOp>;" << std::endl
8554 << "def TCEConstPool : SDNode<\"TCEISD::CONST_POOL\", SDTIntUnaryOp>;" << std::endl
8555 << "def : Pat<(TCEGlobalAddr tglobaladdr:$in), (MOVI64sa tglobaladdr:$in)>;" << std::endl
8556 << "def : Pat<(TCEGlobalAddr tconstpool:$in), (MOVI64sa tconstpool:$in)>;" << std::endl
8557 << "def : Pat<(TCEConstPool tglobaladdr:$in), (MOVI64sa tglobaladdr:$in)>;" << std::endl
8558 << "def : Pat<(TCEConstPool tconstpool:$in), (MOVI64sa tconstpool:$in)>;" << std::endl;
8559
8560 o << "// some peephole patterns." << std::endl
8561 << "// 1-bit select with imm values - xor or mov." << std::endl
8562 << "def : Pat<(i1 (select R1Regs:$c, (i1 0), (i1 -1))), (XOR64bbj R1Regs:$c, 1)>;" << std::endl
8563 << "def : Pat<(i1 (select R1Regs:$c, (i1 -1), (i1 0))), (MOVI1rr R1Regs:$c)>;" << std::endl
8564 << "def : Pat<(i1 (select R1Regs:$c, (i1 -1), R1Regs:$F)), (IOR64bbb R1Regs:$c, R1Regs:$F)>;" << std::endl
8565 << "def : Pat<(i1 (select R1Regs:$c, R1Regs:$T, (i1 0))), (AND64bbb R1Regs:$c, R1Regs:$T)>;" << std::endl;
8566
8567 o << "// 1-bit comparison between booleans - xor or xnor(implemented with 2 xors)" << std::endl
8568 << "def : Pat<(i1 (setne R1Regs:$op1, R1Regs:$op2)), (XOR64bbb R1Regs:$op1, R1Regs:$op2)>;" << std::endl
8569 << "// TODO: should the temp values be converted to i64? usually more i64 regs." << std::endl
8570 << "def : Pat<(i1 (seteq R1Regs:$op1, R1Regs:$op2)), (XOR64bbj (XOR64bbb R1Regs:$op1, R1Regs:$op2), 1)>;" << std::endl;
8571
8572 o << "def TCEBlockAddress : SDNode<\"TCEISD::BLOCK_ADDR\", SDTIntUnaryOp>;" << std::endl
8573 << "def : Pat<(TCEBlockAddress tblockaddress:$src1), (MOVI64sa tblockaddress:$src1)>;" << std::endl;
8574 }
8575}

References TTAMachine::Machine::is64bit(), and mach_.

Referenced by writeInstrInfo().

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◆ writeMoveImmediateDefs()

void TDGen::writeMoveImmediateDefs ( std::ostream &  o)
protected

Writes immediate operand definitions that are used for MOV instructions.

Creates immediate operand definitions for immediate to register instructions (MOVI), that only accept supported immediate values.

Note
Implemented currently only for i32 registers.

Definition at line 756 of file TDGen.cc.

756 {
757 using MCC = MachineConnectivityCheck;
758
759 TCEString immDefBaseName = mach_.is64bit() ? "i64imm" : "i32imm";
760 TCEString immDefType = mach_.is64bit() ? "i64" : "i32";
761 int bits = mach_.is64bit() ? 64 : 32;
762
763 std::pair<int64_t, uint64_t> moveImm{ 0, 0 };
764 for (auto& rf : mach_.registerFileNavigator()) {
765 if (rf->width() != bits) continue;
766
767 for (auto& bus : mach_.busNavigator()) {
768 if (!MCC::busConnectedToRF(*bus, *rf)
769 || bus->immediateWidth() == 0) {
770 continue;
771 }
772
773 if (bus->immediateWidth() >= bits) {
774 moveImm.first = -(1ll << (bits-1));
775 moveImm.second = (1ll << bits)-1;
776 break;
777 } else {
778 std::pair<int64_t, uint64_t> imm =
779 MathTools::bitsToIntegerRange<int64_t, uint64_t>(
780 bus->immediateWidth(),
781 bus->signExtends());
782
783 moveImm.first = std::min(moveImm.first, imm.first);
784 moveImm.second = std::max(moveImm.second, imm.second);
785 }
786 }
787 }
788
789 for (auto& iu : mach_.immediateUnitNavigator()) {
790 for (auto& it : mach_.instructionTemplateNavigator()) {
791 int supportedWidth = it->supportedWidth(*iu);
792 if (supportedWidth >= bits) {
793 moveImm.first = -(1ll << (bits-1));
794 moveImm.second = (1ll << bits)-1;
795 break;
796 } else {
797 std::pair<int64_t, uint64_t> imm =
798 MathTools::bitsToIntegerRange<int64_t, uint64_t>(
799 supportedWidth, iu->signExtends());
800
801 moveImm.first = std::min(moveImm.first, imm.first);
802 moveImm.second = std::max(moveImm.second, imm.second);
803 }
804 }
805 }
806
807 writeImmediateDef(o, "i32MoveImm", "i32", immediatePredicate(
808 moveImm.first, moveImm.second));
809
810 writeImmediateDef(o, "i64MoveImm", "i64", immediatePredicate(
811 moveImm.first, moveImm.second));
812
813}

References TTAMachine::Machine::busNavigator(), immediatePredicate(), TTAMachine::Machine::immediateUnitNavigator(), TTAMachine::Machine::instructionTemplateNavigator(), TTAMachine::Machine::is64bit(), mach_, TTAMachine::Machine::registerFileNavigator(), and writeImmediateDef().

Referenced by writeOperandDefs().

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◆ writeOperandDefs()

void TDGen::writeOperandDefs ( std::ostream &  o)
protected

Writes all short immediate definitions to the stream.

Parameters
oThe output stream.

Definition at line 621 of file TDGen.cc.

621 {
622 assert(immInfo_ != nullptr
623 && "Short immediate analysis results are not available!");
624
625 o << "// Immediate definitions for TCE instructions." << std::endl;
626
627 writeIntegerImmediateDefs(o, *immInfo_);
628
629 o << std::endl;
630 o << "// Immediate definitions for immediate to register moves."
631 << std::endl;
632 writeMoveImmediateDefs(o);
633
634 o << std::endl;
635}
TDGen::writeIntegerImmediateDefs
void writeIntegerImmediateDefs(std::ostream &o, const ImmInfo &iivis)
Definition TDGen.cc:649
TDGen::writeMoveImmediateDefs
void writeMoveImmediateDefs(std::ostream &o)
Definition TDGen.cc:756

References assert, immInfo_, writeIntegerImmediateDefs(), and writeMoveImmediateDefs().

Referenced by initializeBackendContents().

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◆ writeOperationDef()

void TDGen::writeOperationDef ( std::ostream &  o,
Operation &  op,
const std::string &  operandTypes,
const std::string &  attrs,
bool  skipPattern,
std::string  backendPrefix = "" 
)
protected

Writes a single operation def for single operation.

Parameters
oOutput stream to write the definition to.
opOperation to write definition for.
operandTypesvalue types of operands.

Definition at line 4649 of file TDGen.cc.

4652 {
4653 assert (operandTypes.size() > 0);
4654
4655 // Skip definition if the operation has immediate to operand which the
4656 // machine can not transport short immediates to.
4657 if (!areImmediateOperandsLegal(op, operandTypes)) {
4658 if (Application::verboseLevel() >
4659 Application::VERBOSE_LEVEL_DEFAULT) {
4660 Application::logStream()
4661 << "Skipped writing operation pattern for: "
4662 << op.name() + operandTypes
4663 << ": Can not have immediate operand."
4664 << std::endl;
4665 }
4666 return;
4667 }
4668
4669 char operandChar = mach_.is64bit() ? OT_REG_LONG : OT_REG_INT;
4670
4671 std::string outputs, inputs, asmstr, pattern;
4672 outputs = "(outs" + patOutputs(op, operandTypes) + ")";
4673 inputs = "(ins " + patInputs(op, operandTypes) + ")";
4674 std::string predicatedInputs =
4675 "(ins GuardRegs:$pred, " +patInputs(op, operandTypes)+ ")";
4676
4677 asmstr = "\"\"";
4678
4679 if (!skipPattern) {
4680 if (llvmOperationPattern(op, operandChar) != "" ||
4681 op.dagCount() == 0) {
4682 OperationDAG* trivial = createTrivialDAG(op);
4683 pattern = operationPattern(op, *trivial, operandTypes);
4684 delete trivial;
4685 } else {
4686 auto* dagToUse = getMatchableOperationDAG(op);
4687 if (dagToUse)
4688 pattern = operationPattern(op, *dagToUse, operandTypes);
4689 }
4690 }
4691
4692 if (attrs != "") {
4693 o << "let" << attrs << " in { " << std::endl;
4694 }
4695
4696 std::string opcEnum =
4697 StringTools::stringToUpper(op.name()) + operandTypes;
4698
4699 o << "def " << opcEnum << " : "
4700 << "InstTCE<"
4701 << outputs << ", "
4702 << inputs << ", "
4703 << asmstr << ", " ;
4704 if(operandTypes[0] == 'b') { //instruction can be used for comparison
4705 o << "[" << pattern << "]>"
4706 << std::endl
4707 << "{ let isCompare = 1;}" << std::endl;
4708 } else {
4709 o << "[" << pattern << "]>;"
4710 << std::endl;
4711 }
4712
4713 bool opCanBePredicated = canBePredicated(op, operandTypes);
4714
4715 if (opCanBePredicated) {
4716 // write predicated versions
4717 o << "def PRED_TRUE_" << opcEnum << " : "
4718 << "InstTCE<"
4719 << outputs << ", "
4720 << predicatedInputs << ", "
4721 << asmstr << ", "
4722 << "[]>;"
4723 << std::endl;
4724 // write predicated versions
4725 o << "def PRED_FALSE_" << opcEnum << " : "
4726 << "InstTCE<"
4727 << outputs << ", "
4728 << predicatedInputs << ", "
4729 << asmstr << ", "
4730 << "[]>;"
4731 << std::endl;
4732 }
4733
4734 if (attrs != "") {
4735 o << "}" << std::endl;
4736 }
4737 opNames_[opcEnum] = backendPrefix + op.name();
4738
4739 if (opCanBePredicated) {
4740 opNames_["PRED_TRUE_" + opcEnum] = "?" + backendPrefix + op.name();
4741 opNames_["PRED_FALSE_" + opcEnum] = "!" + backendPrefix + op.name();
4742 truePredOps_[opcEnum] = "PRED_TRUE_" + opcEnum;
4743 falsePredOps_[opcEnum] = "PRED_FALSE_" + opcEnum;
4744 }
4745}
TDGen::createTrivialDAG
OperationDAG * createTrivialDAG(Operation &op)
Definition TDGen.cc:6093
TDGen::canBePredicated
bool canBePredicated(Operation &op, const std::string &operandTypes)
Definition TDGen.cc:7665
TDGen::patOutputs
std::string patOutputs(const Operation &op, const std::string &oprTypes)
Definition TDGen.cc:6074
TDGen::operationPattern
std::string operationPattern(const Operation &op, const OperationDAG &dag, const std::string &operandTypes)
Definition TDGen.cc:5421
TDGen::areImmediateOperandsLegal
bool areImmediateOperandsLegal(const Operation &operation, const std::string &operandTypes) const
Definition TDGen.cc:7617
TDGen::patInputs
std::string patInputs(const Operation &op, const std::string &oprTypes)
Definition TDGen.cc:6043

References areImmediateOperandsLegal(), assert, canBePredicated(), createTrivialDAG(), Operation::dagCount(), falsePredOps_, getMatchableOperationDAG(), TTAMachine::Machine::is64bit(), llvmOperationPattern(), Application::logStream(), mach_, Operation::name(), operandChar(), operationPattern(), opNames_, OT_REG_INT, OT_REG_LONG, patInputs(), patOutputs(), StringTools::stringToUpper(), truePredOps_, Application::VERBOSE_LEVEL_DEFAULT, and Application::verboseLevel().

Referenced by writeOperationDefs(), writeOperationDefs(), and writeVectorOperationDef().

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◆ writeOperationDefs() [1/2]

void TDGen::writeOperationDefs ( std::ostream &  o,
Operation &  op,
bool  skipPattern 
)
protected

Writes scalar operation definition(s).

Parameters
oOutput stream to write the definition to.
opOperation to write definition for.
skipPatternTrue, if skip pattern generation.
Note
This todo marking is from TDGen.
This todo marking is from TDGen.

Definition at line 4312 of file TDGen.cc.

4315 {
4316
4317 std::string attrs;
4318
4319 // These white listed operations have mayLoad/mayStore flag
4320 // inferred from the llvm pattern and declaring it
4321 // explicitly will display warning in tablegen.
4322 if (op.name() != "LDQ" && op.name() != "LDQU" &&
4323 op.name() != "LDH" && op.name() != "LDHU" &&
4324 op.name() != "LDW" && op.name() != "LDD" &&
4325 op.name() != "STQ" && op.name() != "STH" &&
4326 op.name() != "STW" && op.name() != "STD" &&
4327 op.name() != "ALDQ" && op.name() != "ALDQU" &&
4328 op.name() != "ALDH" && op.name() != "ALDHU" &&
4329 op.name() != "ALDW" && op.name() != "ALDD" &&
4330 op.name() != "ASTQ" && op.name() != "ASTH" &&
4331 op.name() != "ASTW" && op.name() != "ASTD" &&
4332
4333 op.name() != "LD8" && op.name() != "LDU8" &&
4334 op.name() != "LD16" && op.name() != "LDU16" &&
4335 op.name() != "LD32" && op.name() != "LDU32" &&
4336 op.name() != "LD64" &&
4337 op.name() != "ST8" && op.name() != "ST16" &&
4338 op.name() != "ST32" && op.name() != "ST64" &&
4339 op.name() != "ALD8" && op.name() != "ALDU8" &&
4340 op.name() != "ALD16" && op.name() != "ALDU16" &&
4341 op.name() != "ALD32" && op.name() != "ALDU32" &&
4342 op.name() != "ALD64" &&
4343 op.name() != "AST8" && op.name() != "AST16" &&
4344 op.name() != "AST32" && op.name() != "AST64" &&
4345 op.name() != "CAS") {
4346
4347 if (op.readsMemory()) attrs += " mayLoad = 1";
4348 if (op.readsMemory() && op.writesMemory()) attrs += ", ";
4349 if (op.writesMemory()) attrs += " mayStore = 1";
4350 }
4351
4352 // no bool outs for some operatios
4353 if (op.name() == "CFI" || op.name() == "CFIU") {
4354 writeOperationDef(o, op, "rf", attrs, skipPattern);
4355 return;
4356 }
4357
4358 if (op.name() == "CDL" || op.name() == "CDLU") {
4359 writeOperationDef(o, op, "sd", attrs, skipPattern);
4360 return;
4361 }
4362
4363 if (op.name() == "CLD" || op.name() == "CLDU") {
4364 writeOperationDef(o, op, "ds", attrs, skipPattern);
4365 return;
4366 }
4367
4368 // no bool outs for some operatios
4369 if (op.name() == "CFD") {
4370 writeOperationDef(o, op, "df", attrs, skipPattern);
4371 return;
4372 }
4373
4374 // no bool outs for some operatios
4375 if (op.name() == "CDF") {
4376 writeOperationDef(o, op, "fd", attrs, skipPattern);
4377 return;
4378 }
4379
4380 // rotations are allways n x n -> n bits.
4381 if (op.name() == "ROTL" || op.name() == "ROTR" ||
4382 op.name() == "SHL" || op.name() == "SHR" || op.name() == "SHRU") {
4383 writeOperationDefs(o, op, "rrr", attrs, skipPattern);
4384 return;
4385 }
4386
4387 if (op.name() == "SXHW" || op.name() == "SXQW") {
4388 writeOperationDef(o, op, "rr", attrs, skipPattern);
4389 return;
4390 }
4391
4392 if (op.name() == "SXW64" || op.name() == "ZXW64") {
4393 writeOperationDef(o, op, "ss", attrs, skipPattern);
4394 return;
4395 }
4396
4397 // these can have 1-bit inputs
4398 // TODO: this is lacking some 64-bit ops??
4399 if (op.name() == "XOR" || op.name() == "IOR" || op.name() == "AND" ||
4400 op.name() == "ANDN" || op.name() == "ADD" || op.name() == "SUB" ||
4401 op.name() == "XOR64" || op.name() == "IOR64" || op.name() == "AND64") {
4402 writeOperationDefs(o, op, "bbb", attrs, skipPattern);
4403 }
4404
4405 if (op.name() == "SELECT") {
4406 if (!hasConditionalMoves_) {
4407 writeOperationDef(o, op, "rrrb", attrs, skipPattern);
4408 writeOperationDef(o, op, "riib", attrs, skipPattern);
4409 writeOperationDef(o, op, "rrib", attrs, skipPattern);
4410 writeOperationDef(o, op, "rirb", attrs, skipPattern);
4411 writeOperationDef(o, op, "bbbb", attrs, skipPattern);
4412 writeOperationDef(o, op, "bjjb", attrs, skipPattern);
4413 writeOperationDef(o, op, "bjbb", attrs, skipPattern);
4414 writeOperationDef(o, op, "bbjb", attrs, skipPattern);
4415 // TODO: what about floating-point values?
4416 writeOperationDef(o, op, "fffb", attrs, skipPattern);
4417 writeOperationDef(o, op, "hhhb", attrs, skipPattern);
4418
4419 // ADFs with boolan values in GPRs
4420 writeOperationDef(o, op, "rrrr", attrs, skipPattern);
4421 writeOperationDef(o, op, "riir", attrs, skipPattern);
4422 writeOperationDef(o, op, "rrir", attrs, skipPattern);
4423 writeOperationDef(o, op, "rirr", attrs, skipPattern);
4424 writeOperationDef(o, op, "bbbr", attrs, skipPattern);
4425 writeOperationDef(o, op, "bjjr", attrs, skipPattern);
4426 writeOperationDef(o, op, "bjbr", attrs, skipPattern);
4427 writeOperationDef(o, op, "bbjr", attrs, skipPattern);
4428 // TODO: what about floating-point values?
4429 writeOperationDef(o, op, "fffr", attrs, skipPattern);
4430 writeOperationDef(o, op, "hhhr", attrs, skipPattern);
4431
4432 hasSelect_ = true;
4433 return;
4434 } else {
4435 std::cerr << "The target architecture has both"
4436 << "conditional moves and select instruction."
4437 << "Ignoring select and using conditional moves instead"
4438 << std::endl;
4439 return;
4440 }
4441 }
4442
4443 // store likes this. store immediate to immediate address
4444 if (op.numberOfInputs() == 2 && op.numberOfOutputs() == 0) {
4445 Operand& operand1 = op.operand(1);
4446 Operand& operand2 = op.operand(2);
4447 /// @note This todo marking is from TDGen.
4448 // TODO: add an else branch here for float immediates
4449 if ((operand1.type() == Operand::UINT_WORD ||
4450 operand1.type() == Operand::SINT_WORD ||
4451 operand1.type() == Operand::RAW_DATA) &&
4452 (operand2.type() == Operand::UINT_WORD ||
4453 operand2.type() == Operand::SINT_WORD ||
4454 operand2.type() == Operand::RAW_DATA)) {
4455
4456 if (mach_.is64bit()) {
4457 writeOperationDef(o, op, "aa", attrs, skipPattern);
4458 } else {
4459 writeOperationDef(o, op, "ii", attrs, skipPattern);
4460 }
4461 }
4462 }
4463
4464 std::string operandTypes = createDefaultOperandTypeString(op);
4465 // this the ordinary def
4466
4467 // then try with immediates.
4468 /// @note This todo marking is from TDGen.
4469 // TODO: this should be 2^n loop instead of n loop, to get
4470 // all permutations.
4471
4472 writeOperationDefs(o, op, operandTypes, attrs, skipPattern);
4473
4474 // then with boolean outs, and vector versions.
4475 if (op.numberOfOutputs() == 1 && !op.readsMemory()) {
4476 Operand& outOperand = op.operand(op.numberOfInputs()+1);
4477 if (outOperand.type() == Operand::UINT_WORD ||
4478 outOperand.type() == Operand::SINT_WORD ||
4479 outOperand.type() == Operand::ULONG_WORD ||
4480 outOperand.type() == Operand::SLONG_WORD) {
4481
4482 // 32/64 to 1-bit operations
4483 operandTypes[0] = OT_REG_BOOL;
4484 writeOperationDefs(o, op, operandTypes, attrs, skipPattern);
4485 }
4486
4487 // create vector versions.
4488 }
4489}
TDGen::writeOperationDef
void writeOperationDef(std::ostream &o, Operation &op, const std::string &operandTypes, const std::string &attrs, bool skipPattern, std::string backendPrefix="")
Definition TDGen.cc:4649

References createDefaultOperandTypeString(), hasConditionalMoves_, hasSelect_, TTAMachine::Machine::is64bit(), mach_, Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), Operation::operand(), OT_REG_BOOL, Operand::RAW_DATA, Operation::readsMemory(), Operand::SINT_WORD, Operand::SLONG_WORD, Operand::type(), Operand::UINT_WORD, Operand::ULONG_WORD, writeOperationDef(), writeOperationDefs(), and Operation::writesMemory().

Referenced by writeInstrInfo(), and writeOperationDefs().

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◆ writeOperationDefs() [2/2]

void TDGen::writeOperationDefs ( std::ostream &  o,
Operation &  op,
const std::string &  operandTypes,
const std::string &  attrs,
bool  skipPattern,
std::string  backendPrefix = "" 
)
protected

Writes operation defs for single operation, with different immediate params.

Parameters
oOutput stream to write the definition to.
opOperation to write definition for.
operandTypesvalue types of operands.

Definition at line 4516 of file TDGen.cc.

4518 {
4519
4520 // first without imms.
4521 writeOperationDef(o, op, operandTypes, attrs, skipPattern, backendPrefix);
4522
4523 for (int i = 0; i < op.numberOfInputs(); i++) {
4524 bool canSwap = false;
4525
4526 // those ops SHOULD be can-swap but are not. kludge-fix.
4527 // consider making them can-swap.
4528 if (op.name() == "ALDQ" || op.name() == "ALDQU" ||
4529 op.name() == "ALDH" || op.name() == "ALDHU" ||
4530 op.name() == "ALDW" || op.name() == "ALDD" ||
4531 op.name() == "ASTQ" || op.name() == "ASTH" ||
4532 op.name() == "ASTW" || op.name() == "ASTD" ||
4533
4534 op.name() == "ALD8" || op.name() == "ALDU8" ||
4535 op.name() == "ALD16"|| op.name() == "ALDU16" ||
4536 op.name() == "ALD32"|| op.name() == "ALD64" ||
4537 op.name() == "AST8" || op.name() == "AST16" ||
4538 op.name() == "AST32"|| op.name() == "AST64") {
4539 canSwap = true;
4540 }
4541
4542 for (int j = i+1 ; j < op.numberOfInputs(); j++) {
4543 if (op.canSwap(i+1, j+1)) {
4544 canSwap = true;
4545 break;
4546 }
4547 }
4548 // setcc of LLVM is not commutative and get confused if we don't generate
4549 // a pattern with immediate elsewhere than the last operand
4550 canSwap = canSwap && !(op.name().upper() == "EQ" || op.name().upper() == "NE");
4551
4552 if (!canSwap) {
4553 std::string opTypes = operandTypes;
4554 char& c = opTypes[i + op.numberOfOutputs()];
4555 c = regOperandCharToImmOperandChar(c);
4556 if (c) {
4557 writeOperationDef(o, op, opTypes, attrs, skipPattern, backendPrefix);
4558 }
4559 }
4560 }
4561}
regOperandCharToImmOperandChar
char regOperandCharToImmOperandChar(char c)
Definition TDGen.cc:4491
Operation::canSwap
virtual bool canSwap(int id1, int id2) const
Definition Operation.cc:470
TCEString::upper
TCEString upper() const
Definition TCEString.cc:86

References Operation::canSwap(), Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), regOperandCharToImmOperandChar(), TCEString::upper(), and writeOperationDef().

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◆ writeOperationDefUsingGivenOperandTypes()

void TDGen::writeOperationDefUsingGivenOperandTypes ( std::ostream &  o,
Operation &  op,
bool  skipPattern,
std::vector< TDGenerator::ValueType >  inputs,
std::vector< TDGenerator::ValueType >  outputs,
TCEString  instrSuffix = "" 
)
protected

Writes operation definition using given operand types.

Changes the operands to match the provided ones, after which a definition is written. Finally, original operands are restored.

Parameters
oOutput stream.
opOperation used to create new operation definitions.
skipPatternIf true, operation pattern writing is skipped.
inputsInput operand types for the new operation.
outputsOutput operand types for the new operation.
instrSuffixOptional suffix that will be added to instruction name.

Definition at line 1896 of file TDGen.cc.

1902 {
1903 assert(
1904 inputs.size() == static_cast<size_t>(op.numberOfInputs()) &&
1905 "Given input operand count doesn't match operation's count.");
1906 assert(
1907 outputs.size() == static_cast<size_t>(op.numberOfOutputs()) &&
1908 "Given output operand count doesn't match operation's count.");
1909
1910 std::vector<ValueType> oldInputs;
1911 std::vector<ValueType> oldOutputs;
1912
1913 // Change operands to match the provided ones.
1914 for (int i = 0; i < op.numberOfInputs(); ++i) {
1915 Operand& input = op.input(i);
1916 oldInputs.push_back(ValueType(input));
1917
1918 ValueType vt = inputs[i];
1919 input.setType(vt.operandType());
1920 input.setElementWidth(vt.subwWidth_);
1921 input.setElementCount(vt.subwCount_);
1922 }
1923
1924 for (int i = 0; i < op.numberOfOutputs(); ++i) {
1925 Operand& output = op.output(i);
1926 oldOutputs.push_back(ValueType(output));
1927
1928 ValueType vt = outputs[i];
1929 output.setType(vt.operandType());
1930 output.setElementWidth(vt.subwWidth_);
1931 output.setElementCount(vt.subwCount_);
1932 }
1933
1934 // Write new operation definition.
1935 TCEString types = createDefaultOperandTypeString(op) + instrSuffix;
1936 writeVectorOperationDef(o, op, types, "", skipPattern);
1937
1938 // Restore old operands.
1939 for (int i = 0; i < op.numberOfInputs(); ++i) {
1940 Operand& input = op.input(i);
1941
1942 ValueType vt = oldInputs[i];
1943 input.setType(vt.operandType());
1944 input.setElementWidth(vt.subwWidth_);
1945 input.setElementCount(vt.subwCount_);
1946 }
1947
1948 for (int i = 0; i < op.numberOfOutputs(); ++i) {
1949 Operand& output = op.output(i);
1950
1951 ValueType vt = oldOutputs[i];
1952 output.setType(vt.operandType());
1953 output.setElementWidth(vt.subwWidth_);
1954 output.setElementCount(vt.subwCount_);
1955 }
1956}
Operand::setElementWidth
virtual void setElementWidth(int elementWidth)
Definition Operand.cc:288
Operand::setType
virtual void setType(OperandType type)
Definition Operand.cc:175
Operand::setElementCount
virtual void setElementCount(int elementCount)
Definition Operand.cc:308
Operation::output
virtual Operand & output(int index) const
Definition Operation.cc:526
Operation::input
virtual Operand & input(int index) const
Definition Operation.cc:503
TDGen::writeVectorOperationDef
void writeVectorOperationDef(std::ostream &o, Operation &op, TCEString valueTypes, const TCEString &attributes, bool skipPattern)
Definition TDGen.cc:2181
TDGenerator::ValueType::subwCount_
int subwCount_
Subword count of the value type.
Definition TDGen.hh:725
TDGenerator::ValueType::operandType
Operand::OperandType operandType() const
Definition TDGen.cc:8826
TDGenerator::ValueType::subwWidth_
int subwWidth_
Subword width of the value type.
Definition TDGen.hh:723

References assert, createDefaultOperandTypeString(), Operation::input(), Operation::numberOfInputs(), Operation::numberOfOutputs(), TDGenerator::ValueType::operandType(), Operation::output(), Operand::setElementCount(), Operand::setElementWidth(), Operand::setType(), TDGenerator::ValueType::subwCount_, TDGenerator::ValueType::subwWidth_, and writeVectorOperationDef().

Referenced by writeScalarOperationExploitations(), writeVectorBitwiseOperationDefs(), and writeVectorLoadStoreOperationExploitations().

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◆ writePatternReplacement()

void TDGen::writePatternReplacement ( std::ostream &  o,
const TCEString &  origPat,
const TCEString &  replacerPat 
) const
protected

Writes a pattern fragment definition.

Parameters
origPatPattern that instruction selector should replace.
replacerPatPattern that will replace the original pattern.

Definition at line 1875 of file TDGen.cc.

1878 {
1879 o << "def : Pat<(" << origPat << "), (" << replacerPat << ")>;" << endl;
1880}

Referenced by writeScalarToVectorDefs(), writeVectorBitConversions(), and writeVectorTruncStoreDefs().

◆ writePortGuardedJumpDefPair()

bool TDGen::writePortGuardedJumpDefPair ( std::ostream &  os,
const TCEString &  tceop1,
const TCEString &  tceop2,
bool  fp = false 
)
protected

Definition at line 3897 of file TDGen.cc.

3898 {
3899
3900 TCEString llvmop1 = TDGen::llvmOperationName(tceop1).upper();
3901 TCEString llvmop2 = TDGen::llvmOperationName(tceop2).upper();
3902
3903 TCEString regclass = fp ? "R32FPRegs" : "R32IRegs";
3904 if (MachineInfo::supportsPortGuardedJump(mach_, false, tceop1) ||
3905 MachineInfo::supportsPortGuardedJump(mach_, true, tceop2)) {
3906
3907 os << std::endl << "let isTerminator = 1, isBranch = 1 in {" << std::endl;
3908
3909 writeInstrDef(os, tceop1+"_JUMP", "",
3910 regclass + ":$cmp1, "+ regclass + ":$cmp2, brtarget:$dst", "",
3911 "(brcc "+ llvmop1 +", "+ regclass + ":$cmp1, " + regclass + ":$cmp2, bb:$dst)");
3912
3913 os << "}" << std::endl;
3914 if (MachineInfo::supportsPortGuardedJump(mach_, false, tceop1)) {
3915 opNames_[tceop1 + "_JUMP"] = tceop1 + "+?jump";
3916 } else {
3917 opNames_[tceop1 + "_JUMP"] = tceop2 + "+!jump";
3918 }
3919 } else {
3920 std::cerr << "Missing "<< tceop1 << " operation as true-guard source"
3921 << " or " << tceop2 << " operation as invarted guard source to jump." << std::endl;
3922 return false;
3923 }
3924
3925 if (MachineInfo::supportsPortGuardedJump(mach_, true, tceop1) ||
3926 MachineInfo::supportsPortGuardedJump(mach_, false, tceop2)) {
3927
3928 os << std::endl << "let isTerminator = 1, isBranch = 1 in {" << std::endl;
3929
3930
3931 writeInstrDef(os, tceop2+"_JUMP", "",
3932 regclass + ":$cmp1, "+ regclass + ":$cmp2, brtarget:$dst", "",
3933 "(brcc "+ llvmop2 +", "+ regclass + ":$cmp1, " + regclass + ":$cmp2, bb:$dst)");
3934
3935 os << "}" << std::endl;
3936
3937 if (MachineInfo::supportsPortGuardedJump(mach_, false, tceop2)) {
3938 opNames_[tceop2 + "_JUMP"] = tceop2 + "+?jump";
3939 } else {
3940 opNames_[tceop2 + "_JUMP"] = tceop1 + "+!jump";
3941 }
3942 } else {
3943 std::cerr << "Missing " << tceop2 << " operation as true-guard source"
3944 << " or " << tceop1 << " operation as inverted guard source to jump."
3945 << std::endl;
3946 return false;
3947 }
3948 return true;
3949}
TDGen::llvmOperationName
virtual TCEString llvmOperationName(const TCEString &opName) const
Definition TDGen.cc:5109

References llvmOperationName(), mach_, opNames_, MachineInfo::supportsPortGuardedJump(), TCEString::upper(), and writeInstrDef().

Referenced by writeCondBranchDefs().

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◆ writeRARegisterInfo()

void TDGen::writeRARegisterInfo ( std::ostream &  o)
protected

Writes return address register definition to the output stream.

Definition at line 3157 of file TDGen.cc.

3157 {
3158 o << "class Rra<string n> : TCEReg<n, []>;" << std::endl;
3159 o << "def RA : Rra<\"return-address\">, ";
3160 o << "DwarfRegNum<[" << dregNum_++ << "]>;";
3161 o << std::endl;
3162 if (mach_.is64bit()) {
3163 o << "def RAReg : RegisterClass<\"TCE\", [i64], 64, (add RA)>;" <<
3164 std::endl;
3165 } else {
3166 o << "def RAReg : RegisterClass<\"TCE\", [i32], 32, (add RA)>;" <<
3167 std::endl;
3168 }
3169}

References dregNum_, TTAMachine::Machine::is64bit(), and mach_.

Referenced by writeRegisterInfo().

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◆ writeRegisterClasses()

void TDGen::writeRegisterClasses ( std::ostream &  o)
protected

Definition at line 816 of file TDGen.cc.

816 {
817
818 o << "class R1<string n, list<Register> aliases> : TCEReg<n, aliases> {"
819 << "}" << std::endl;
820
821 o << "class R32<string n, list<Register> aliases> : TCEReg<n, aliases> {"
822 << "}" << std::endl;
823
824 o << "class R64<string n, list<Register> aliases> : TCEReg<n, aliases> {"
825 << "}" << std::endl;
826
827
828 o << "class R16<string n, list<Register> aliases> : TCEReg<n, aliases> {"
829 << "}" << std::endl;
830}

Referenced by writeRegisterInfo().

◆ writeRegisterDef()

void TDGen::writeRegisterDef ( std::ostream &  o,
const RegInfo &  reg,
const std::string  regName,
const std::string  regTemplate,
const std::string  aliases,
RegType  type 
)
protected

Writes .td definition of a single register to the output stream.

Parameters
oOutput stream to write the definition to.
regInformation about the physical register.
regNameName for the register in the llvm framework.
regTemplateBase class for the register.
aliasesComma-separated list of aliases for this register.

Definition at line 503 of file TDGen.cc.

509 {
510
511 std::string templ = regTemplate;
512
513 o << "def " << regName << " : " << templ
514 << "<\"" << reg.rf << "." << reg.idx
515 << "\", [" << aliases << "]>, DwarfRegNum<"
516 << "[" << dregNum_ << "]>;"
517 << std::endl;
518
519
520 if (type == GPR) {
521 gprRegNames_.push_back(regName);
522 } else if (type == ARGUMENT) {
523 argRegNames_.push_back(regName);
524 } else if (type == RESULT) {
525 argRegNames_.push_back(regName);
526 resRegNames_.push_back(regName);
527 } else {
528 assert(type == RESERVED);
529 }
530
531 regs_[regName] = reg;
532
533 regsInClasses_[regTemplate].push_back(regName);
534
535 if (guardedRegs_.find(reg) != guardedRegs_.end()) {
536 llvmGuardRegs_.push_back(regName);
537 regsInClasses_[guardRegTemplateName].push_back(regName);
538 }
539
540 dregNum_++;
541}

References argRegNames_, ARGUMENT, assert, dregNum_, GPR, gprRegNames_, guardedRegs_, guardRegTemplateName, TDGen::RegInfo::idx, llvmGuardRegs_, regs_, regsInClasses_, RESERVED, resRegNames_, RESULT, and TDGen::RegInfo::rf.

Referenced by write16bitRegisterInfo(), write1bitRegisterInfo(), write32bitRegisterInfo(), write64bitRegisterInfo(), writeGuardRegisterClassInfo(), and writeVectorRegisterNames().

◆ writeRegisterInfo()

bool TDGen::writeRegisterInfo ( std::ostream &  o)
protected

Writes .td definitions of all registers in the machine to an output stream.

Parameters
oOutput stream for the .td definitions.
Returns
True, if the definitions were succesfully generated.

Definition at line 551 of file TDGen.cc.

551 {
552 analyzeRegisters();
553
554 if (!checkRequiredRegisters()) {
555 return false;
556 }
557
558 assert(regs32bit_.size() >= requiredI32Regs_);
559
560 // Write scalar register information without old vector backend registers.
561 writeStartOfRegisterInfo(o);
562 writeRegisterClasses(o);
563 writeRARegisterInfo(o);
564 write1bitRegisterInfo(o);
565// write16bitRegisterInfo(o); // currently not supported properly
566 write32bitRegisterInfo(o);
567 write64bitRegisterInfo(o);
568
569 // Gather and separate all operations to vector and scalar containers.
570 gatherAllMachineOperations();
571
572 // Create register classes for vector operands.
573 analyzeMachineVectorRegisterClasses();
574 // Group registers by width.
575 analyzeMachineRegisters();
576 // Associate register groups properly with register classes.
577 associateRegistersWithVectorRegisterClasses();
578
579 // Write register related information to the .td file.
580 writeVectorRegisterBaseClasses(o);
581 writeVectorRegisterNames(o);
582 writeVectorRegisterClasses(o);
583 writeGuardRegisterClassInfo(o);
584
585 return true;
586}
TDGen::write32bitRegisterInfo
void write32bitRegisterInfo(std::ostream &o)
Definition TDGen.cc:1021
TDGen::writeVectorRegisterNames
void writeVectorRegisterNames(std::ostream &o)
Definition TDGen.cc:2070
TDGen::associateRegistersWithVectorRegisterClasses
void associateRegistersWithVectorRegisterClasses()
Definition TDGen.cc:1709
TDGen::writeGuardRegisterClassInfo
void writeGuardRegisterClassInfo(std::ostream &o)
Definition TDGen.cc:2008
TDGen::analyzeRegisters
void analyzeRegisters()
Definition TDGen.cc:838
TDGen::analyzeMachineRegisters
void analyzeMachineRegisters()
Definition TDGen.cc:1478
TDGen::writeRARegisterInfo
void writeRARegisterInfo(std::ostream &o)
Definition TDGen.cc:3157
TDGen::writeRegisterClasses
void writeRegisterClasses(std::ostream &o)
Definition TDGen.cc:816
TDGen::write1bitRegisterInfo
void write1bitRegisterInfo(std::ostream &o)
Definition TDGen.cc:961
TDGen::checkRequiredRegisters
bool checkRequiredRegisters()
Definition TDGen.cc:3336
TDGen::writeVectorRegisterClasses
void writeVectorRegisterClasses(std::ostream &o) const
Definition TDGen.cc:2102
TDGen::gatherAllMachineOperations
void gatherAllMachineOperations()
Definition TDGen.cc:997
TDGen::write64bitRegisterInfo
void write64bitRegisterInfo(std::ostream &o)
Definition TDGen.cc:1363
TDGen::analyzeMachineVectorRegisterClasses
void analyzeMachineVectorRegisterClasses()
Definition TDGen.cc:1282
TDGen::writeVectorRegisterBaseClasses
void writeVectorRegisterBaseClasses(std::ostream &o) const
Definition TDGen.cc:2047
TDGen::writeStartOfRegisterInfo
void writeStartOfRegisterInfo(std::ostream &o)
Definition TDGen.cc:594

References analyzeMachineRegisters(), analyzeMachineVectorRegisterClasses(), analyzeRegisters(), assert, associateRegistersWithVectorRegisterClasses(), checkRequiredRegisters(), gatherAllMachineOperations(), regs32bit_, requiredI32Regs_, write1bitRegisterInfo(), write32bitRegisterInfo(), write64bitRegisterInfo(), writeGuardRegisterClassInfo(), writeRARegisterInfo(), writeRegisterClasses(), writeStartOfRegisterInfo(), writeVectorRegisterBaseClasses(), writeVectorRegisterClasses(), and writeVectorRegisterNames().

Referenced by initializeBackendContents().

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◆ writeScalarOperationExploitations()

void TDGen::writeScalarOperationExploitations ( std::ostream &  o)
protected

This function writes scalar operation exploitations.

Some scalar operations can be exploited to execute vector operations. For instance, bitwise logical operations are same for any operand width. A 32-bit scalar XOR operation can execute bitwise exclusive OR operation for v32i1, v4i8 and v2i16 vector operands similarly as it does for i32 type.

Definition at line 2475 of file TDGen.cc.

2475 {
2476 o << endl
2477 << endl
2478 << "// Scalar operations exploited to execute small vector operations."
2479 << endl;
2480
2481 // Use minimal architecture NOT/AND/IOR/XOR 32-bit operations to execute
2482 // bitwise vector operations with operands of 32 bits or lower width.
2483 OperationPool opPool;
2484
2485 std::vector<Operation*> scalarBitwiseOps;
2486 scalarBitwiseOps.push_back(&opPool.operation("NOT"));
2487 scalarBitwiseOps.push_back(&opPool.operation("AND"));
2488 scalarBitwiseOps.push_back(&opPool.operation("IOR"));
2489 scalarBitwiseOps.push_back(&opPool.operation("XOR"));
2490 scalarBitwiseOps.push_back(&opPool.operation("NOT64"));
2491 scalarBitwiseOps.push_back(&opPool.operation("AND64"));
2492 scalarBitwiseOps.push_back(&opPool.operation("IOR64"));
2493 scalarBitwiseOps.push_back(&opPool.operation("XOR64"));
2494
2495
2496 for (size_t opI = 0; opI < scalarBitwiseOps.size(); ++opI) {
2497 Operation& op = *scalarBitwiseOps[opI];
2498 if (&op == &NullOperation::instance() ||
2499 !mach_.hasOperation(op.name())) {
2500 continue;
2501 }
2502
2503 int width = 2;
2504
2505 while (width <= op.output(0).width()) {
2506 // Get vector value types for the current width, e.g v4i8, v2i16
2507 // and v32i1 value types for width 32.
2508 std::vector<ValueType> intVecVts =
2509 ValueType::vectorTypesOfWidth(width, true);
2510
2511 for (size_t i = 0; i < intVecVts.size(); ++i) {
2512 ValueType& vecVt = intVecVts[i];
2513 const TCEString vecVtStr = vecVt.valueTypeStr();
2514
2515 if (hasRegisterClassSupport(vecVt)) {
2516 std::vector<ValueType> inputs;
2517 std::vector<ValueType> outputs;
2518
2519 for (int i = 0; i < op.numberOfInputs(); ++i) {
2520 inputs.push_back(vecVt);
2521 }
2522 for (int i = 0; i < op.numberOfOutputs(); ++i) {
2523 outputs.push_back(vecVt);
2524 }
2525
2526 writeOperationDefUsingGivenOperandTypes(
2527 o, op, false, inputs, outputs, vecVtStr);
2528 }
2529 }
2530
2531 width *= 2;
2532 }
2533 }
2534
2535 // Use LDQ/LDH/LDW and STQ/STH/STW operations to create memory access
2536 // operations for vector operands of 32-bit or lower width.
2537 int memDataOpndWidth = 2;
2538
2539 const char* defaultType = mach_.is64bit() ? "i64" : "i32";
2540
2541 while (memDataOpndWidth <= MAX_SCALAR_WIDTH) {
2542 std::vector<ValueType> vecVts =
2543 ValueType::vectorTypesOfWidth(memDataOpndWidth);
2544
2545 for (size_t i = 0; i < vecVts.size(); ++i) {
2546 const ValueType& dataOpndVt = vecVts[i];
2547 const TCEString dataOpndVtStr = dataOpndVt.valueTypeStr();
2548
2549 if (hasRegisterClassSupport(dataOpndVt)) {
2550 Operation* op = NULL;
2551 if (memDataOpndWidth <= 8) {
2552 if (littleEndian_) {
2553 op = &opPool.operation("LD8");
2554 } else {
2555 op = &opPool.operation("LDQ");
2556 }
2557 } else if (memDataOpndWidth <= 16) {
2558 if (littleEndian_) {
2559 op = &opPool.operation("LD16");
2560 } else {
2561 op = &opPool.operation("LDH");
2562 }
2563 } else if (memDataOpndWidth <= 32){
2564 if (littleEndian_) {
2565 op = &opPool.operation("LD32");
2566 } else {
2567 op = &opPool.operation("LDW");
2568 }
2569 } else {
2570 if (littleEndian_) {
2571 op = &opPool.operation("LD64");
2572 } else {
2573 op = &opPool.operation("LDD");
2574 std::cerr << "Warning: SIMD support with "
2575 << "big-endian adf is deprecated" << std::endl;
2576 }
2577 }
2578
2579 std::vector<ValueType> inputs;
2580 std::vector<ValueType> outputs;
2581
2582 // Address operand 32 or 64 bits
2583 inputs.push_back(ValueType(defaultType));
2584 // Data operand.
2585 outputs.push_back(dataOpndVt);
2586
2587 writeOperationDefUsingGivenOperandTypes(
2588 o, *op, false, inputs, outputs, dataOpndVtStr);
2589 }
2590 }
2591
2592 for (size_t i = 0; i< vecVts.size(); ++i) {
2593 const ValueType& dataOpndVt = vecVts[i];
2594 const TCEString dataOpndVtStr = dataOpndVt.valueTypeStr();
2595
2596 if (hasRegisterClassSupport(dataOpndVt)) {
2597 Operation* op = NULL;
2598 if (memDataOpndWidth <= 8) {
2599 if (littleEndian_) {
2600 op = &opPool.operation("ST8");
2601 } else {
2602 op = &opPool.operation("STQ");
2603 }
2604 } else if (memDataOpndWidth <= 16) {
2605 if (littleEndian_) {
2606 op = &opPool.operation("ST16");
2607 } else {
2608 op = &opPool.operation("STH");
2609 }
2610 } else if (memDataOpndWidth <= 32) {
2611 if (littleEndian_) {
2612 op = &opPool.operation("ST32");
2613 } else {
2614 op = &opPool.operation("STW");
2615 }
2616 } else {
2617 if (littleEndian_) {
2618 op = &opPool.operation("ST64");
2619 } else {
2620 op = &opPool.operation("STD");
2621 std::cerr << "Warning: SIMD support with "
2622 << "big-endian adf is deprecated" << std::endl;
2623 }
2624 }
2625
2626 std::vector<ValueType> inputs;
2627 std::vector<ValueType> outputs;
2628
2629 // Address operand 32 or 64 bits.
2630 inputs.push_back(ValueType(defaultType));
2631 inputs.push_back(dataOpndVt);
2632 // There is no output operands for store.
2633
2634 writeOperationDefUsingGivenOperandTypes(
2635 o, *op, false, inputs, outputs, dataOpndVtStr);
2636
2637 }
2638 }
2639
2640 memDataOpndWidth *= 2;
2641 }
2642}
TDGen::hasRegisterClassSupport
bool hasRegisterClassSupport(const Operation &op) const
Definition TDGen.cc:1805
TDGen::writeOperationDefUsingGivenOperandTypes
void writeOperationDefUsingGivenOperandTypes(std::ostream &o, Operation &op, bool skipPattern, std::vector< TDGenerator::ValueType > inputs, std::vector< TDGenerator::ValueType > outputs, TCEString instrSuffix="")
Definition TDGen.cc:1896
TDGenerator::ValueType::vectorTypesOfWidth
static std::vector< ValueType > vectorTypesOfWidth(int width, bool onlyInts=false)
Definition TDGen.cc:8941

References TTAMachine::Machine::hasOperation(), hasRegisterClassSupport(), NullOperation::instance(), TTAMachine::Machine::is64bit(), littleEndian_, mach_, MAX_SCALAR_WIDTH, Operation::name(), Operation::numberOfInputs(), Operation::numberOfOutputs(), OperationPool::operation(), Operation::output(), TDGenerator::ValueType::valueTypeStr(), TDGenerator::ValueType::vectorTypesOfWidth(), Operand::width(), and writeOperationDefUsingGivenOperandTypes().

Referenced by writeInstrInfo().

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◆ writeScalarToVectorDefs()

void TDGen::writeScalarToVectorDefs ( std::ostream &  o) const
protected

Writes scalar_to_vector patterns for vector value types.

Todo:
Add i8 and i16 subword support once those types have RegisterClass support. For now, just skip generation for them.

Definition at line 2388 of file TDGen.cc.

2388 {
2389 o << endl << "// Scalar to vector definitions." << endl;
2390 std::map<TCEString, TCEString>::const_iterator it;
2391 for (it = vbcastOperations_.begin(); it != vbcastOperations_.end();
2392 ++it) {
2393 const TCEString& vtStr = it->first;
2394 const TCEString& vbcastInstr = it->second;
2395
2396 ValueType scalarVt(vtStr);
2397 scalarVt.subwCount_ = 1; // Change vector type to scalar.
2398 TCEString scalarVtStr = scalarVt.valueTypeStr();
2399
2400 /// @todo Add i8 and i16 subword support once those types have
2401 /// RegisterClass support. For now, just skip generation for them.
2402 if (scalarVtStr == "f16" || scalarVtStr == "f32" ||
2403 scalarVtStr == "i32") {
2404 TCEString originalPattern =
2405 vtStr + " (scalar_to_vector " + scalarVtStr + ":$in)";
2406 TCEString replacerPattern =
2407 vbcastInstr + " " + scalarVtStr + ":$in";
2408
2409 writePatternReplacement(o, originalPattern, replacerPattern);
2410 }
2411 }
2412}
TDGen::vbcastOperations_
std::map< TCEString, TCEString > vbcastOperations_
Contains machine's VBCAST instructions (<ValueType, InstrName>).
Definition TDGen.hh:549
TDGen::writePatternReplacement
void writePatternReplacement(std::ostream &o, const TCEString &origPat, const TCEString &replacerPat) const
Definition TDGen.cc:1875

References TDGenerator::ValueType::subwCount_, TDGenerator::ValueType::valueTypeStr(), vbcastOperations_, and writePatternReplacement().

Referenced by writeInstrInfo().

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◆ writeStartOfRegisterInfo()

void TDGen::writeStartOfRegisterInfo ( std::ostream &  o)
protected

Writes static register info to the beginning of register info .td file.

Parameters
oOutput stream to the file.

Definition at line 594 of file TDGen.cc.

594 {
595 o << "//" << endl;
596 o << "// This file is generated automatically!" << endl;
597 o << "// Do not edit." << endl;
598 o << "//" << endl;
599 o << endl;
600
601 o << "class TCEReg<string n, list<Register> aliases> : "
602 << "Register<n> {"
603 << endl;
604
605 o << " let Namespace = \"TCE\";" << endl;
606 o << " let Aliases = aliases;" << endl;
607 o << "}" << endl;
608 o << "class TCEVectorReg<string n, list<Register> subregs> : "
609 << "RegisterWithSubRegs<n, subregs> {"
610 << endl
611 << " let Namespace = \"TCE\";" << endl
612 << "}\n" << endl;
613}

Referenced by writeRegisterInfo().

◆ writeTopLevelTD()

void TDGen::writeTopLevelTD ( std::ostream &  o)
protected

Writes a top level TCE.td file which includes generated .td definitions.

Parameters
oOutput stream to the file.

Definition at line 4231 of file TDGen.cc.

4231 {
4232 o << "include \"Target.td\"" << std::endl;
4233 o << "include \"TCEItinerary.td\"" << std::endl;
4234 o << "include \"GenRegisterInfo.td\"" << std::endl;
4235 o << "include \"GenTCEInstrFormats.td\"" << std::endl;
4236 o << "include \"TCEInstrInfo.td\"" << std::endl;
4237 o << "include \"GenCallingConv.td\"" << std::endl;
4238 o << "def TCEInstrInfo : InstrInfo { }" << std::endl;
4239 o << "class Proc<string Name, SchedMachineModel Model,";
4240 o << " list<SubtargetFeature> Features>";
4241 o << " : ProcessorModel<Name, Model, Features>;";
4242 o << std::endl;
4243 o << "def : Proc<\"generic\", TCEModelV0,[]>;";
4244 o << std::endl;
4245 o << "def TCE : Target { let InstructionSet = TCEInstrInfo; }"
4246 << std::endl;
4247}

Referenced by initializeBackendContents().

◆ writeVectorAnyextPattern()

void TDGen::writeVectorAnyextPattern ( std::ostream &  o,
Operation &  op,
const TCEString &  loadPatternName,
int  vectorLen 
)
protected

◆ writeVectorBitConversions()

void TDGen::writeVectorBitConversions ( std::ostream &  o) const
protected

Writes bit conversion patterns.

Definition at line 2418 of file TDGen.cc.

2418 {
2419 o << endl << "// Bit conversions between vector types." << endl;
2420
2421 std::map<TCEString, RegisterClass>::const_iterator it1;
2422 for (it1 = vRegClasses_.begin(); it1 != vRegClasses_.end(); ++it1) {
2423 const TCEString& vtStr1 = it1->first;
2424 const RegisterClass& regClass1 = it1->second;
2425
2426 std::map<TCEString, RegisterClass>::const_iterator it2;
2427 for (it2 = vRegClasses_.begin(); it2 != vRegClasses_.end(); ++it2) {
2428 const TCEString& vtStr2 = it2->first;
2429 const RegisterClass& regClass2 = it2->second;
2430 if (regClass1.valueType().width() !=
2431 regClass2.valueType().width() ||
2432 vtStr1 == vtStr2) {
2433 continue;
2434 }
2435 const TCEString originalPattern = vtStr2 + " (bitconvert (" +
2436 vtStr1 + " " +
2437 regClass1.name() + ":$src))";
2438 const TCEString replacerPattern =
2439 vtStr2 + " " + regClass2.name() + ":$src";
2440 writePatternReplacement(o, originalPattern, replacerPattern);
2441 }
2442 }
2443
2444 o << endl << "// Bit conversions to/from i32." << endl;
2445
2446 // Write i32 -> same size vector type bit conversions.
2447 std::map<TCEString, RegisterClass>::const_iterator it;
2448 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
2449 const TCEString& vtStr = it->first;
2450 const RegisterClass& regClass = it->second;
2451
2452 if (regClass.valueType().width() == 32 && vtStr != "i32") {
2453 TCEString originalPattern = "i32 (bitconvert (" + vtStr + " " +
2454 regClass.name() + ":$src))";
2455 TCEString replacerPattern = "i32 R32IRegs:$src";
2456 writePatternReplacement(o, originalPattern, replacerPattern);
2457
2458 originalPattern = vtStr + " (bitconvert (i32 R32IRegs:$src))";
2459 replacerPattern = vtStr + " " + regClass.name() + ":$src";
2460 writePatternReplacement(o, originalPattern, replacerPattern);
2461 }
2462 }
2463}

References TDGenerator::RegisterClass::name(), TDGenerator::RegisterClass::valueType(), vRegClasses_, TDGenerator::ValueType::width(), and writePatternReplacement().

Referenced by writeInstrInfo().

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◆ writeVectorBitwiseOperationDefs()

void TDGen::writeVectorBitwiseOperationDefs ( std::ostream &  o,
Operation &  op,
bool  skipPattern 
)
protected

Writes bitwise NOT/AND/IOR/XOR operation definitions for vector operations.

For 32-bit or less vector widths, 32-bit base operation is used. For bitwise bool vector operations wider than 32 bits, corresponding bitwise operation is searched from the machine, and used to create operation definitions if it exists.

Parameters
oOutput stream.
opOperation used to create bitwise operations.
skipPatternIf true, operation pattern writing is skipped.

Definition at line 2657 of file TDGen.cc.

2658 {
2659 o << endl;
2660
2661 if (op.numberOfOutputs() == 0) {
2662 assert(false && "Bitwise operation has 0 outputs.");
2663 }
2664
2665 int opWidth = op.output(0).width();
2666 std::vector<ValueType> vts = ValueType::vectorTypesOfWidth(opWidth);
2667
2668 for (size_t i = 0; i < vts.size(); ++i) {
2669 const ValueType& vecVt = vts[i];
2670 const TCEString vecVtStr = vecVt.valueTypeStr();
2671
2672 // Only integer value types are used in bitwise operations.
2673 if (!vecVt.isFloat_ && hasRegisterClassSupport(vecVt)) {
2674 std::vector<ValueType> inputs;
2675 std::vector<ValueType> outputs;
2676
2677 for (int i = 0; i < op.numberOfInputs(); ++i) {
2678 inputs.push_back(vecVt);
2679 }
2680 for (int i = 0; i < op.numberOfOutputs(); ++i) {
2681 outputs.push_back(vecVt);
2682 }
2683
2684 writeOperationDefUsingGivenOperandTypes(
2685 o, op, skipPattern, inputs, outputs, vecVtStr);
2686 }
2687 }
2688
2689 o << endl;
2690}
TDGenerator::ValueType::isFloat_
bool isFloat_
If true, the value type is a floating point type.
Definition TDGen.hh:727

References assert, hasRegisterClassSupport(), TDGenerator::ValueType::isFloat_, Operation::numberOfInputs(), Operation::numberOfOutputs(), Operation::output(), TDGenerator::ValueType::valueTypeStr(), TDGenerator::ValueType::vectorTypesOfWidth(), Operand::width(), and writeOperationDefUsingGivenOperandTypes().

Referenced by writeInstrInfo().

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◆ writeVectorImmediateWriteDefs()

void TDGen::writeVectorImmediateWriteDefs ( std::ostream &  instrInfoTD)
protected

Definition at line 3216 of file TDGen.cc.

3216 {
3217 for (auto it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
3218 const RegisterClass& regClass = it->second;
3219 TCEString regClassName = regClass.name();
3220 ValueType valType = regClass.valueType();
3221 TCEString valTypeName = valType.valueTypeStr();
3222 if (valType.width() <= 32) {
3223 TCEString opName = "MOVI" + valTypeName;
3224 instrInfoTD << "def " << opName << " : InstTCE<(outs "
3225 << regClassName
3226 << ":$dst), (ins i32imm:$val), \"\",[]>;"
3227 << std::endl;
3228
3229 opNames_[opName] = "MOVE";
3230 }
3231 }
3232}

References TDGenerator::RegisterClass::name(), opNames_, TDGenerator::RegisterClass::valueType(), TDGenerator::ValueType::valueTypeStr(), vRegClasses_, and TDGenerator::ValueType::width().

Referenced by writeInstrInfo().

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◆ writeVectorLoadDefs() [1/2]

void TDGen::writeVectorLoadDefs ( std::ostream &  o,
const TCEString &  opName,
const TCEString &  opNameSuffix,
bool  addrImm,
const TCEString &  resultType,
const TCEString &  loadPatternName,
bool  writePredicatedVersions 
)
protected

◆ writeVectorLoadDefs() [2/2]

void TDGen::writeVectorLoadDefs ( std::ostream &  o,
Operation &  op,
const TCEString &  loadPatternName,
int  vectorLen 
)
protected

◆ writeVectorLoadStoreOperationExploitations()

void TDGen::writeVectorLoadStoreOperationExploitations ( std::ostream &  o)
protected

Attaches load and store operations to vector types that don't have them.

Checks first which vector value types don't have load and store operations for memory accessing. After collecting the value types without load/store, the function tries to search existing load/store instructions whose data operand width matches the vector value type that doesn't have a load/store operation. If the function can find matching memory instructions, it creates new memory instructions for the vector value types by exploiting existing matching memory instructions.

Definition at line 2704 of file TDGen.cc.

2705 {
2706
2707 const char* defaultTypeStr = mach_.is64bit() ? "i64" : "i32";
2708
2709 // Value type string of the register class.
2710 std::set<TCEString> withoutLoadOperation;
2711 std::set<TCEString> withoutStoreOperation;
2712
2713 // Collect all vector value types that are without load or store
2714 // operation support for memory accessing.
2715 std::map<TCEString, RegisterClass>::iterator it;
2716 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
2717 const TCEString vtStr = it->first;
2718 const ValueType vt(vtStr);
2719
2720 // 32-bit and smaller vectors are covered by LDQ/LDH/LDW/STQ/STH/STW.
2721 // TODO: shoudl this have 64 also for 32-bit ADFs?
2722 if (vt.width() > maxScalarWidth_) {
2723 if (registerLoads_.find(vtStr) == registerLoads_.end()) {
2724 withoutLoadOperation.insert(vtStr);
2725 }
2726
2727 if (registerStores_.find(vtStr) == registerStores_.end()) {
2728 withoutStoreOperation.insert(vtStr);
2729 }
2730 }
2731 }
2732
2733 o << endl << "// Define memory operations for vector operands without"
2734 << endl << "// load or store operation definition by exploiting"
2735 << endl << "// existing memory operations of proper width." << endl;
2736
2737 OperationPool opPool;
2738
2739 std::set<TCEString>::const_iterator wLoadIt;
2740 for (wLoadIt = withoutLoadOperation.begin();
2741 wLoadIt != withoutLoadOperation.end(); ++wLoadIt) {
2742 const TCEString& dataOpndVtStr = *wLoadIt;
2743 const ValueType vt(dataOpndVtStr);
2744
2745 bool foundExploitable = false;
2746 std::map<TCEString, InstructionInfo>::const_iterator loadIt =
2747 registerLoads_.begin();
2748
2749 // Try to find any machine load instruction that is able to load
2750 // equal amount of bytes from memory as the ValueType is wide.
2751 while (!foundExploitable && loadIt != registerLoads_.end()) {
2752 const ValueType loadInstrVt(loadIt->first);
2753
2754 // If found a match, remove the last two characters of the
2755 // load instruction name to get the OSAL operation name.
2756 if (vt.width() == loadInstrVt.width()) {
2757 foundExploitable = true;
2758 const TCEString opName = (loadIt->second).osalOpName_;
2759 Operation& op = opPool.operation(opName.c_str());
2760
2761 std::vector<ValueType> inputs;
2762 std::vector<ValueType> outputs;
2763
2764 // Address operand always 32 or 64 bits.
2765 inputs.push_back(ValueType(defaultTypeStr));
2766 // Data operand.
2767 outputs.push_back(dataOpndVtStr);
2768
2769 writeOperationDefUsingGivenOperandTypes(
2770 o, op, false, inputs, outputs, dataOpndVtStr);
2771 }
2772
2773 ++loadIt;
2774 }
2775 }
2776
2777 std::set<TCEString>::const_iterator wStoreIt;
2778 for (wStoreIt = withoutStoreOperation.begin();
2779 wStoreIt != withoutStoreOperation.end(); ++wStoreIt) {
2780 const TCEString& dataOpndVtStr = *wStoreIt;
2781 const ValueType vt(dataOpndVtStr);
2782
2783 bool foundExploitable = false;
2784 std::map<TCEString, InstructionInfo>::const_iterator storeIt =
2785 registerStores_.begin();
2786
2787 // Try to find any machine store instruction that is able to store
2788 // equal amount of bytes to memory as the ValueType is wide.
2789 while (!foundExploitable && storeIt != registerStores_.end()) {
2790 const ValueType storeInstrVt(storeIt->first);
2791
2792 // If found a match, remove the last two characters of the
2793 // store instruction name to get the OSAL operation name.
2794 if (vt.width() == storeInstrVt.width()) {
2795 foundExploitable = true;
2796 const TCEString opName = (storeIt->second).osalOpName_;
2797 Operation& op = opPool.operation(opName.c_str());
2798
2799 std::vector<ValueType> inputs;
2800 std::vector<ValueType> outputs;
2801
2802 // Address operand always i32 or 64 bits.
2803 inputs.push_back(ValueType(defaultTypeStr));
2804 inputs.push_back(dataOpndVtStr);
2805 // There is no output operands for store.
2806
2807 writeOperationDefUsingGivenOperandTypes(
2808 o, op, false, inputs, outputs, dataOpndVtStr);
2809 }
2810
2811 ++storeIt;
2812 }
2813 }
2814
2815 o << endl;
2816}

References TTAMachine::Machine::is64bit(), mach_, maxScalarWidth_, OperationPool::operation(), registerLoads_, registerStores_, vRegClasses_, TDGenerator::ValueType::width(), and writeOperationDefUsingGivenOperandTypes().

Referenced by writeInstrInfo().

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◆ writeVectorMemoryOperationDefs()

void TDGen::writeVectorMemoryOperationDefs ( std::ostream &  o,
Operation &  op,
bool  skipPattern 
)
protected

Writes instruction definitions for memory vector operations.

Subword aligned LDQ/LDH/LDW/STQ/STH/STQ vector operations can be passed directly to writing vector operation definitions, but vector aligned LOAD and STORE operations can be used for several different vector types of the same width, thus, all the different vector types need to be covered and separate memory instruction have to be made for them.

Definition at line 2261 of file TDGen.cc.

2262 {
2263 abortWithError("WiP");
2264}

References abortWithError.

Referenced by writeInstrInfo().

◆ writeVectorOperationDef()

void TDGen::writeVectorOperationDef ( std::ostream &  o,
Operation &  op,
TCEString  valueTypes,
const TCEString &  attributes,
bool  skipPattern 
)
protected

Writes instruction of the vector operation to the .td file.

Creates register version and possibly an immediate version of the vector operation in case there are any scalar operands.

Parameters
oOutput stream to the file.
opOperation to be written as an instruction to the .td file.
valueTypesOperand value type identifier characters.
attributesOperation attributes.
skipPatternTrue, if skip pattern creation.

Definition at line 2181 of file TDGen.cc.

2183 {
2184 // Make sure operation's operands are fully supported by
2185 // vector register classes.
2186 if (!hasRegisterClassSupport(op)) {
2187 verbose(
2188 "Warning: " + op.name() + valueTypes +
2189 " was not created due to unsupported operands.");
2190 return;
2191 }
2192
2193 // Write register version of the operation.
2194 TDGen::writeOperationDef(o, op, valueTypes, attributes, skipPattern);
2195
2196 // Information of some operations is needed later, save it if needed.
2197 saveAdditionalVectorOperationInfo(op, valueTypes, true);
2198
2199 // Create the same instruction with immediate inputs if there are
2200 // any input operands that are scalars.
2201 bool scalarsFound = false;
2202 for (int i = op.numberOfOutputs(); i < op.operandCount(); ++i) {
2203 char& c = valueTypes[i];
2204 switch (c) {
2205 case OT_REG_BOOL:
2206 c = OT_IMM_BOOL;
2207 scalarsFound = true;
2208 break;
2209 case OT_REG_INT:
2210 c = OT_IMM_INT;
2211 scalarsFound = true;
2212 break;
2213 case OT_REG_FP:
2214 c = OT_IMM_FP;
2215 scalarsFound = true;
2216 break;
2217 case OT_REG_HFP:
2218 c = OT_IMM_HFP;
2219 scalarsFound = true;
2220 break;
2221 default:
2222 continue;
2223 }
2224 }
2225
2226 if (scalarsFound) {
2227 // Write immediate version of the operation.
2228 TDGen::writeOperationDef(o, op, valueTypes, attributes, skipPattern);
2229
2230 // Information of some immediate versions are needed also.
2231 saveAdditionalVectorOperationInfo(op, valueTypes, false);
2232 }
2233}
TDGen::saveAdditionalVectorOperationInfo
void saveAdditionalVectorOperationInfo(const Operation &op, const TCEString &valueTypes, bool isRegisterOp)
Definition TDGen.cc:2246

References hasRegisterClassSupport(), Operation::name(), Operation::numberOfOutputs(), Operation::operandCount(), OT_IMM_BOOL, OT_IMM_FP, OT_IMM_HFP, OT_IMM_INT, OT_REG_BOOL, OT_REG_FP, OT_REG_HFP, OT_REG_INT, saveAdditionalVectorOperationInfo(), verbose(), and writeOperationDef().

Referenced by writeOperationDefUsingGivenOperandTypes().

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◆ writeVectorOperationDefs()

void TDGen::writeVectorOperationDefs ( std::ostream &  o,
Operation &  op,
bool  skipPattern 
)
protected

Writes needed defitinion(s) of the vector operation to the .td file.

Creates 4 differend instructions of the operation at most:

  • Integer version (register)
  • Integer version (immediate)
  • Float/half float version (register)
  • Float/half float version (immediate)
Parameters
oOutput stream to the .td file.
opVector operation of which the definitions will be created.
skipPatternTrue, if skip pattern creation.

Definition at line 2164 of file TDGen.cc.

2164 {
2165 abortWithError("WiP");
2166}

References abortWithError.

Referenced by writeInstrInfo().

◆ writeVectorRegisterBaseClasses()

void TDGen::writeVectorRegisterBaseClasses ( std::ostream &  o) const
protected

Writes base class definitions to the .td file.

Definition at line 2047 of file TDGen.cc.

2047 {
2048 o << endl
2049 << "// #################################" << endl
2050 << "// Vector register base class definitions" << endl;
2051
2052 std::map<int, TCEString>::const_iterator bcIt;
2053 for (bcIt = baseClasses_.begin(); bcIt != baseClasses_.end(); ++bcIt) {
2054 int width = bcIt->first;
2055
2056 if (width > MAX_SCALAR_WIDTH) {
2057 TCEString baseClassName = bcIt->second;
2058 o << "class " << baseClassName
2059 << "<string n, list<Register> aliases> : "
2060 << "TCEVectorReg<n, aliases> {}" << endl;
2061 }
2062 }
2063 o << "// #################################" << endl;
2064}

References baseClasses_, and MAX_SCALAR_WIDTH.

Referenced by writeRegisterInfo().

◆ writeVectorRegisterClasses()

void TDGen::writeVectorRegisterClasses ( std::ostream &  o) const
protected

Writes register class definitions to the .td file.

Definition at line 2102 of file TDGen.cc.

2102 {
2103 o << endl
2104 << "// #################################" << endl
2105 << "// Register class definitions for vector registers" << endl;
2106
2107 std::map<TCEString, RegisterClass>::const_iterator it;
2108 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
2109 const TCEString& vtStr = it->first;
2110 const RegisterClass& regClass = it->second;
2111
2112 if (regClass.numberOfRegisters() == 0) {
2113 std::string msg =
2114 std::string("The machine is missing registers for ") +
2115 regClass.valueType().valueTypeStr() + " operands" +
2116 " required by some operation(s).";
2117
2118 std::cerr << "Error: Illegal machine: " << msg << std::endl;
2119 THROW_EXCEPTION(IllegalMachine, msg);
2120 }
2121
2122 o << "def " << regClass.name() << " : "
2123 << "RegisterClass<\"TCE\", "
2124 << "[" << vtStr << "], " << regClass.alignment() << ", (add ";
2125
2126 // Add registers to the register class.
2127 for (size_t i = 0; i < regClass.numberOfRegisters(); ++i) {
2128 const RegisterInfo& reg = regClass.registerInfo(i);
2129 o << reg.regName_;
2130
2131 if (i != regClass.numberOfRegisters() - 1) {
2132 o << ", ";
2133 }
2134 }
2135 o << ")> ";
2136
2137 // Register classes below 8 bit of total width need to be set as
2138 // "8 bit of size" so that when they are spilled to stack, the
2139 // byte size of the register class is at least 1.
2140 if (regClass.valueType().width() < 8) {
2141 o << "{" << endl << " let Size=8;" << endl << "}" << endl;
2142 } else {
2143 o << ";" << endl;
2144 }
2145 }
2146
2147 o << "// #################################" << endl;
2148}

References TDGenerator::RegisterClass::alignment(), TDGenerator::RegisterClass::name(), TDGenerator::RegisterClass::numberOfRegisters(), TDGenerator::RegisterClass::registerInfo(), TDGenerator::RegisterInfo::regName_, THROW_EXCEPTION, TDGenerator::RegisterClass::valueType(), TDGenerator::ValueType::valueTypeStr(), vRegClasses_, and TDGenerator::ValueType::width().

Referenced by writeRegisterInfo().

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◆ writeVectorRegisterMoveDefs()

void TDGen::writeVectorRegisterMoveDefs ( std::ostream &  o)
protected

Writes MOV instructions between vector register classes.

Definition at line 2270 of file TDGen.cc.

2270 {
2271 o << endl
2272 << "// Vector register->register move definitions." << endl
2273 << "let isAsCheapAsAMove = 1 in {" << endl;
2274
2275 std::map<TCEString, RegisterClass>::const_iterator it;
2276 for (it = vRegClasses_.begin(); it != vRegClasses_.end(); ++it) {
2277 const RegisterClass& regClass = it->second;
2278
2279 const TCEString opcode = "MOV" + regClass.name();
2280 const TCEString vtStr = regClass.valueType().valueTypeStr();
2281
2282 const TCEString outs = "(outs " + regClass.name() + ":$dst), ";
2283 const TCEString ins = "(ins " + regClass.name() + ":$src), ";
2284 const TCEString insPred =
2285 "(ins GuardRegs:$pred, " + regClass.name() + ":$src), ";
2286 const TCEString asmOp = "\"$src -> $dst;\", []";
2287
2288 o << "def " << opcode << " : "
2289 << "InstTCE<" << outs << ins << asmOp << ">;" << endl;
2290
2291 opNames_[opcode] = opcode;
2292 movOperations_.insert(opcode);
2293
2294 if (hasConditionalMoves_) {
2295 o << "def PRED_TRUE_" << opcode << " : "
2296 << "InstTCE<" << outs << insPred << asmOp << ">;" << endl;
2297
2298 o << "def PRED_FALSE_" << opcode << " : "
2299 << "InstTCE<" << outs << insPred << asmOp << ">;" << endl;
2300
2301 opNames_["PRED_TRUE_" + opcode] = "?" + opcode;
2302 opNames_["PRED_FALSE_" + opcode] = "!" + opcode;
2303 truePredOps_[opcode] = "PRED_TRUE_" + opcode;
2304 falsePredOps_[opcode] = "PRED_TRUE_" + opcode;
2305
2306 movOperations_.insert("PRED_TRUE_" + opcode);
2307 movOperations_.insert("PRED_FALSE_" + opcode);
2308 }
2309 }
2310
2311 o << "}" << endl;
2312}
TDGen::movOperations_
std::set< TCEString > movOperations_
Contains all moves between register classes (<InstrName>).
Definition TDGen.hh:586

References falsePredOps_, hasConditionalMoves_, movOperations_, TDGenerator::RegisterClass::name(), opNames_, truePredOps_, TDGenerator::RegisterClass::valueType(), TDGenerator::ValueType::valueTypeStr(), and vRegClasses_.

Referenced by writeInstrInfo().

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◆ writeVectorRegisterNames()

void TDGen::writeVectorRegisterNames ( std::ostream &  o)
protected

Writes register definitions to the .td file.

Definition at line 2070 of file TDGen.cc.

2070 {
2071 o << endl
2072 << "// #################################" << endl
2073 << "// Register name definitions for vector registers" << endl;
2074
2075 std::set<TCEString> declaredRegNames;
2076
2077 std::map<int, std::vector<RegisterInfo>>::const_iterator it;
2078 for (it = registers_.begin(); it != registers_.end(); ++it) {
2079 int regsWidth = it->first;
2080
2081 const std::vector<RegisterInfo>& regs = it->second;
2082 TCEString baseClass = baseClasses_.find(regsWidth)->second;
2083
2084 for (size_t i = 0; i < regs.size(); ++i) {
2085 // Don't declare <=32b registers again, it has been done in TDGen.
2086 if (regsWidth > MAX_SCALAR_WIDTH) {
2087 RegisterInfo reg = regs[i];
2088 RegInfo oldRegInfo = {reg.regFileName_, reg.regIndex_};
2089 writeRegisterDef(
2090 o, oldRegInfo, reg.regName_, baseClass, "", RESERVED);
2091 declaredRegNames.insert(reg.regName_);
2092 }
2093 }
2094 }
2095 o << "// #################################" << endl;
2096}
TDGenerator::RegisterInfo::regFileName_
TCEString regFileName_
Name of the register file the register belongs to, e.g. "RF".
Definition TDGen.hh:671

References baseClasses_, MAX_SCALAR_WIDTH, TDGenerator::RegisterInfo::regFileName_, TDGenerator::RegisterInfo::regIndex_, registers_, TDGenerator::RegisterInfo::regName_, RESERVED, and writeRegisterDef().

Referenced by writeRegisterInfo().

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◆ writeVectorStoreDefs() [1/2]

void TDGen::writeVectorStoreDefs ( std::ostream &  o,
const TCEString &  opName,
const TCEString &  opNameSuffix,
bool  addrImm,
const TCEString &  dataType,
bool  writePredicatedVersions 
)
protected

◆ writeVectorStoreDefs() [2/2]

void TDGen::writeVectorStoreDefs ( std::ostream &  o,
Operation &  op,
int  vectorLen 
)
protected

◆ writeVectorTruncStoreDefs() [1/2]

void TDGen::writeVectorTruncStoreDefs ( std::ostream &  o) const
protected

Writes truncstore patterns for vector value types.

Definition at line 2318 of file TDGen.cc.

2318 {
2319 o << endl << "// Vector truncstore definitions, needed below." << endl;
2320
2321 // Create truncstore definitions for vector value types, there has to
2322 // exist store operations for the same value type that the TRUNC
2323 // operation has. For example, in order to create truncstore using
2324 // TRUNCWH16X4, there has to be store operations in the machine that
2325 // supports storing v4i16 value type.
2326
2327 std::map<TCEString, RegisterClass>::const_iterator rcIt;
2328 for (rcIt = vRegClasses_.begin(); rcIt != vRegClasses_.end(); ++rcIt) {
2329 o << "def truncstore" << rcIt->first << " : "
2330 << "PatFrag<(ops node:$val, node:$ptr),"
2331 << "(truncstore node:$val, node:$ptr), "
2332 << "[{return cast<StoreSDNode>(N)->getMemoryVT() == "
2333 << "MVT::" << rcIt->first << ";}]>;" << endl;
2334 }
2335 // Create patterns which will replace "truncstore" pattern with separate
2336 // TRUNC and then STORE operations.
2337
2338 o << endl << "// Pattern definitions for truncstores." << endl;
2339 std::vector<std::pair<const Operation*, TCEString>>::const_iterator it;
2340 for (it = truncOperations_.begin(); it != truncOperations_.end(); ++it) {
2341 const TCEString& truncInstr = it->second;
2342 const TCEString& vtFromStr =
2343 ValueType::valueTypeStr(it->first->input(0));
2344 const TCEString targetVtStr =
2345 ValueType::valueTypeStr(it->first->output(0));
2346
2347 std::map<TCEString, InstructionInfo>::const_iterator regStoreIt =
2348 registerStores_.find(targetVtStr);
2349
2350 // Use register version of store operations.
2351 if (regStoreIt != registerStores_.end()) {
2352 const TCEString& regStoreInstr = (regStoreIt->second).instrName_;
2353 const TCEString originalPattern = "truncstore" + targetVtStr +
2354 " " + vtFromStr +
2355 ":$op2, ADDRrr:$op1";
2356 const RegisterClass& regClass =
2357 vRegClasses_.find(vtFromStr)->second;
2358 const TCEString replacerPattern =
2359 regStoreInstr + " ADDRrr:$op1, (" + truncInstr + " " +
2360 regClass.name() + ":$op2)";
2361
2362 writePatternReplacement(o, originalPattern, replacerPattern);
2363 }
2364
2365 std::map<TCEString, InstructionInfo>::const_iterator immStoreIt =
2366 immediateStores_.find(targetVtStr);
2367
2368 // Use immediate version of store operations.
2369 if (immStoreIt != immediateStores_.end()) {
2370 const TCEString& immStoreInstr = (immStoreIt->second).instrName_;
2371 const TCEString originalPattern = "truncstore" + targetVtStr +
2372 " " + vtFromStr +
2373 ":$op2, ADDRri:$op1";
2374 const RegisterClass& regClass =
2375 vRegClasses_.find(vtFromStr)->second;
2376 const TCEString replacerPattern =
2377 immStoreInstr + " ADDRri:$op1, (" + truncInstr + " " +
2378 regClass.name() + ":$op2)";
2379 writePatternReplacement(o, originalPattern, replacerPattern);
2380 }
2381 }
2382}
TDGen::truncOperations_
std::vector< std::pair< const Operation *, TCEString > > truncOperations_
Contains machine's TRUNCxx/CFH instructions (<ValueType, InstrName>).
Definition TDGen.hh:551
TDGen::immediateStores_
std::map< TCEString, TDGenerator::InstructionInfo > immediateStores_
All immediate store operations (<ValueType, InstrInfo>).
Definition TDGen.hh:542

References immediateStores_, TDGenerator::RegisterClass::name(), registerStores_, truncOperations_, TDGenerator::ValueType::valueTypeStr(), vRegClasses_, and writePatternReplacement().

Referenced by writeInstrInfo().

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◆ writeVectorTruncStoreDefs() [2/2]

void TDGen::writeVectorTruncStoreDefs ( std::ostream &  o,
Operation &  op,
int  bitsize,
int  vectorLen 
)
protected

◆ writeWiderVectorOperationExploitations()

void TDGen::writeWiderVectorOperationExploitations ( std::ostream &  o)
protected

Writes vector operation definitions that exploit bigger vector operations.

Exploited vector operands are written in ascending order by their subword count, meaning that e.g. ADD32X16, ADD32X32, and ADD32X4 operation exploitations are listed so that ADD32X4 are written first, then ADD32X16, and then ADD32X32. This way the instruction selection will first use ADD32X4 to execute vector addition for v2i32 vector operand types, and thus, is more optimal solution than executing the same v2i32 addition with ADD32X16 (though ADD32X4 would be also available in the machine).

Definition at line 2831 of file TDGen.cc.

2831 {
2832 abortWithError("WiP");
2833}

References abortWithError.

Member Data Documentation

◆ addOperations_

std::map<TCEString, TCEString> TDGen::addOperations_
protected

Contains machine's add instructions (<ValueType, InstrName>).

Definition at line 579 of file TDGen.hh.

Referenced by genGeneratedTCEPlugin_getAddOpcode().

◆ addressingModeDefs_

std::string TDGen::addressingModeDefs_
protected

Definition at line 470 of file TDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ allOpNames_

OperationDAGSelector::OperationSet TDGen::allOpNames_
protected

Contains all operation names in upper case.

Definition at line 520 of file TDGen.hh.

Referenced by analyzeMachineVectorRegisterClasses(), gatherAllMachineOperations(), and writeInstrInfo().

◆ andSameOperations_

std::map<TCEString, TCEString> TDGen::andSameOperations_
protected

Contains machine's ANDSAME instructions (<ValueType, InstrName>).

Definition at line 571 of file TDGen.hh.

◆ argRegCount_

unsigned int TDGen::argRegCount_
protected

Definition at line 628 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), createParamDRegNums(), TDGen(), write32bitRegisterInfo(), write64bitRegisterInfo(), writeArgRegsArray(), and writeCallingConv().

◆ argRegNames_

std::vector<std::string> TDGen::argRegNames_
protected

Definition at line 605 of file TDGen.hh.

Referenced by writeCallDef(), writeCallDefRegs(), and writeRegisterDef().

◆ argRegsArray_

std::string TDGen::argRegsArray_
protected

Definition at line 475 of file TDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ backendCode_

std::string TDGen::backendCode_
protected

Definition at line 476 of file TDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ baseClasses_

std::map<int, TCEString> TDGen::baseClasses_
protected

Contains vector base classes for register files (<Width, Name>).

Definition at line 529 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), writeCallDefRegs(), writeVectorRegisterBaseClasses(), and writeVectorRegisterNames().

◆ BOOL_SUBW_WIDTH

const int TDGen::BOOL_SUBW_WIDTH
staticprotected
Initial value:
=
Operand::defaultElementWidth(Operand::BOOL)
Operand::defaultElementWidth
static int defaultElementWidth(OperandType type)
Definition Operand.cc:557

Bool type subword width.

Definition at line 484 of file TDGen.hh.

◆ callingConv_

std::string TDGen::callingConv_
protected

Definition at line 474 of file TDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ constantMaterializationPredicates_

std::vector<std::string> TDGen::constantMaterializationPredicates_
protected

All predicates used in constant materialization patterns.

Definition at line 649 of file TDGen.hh.

Referenced by createConstantMaterializationPatterns(), and createConstantMaterializationQuery().

◆ dregNum_

unsigned TDGen::dregNum_
protected

Definition at line 468 of file TDGen.hh.

Referenced by write32bitRegisterInfo(), write64bitRegisterInfo(), writeRARegisterInfo(), and writeRegisterDef().

◆ EXPLOIT_BIGGER_REGISTERS

const bool TDGen::EXPLOIT_BIGGER_REGISTERS = true
staticprotected

If set to true, smaller vector value types can be stored to larger register files, e.g. v4i8 vectors can be stored to registers that are over 32 bits in size.

Definition at line 493 of file TDGen.hh.

Referenced by associateRegistersWithVectorRegisterClasses().

◆ extractElemOperations_

std::map<TCEString, TCEString> TDGen::extractElemOperations_
protected

Contains machine's EXTRACTELEM instructions (<ValueType, InstrName>).

Definition at line 563 of file TDGen.hh.

◆ falsePredOps_

std::map<std::string, std::string> TDGen::falsePredOps_
protected

Definition at line 612 of file TDGen.hh.

Referenced by writeBackendCode(), writeInstrInfo(), writeOperationDef(), and writeVectorRegisterMoveDefs().

◆ FP_SUBW_WIDTH

const int TDGen::FP_SUBW_WIDTH
staticprotected
Initial value:
=
Operand::defaultElementWidth(Operand::FLOAT_WORD)

Float type subword width.

Definition at line 480 of file TDGen.hh.

Referenced by analyzeMachineVectorRegisterClasses().

◆ gatherOperations_

std::map<TCEString, TCEString> TDGen::gatherOperations_
protected

Contains machine's GATHER instructions (<ValueType, InstrName>).

Definition at line 577 of file TDGen.hh.

Referenced by genGeneratedTCEPlugin_getGatherOpcode().

◆ gprRegNames_

std::vector<std::string> TDGen::gprRegNames_
protected

Definition at line 607 of file TDGen.hh.

Referenced by writeCallDefRegs(), and writeRegisterDef().

◆ guardedRegs_

std::set<RegInfo> TDGen::guardedRegs_
protected

List of register that are associated with a guard on a bus.

Definition at line 636 of file TDGen.hh.

Referenced by analyzeRegisters(), and writeRegisterDef().

◆ guardRegTemplateName

const std::string TDGen::guardRegTemplateName = "Guard"
staticprotected

Definition at line 651 of file TDGen.hh.

Referenced by genGeneratedTCEPlugin_getLoad(), genGeneratedTCEPlugin_getStore(), writeGuardRegisterClassInfo(), and writeRegisterDef().

◆ hasConditionalMoves_

bool TDGen::hasConditionalMoves_
protected

Definition at line 623 of file TDGen.hh.

Referenced by canBePredicated(), createSelectPatterns(), TDGen(), writeInstrInfo(), writeOperationDefs(), and writeVectorRegisterMoveDefs().

◆ hasExBoolRegs_

bool TDGen::hasExBoolRegs_
protected

Definition at line 619 of file TDGen.hh.

◆ hasExIntRegs_

bool TDGen::hasExIntRegs_
protected

Definition at line 620 of file TDGen.hh.

◆ hasSelect_

bool TDGen::hasSelect_
protected

Definition at line 621 of file TDGen.hh.

Referenced by createSelectPatterns(), and writeOperationDefs().

◆ HFP_SUBW_WIDTH

const int TDGen::HFP_SUBW_WIDTH
staticprotected
Initial value:
=
Operand::defaultElementWidth(Operand::HALF_FLOAT_WORD)

Half float type subword width.

Definition at line 482 of file TDGen.hh.

Referenced by analyzeMachineVectorRegisterClasses().

◆ highestLaneBool_

int TDGen::highestLaneBool_
protected

Definition at line 617 of file TDGen.hh.

◆ highestLaneInt_

int TDGen::highestLaneInt_
protected

Definition at line 616 of file TDGen.hh.

◆ immediateLoads_

std::map<TCEString, TDGenerator::InstructionInfo> TDGen::immediateLoads_
protected

All immediate load operations (<ValueType, InstrInfo>).

Definition at line 544 of file TDGen.hh.

◆ immediateStores_

std::map<TCEString, TDGenerator::InstructionInfo> TDGen::immediateStores_
protected

All immediate store operations (<ValueType, InstrInfo>).

Definition at line 542 of file TDGen.hh.

Referenced by writeVectorTruncStoreDefs().

◆ immInfo_

ImmInfo* TDGen::immInfo_
protected

Definition at line 465 of file TDGen.hh.

Referenced by areImmediateOperandsLegal(), createConstantMaterializationPatterns(), getLLVMPatternWithConstants(), TDGen(), writeInstrInfo(), writeOperandDefs(), and ~TDGen().

◆ immOperandDefs_

std::map<ImmInfoKey, std::string> TDGen::immOperandDefs_
protected

Maps (operation, operand) pairs to i32 immediate operand definition names.

Definition at line 436 of file TDGen.hh.

Referenced by dagNodeToString(), immediateOperandNameForEmulatedOperation(), patInputs(), and writeIntegerImmediateDefs().

◆ instrFormats_

std::string TDGen::instrFormats_
protected

Definition at line 473 of file TDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ instrInfo_

std::string TDGen::instrInfo_
protected

Definition at line 472 of file TDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ iorOperations_

std::map<TCEString, TCEString> TDGen::iorOperations_
protected

Contains machine's shl instructions (<ValueType, InstrName>).

Definition at line 583 of file TDGen.hh.

Referenced by genGeneratedTCEPlugin_getIorOpcode().

◆ iorSameOperations_

std::map<TCEString, TCEString> TDGen::iorSameOperations_
protected

Contains machine's IORSAME instructions (<ValueType, InstrName>).

Definition at line 573 of file TDGen.hh.

◆ littleEndian_

bool TDGen::littleEndian_
protected

Definition at line 627 of file TDGen.hh.

Referenced by createBoolAndHalfLoadPatterns(), createByteExtLoadPatterns(), createEndiannesQuery(), createShortExtLoadPatterns(), genGeneratedTCEPlugin_getLoad(), genGeneratedTCEPlugin_getStore(), llvmOperationName(), llvmOperationPattern(), writeBackendCode(), writeBooleanStorePatterns(), writeInstrInfo(), and writeScalarOperationExploitations().

◆ llvmGuardRegs_

std::vector<std::string> TDGen::llvmGuardRegs_
protected

The LLVM register defs used as guards.

Definition at line 599 of file TDGen.hh.

Referenced by writeGuardRegisterClassInfo(), and writeRegisterDef().

◆ mach_

const TTAMachine::Machine& TDGen::mach_
protected

Definition at line 463 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), analyzeRegisters(), checkRequiredRegisters(), constantNodeString(), create32BitExtLoadPatterns(), createBoolAndHalfLoadPatterns(), createBranchAnalysis(), createByteExtLoadPatterns(), createConstShiftPatterns(), createEndiannesQuery(), createGetMaxMemoryAlignment(), createMinMaxGenerator(), createSelectPatterns(), createShortExtLoadPatterns(), emulatingOpNodeLLVMName(), gatherAllMachineOperations(), genGeneratedTCEPlugin_getLoad(), genGeneratedTCEPlugin_getStore(), genTCEInstrInfo_copyPhys64bitReg(), llvmOperationName(), llvmOperationPattern(), operandChar(), operandToString(), operationCanBeMatched(), TDGen(), write1bitRegisterInfo(), write32bitRegisterInfo(), write64bitRegisterInfo(), writeAddressingModeDefs(), writeBackendCode(), writeCallingConv(), writeCallSeqStart(), writeCondBranchDefs(), writeConstShiftPat(), writeEmulationPattern(), writeGetPointerAdjustmentQuery(), writeGuardRegisterClassInfo(), writeHWLoopDef(), writeInstrInfo(), writeIntegerImmediateDefs(), writeMiscPatterns(), writeMoveImmediateDefs(), writeOperationDef(), writeOperationDefs(), RISCVTDGen::writePatternDefinition(), writePortGuardedJumpDefPair(), writeRARegisterInfo(), writeScalarOperationExploitations(), and writeVectorLoadStoreOperationExploitations().

◆ MAX_SCALAR_WIDTH

const int TDGen::MAX_SCALAR_WIDTH = 64
staticprotected

Distincts wide vs scalar registers.

Definition at line 486 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), writeScalarOperationExploitations(), writeVectorRegisterBaseClasses(), and writeVectorRegisterNames().

◆ MAX_SUBW_COUNT

const int TDGen::MAX_SUBW_COUNT = SIMD_WORD_WIDTH / BYTE_BITWIDTH
staticprotected

Maximum number of subwords that any SIMD operation can have.

Definition at line 488 of file TDGen.hh.

Referenced by genTCETargetLoweringSIMD_getSetCCResultVT().

◆ maxScalarWidth_

int TDGen::maxScalarWidth_
protected

Definition at line 625 of file TDGen.hh.

Referenced by createVectorRVDRegNums(), genTCERegisterInfo_setReservedVectorRegs(), TDGen(), writeCallDefRegs(), and writeVectorLoadStoreOperationExploitations().

◆ maxVectorSize_

int TDGen::maxVectorSize_
protected

Definition at line 614 of file TDGen.hh.

Referenced by writeBackendCode().

◆ movOperations_

std::set<TCEString> TDGen::movOperations_
protected

Contains all moves between register classes (<InstrName>).

Definition at line 586 of file TDGen.hh.

Referenced by writeVectorRegisterMoveDefs().

◆ operandDefs_

std::string TDGen::operandDefs_
protected

Definition at line 471 of file TDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ OPERATION_PATTERNS_

const std::map< TCEString, TCEString > TDGen::OPERATION_PATTERNS_
staticprotected

Contains <BaseOpName, OpPattern> key-value pairs.

Definition at line 517 of file TDGen.hh.

◆ opNames_

std::map<std::string, std::string> TDGen::opNames_
protected

Definition at line 609 of file TDGen.hh.

Referenced by createBoolAndHalfLoadPatterns(), createBranchAnalysis(), createConstantMaterializationPatterns(), createMinMaxDef(), createMinMaxGenerator(), createSelectPatterns(), getLLVMPatternWithConstants(), writeBackendCode(), writeBooleanStorePatterns(), writeCondBranchDefs(), writeConstShiftPat(), writeGetPointerAdjustmentQuery(), writeHWLoopDef(), writeInstrInfo(), writeOperationDef(), writePortGuardedJumpDefPair(), writeVectorImmediateWriteDefs(), and writeVectorRegisterMoveDefs().

◆ OT_IMM_BOOL

const char TDGen::OT_IMM_BOOL = 'j'
static

Definition at line 503 of file TDGen.hh.

Referenced by constantNodeString(), dagNodeToString(), getLLVMPatternWithConstants(), getMovePattern(), operandToString(), operandTypeToRegister(), regOperandCharToImmOperandChar(), and writeVectorOperationDef().

◆ OT_IMM_FP

const char TDGen::OT_IMM_FP = 'k'
static

Definition at line 505 of file TDGen.hh.

Referenced by constantNodeString(), getLLVMPatternWithConstants(), getMovePattern(), operandToString(), operandTypeToRegister(), regOperandCharToImmOperandChar(), and writeVectorOperationDef().

◆ OT_IMM_HFP

const char TDGen::OT_IMM_HFP = 'l'
static

Definition at line 506 of file TDGen.hh.

Referenced by getLLVMPatternWithConstants(), getMovePattern(), operandToString(), operandTypeToRegister(), regOperandCharToImmOperandChar(), and writeVectorOperationDef().

◆ OT_IMM_INT

const char TDGen::OT_IMM_INT = 'i'
static

Definition at line 504 of file TDGen.hh.

Referenced by areImmediateOperandsLegal(), canBePredicated(), constantNodeString(), createByteExtLoadPatterns(), createShortExtLoadPatterns(), dagNodeToString(), emulatingOpNodeLLVMName(), getLLVMPatternWithConstants(), getMovePattern(), operandToString(), operandTypeToRegister(), patInputs(), regOperandCharToImmOperandChar(), and writeVectorOperationDef().

◆ OT_IMM_LONG

const char TDGen::OT_IMM_LONG = 'a'
static

Definition at line 507 of file TDGen.hh.

Referenced by constantNodeString(), createByteExtLoadPatterns(), createShortExtLoadPatterns(), emulatingOpNodeLLVMName(), operandToString(), and regOperandCharToImmOperandChar().

◆ OT_REG_BOOL

const char TDGen::OT_REG_BOOL = 'b'
static

Definition at line 497 of file TDGen.hh.

Referenced by constantNodeString(), dagNodeToString(), getMovePattern(), operandChar(), operandToString(), operandTypeToRegister(), regOperandCharToImmOperandChar(), writeOperationDefs(), and writeVectorOperationDef().

◆ OT_REG_DOUBLE

const char TDGen::OT_REG_DOUBLE = 'd'
static

Definition at line 502 of file TDGen.hh.

Referenced by constantNodeString().

◆ OT_REG_FP

const char TDGen::OT_REG_FP = 'f'
static

Definition at line 500 of file TDGen.hh.

Referenced by constantNodeString(), getMovePattern(), operandChar(), operandToString(), operandTypeToRegister(), regOperandCharToImmOperandChar(), TDGenerator::ValueType::valueType(), and writeVectorOperationDef().

◆ OT_REG_HFP

const char TDGen::OT_REG_HFP = 'h'
static

Definition at line 501 of file TDGen.hh.

Referenced by constantNodeString(), getMovePattern(), operandChar(), operandToString(), operandTypeToRegister(), regOperandCharToImmOperandChar(), and writeVectorOperationDef().

◆ OT_REG_INT

const char TDGen::OT_REG_INT = 'r'
static

Definition at line 498 of file TDGen.hh.

Referenced by constantNodeString(), createByteExtLoadPatterns(), createShortExtLoadPatterns(), getMovePattern(), operandChar(), operandToString(), operandTypeToRegister(), operationCanBeMatched(), regOperandCharToImmOperandChar(), writeEmulationPattern(), writeOperationDef(), RISCVTDGen::writePatternDefinition(), and writeVectorOperationDef().

◆ OT_REG_LONG

const char TDGen::OT_REG_LONG = 's'
static

Definition at line 499 of file TDGen.hh.

Referenced by constantNodeString(), createByteExtLoadPatterns(), createShortExtLoadPatterns(), operandChar(), operandToString(), operationCanBeMatched(), regOperandCharToImmOperandChar(), writeEmulationPattern(), writeOperationDef(), and RISCVTDGen::writePatternDefinition().

◆ OT_VREG_BOOL

const char TDGen::OT_VREG_BOOL = 'a'
static

Definition at line 508 of file TDGen.hh.

Referenced by operandChar(), and operandToString().

◆ OT_VREG_FP

const char TDGen::OT_VREG_FP = 'e'
static

Definition at line 512 of file TDGen.hh.

Referenced by operandChar(), and operandToString().

◆ OT_VREG_HFP

const char TDGen::OT_VREG_HFP = 'g'
static

Definition at line 513 of file TDGen.hh.

Referenced by operandChar(), and operandToString().

◆ OT_VREG_INT16

const char TDGen::OT_VREG_INT16 = 't'
static

Definition at line 510 of file TDGen.hh.

Referenced by operandChar(), and operandToString().

◆ OT_VREG_INT32

const char TDGen::OT_VREG_INT32 = 'u'
static

Definition at line 511 of file TDGen.hh.

Referenced by operandChar(), and operandToString().

◆ OT_VREG_INT8

const char TDGen::OT_VREG_INT8 = 'q'
static

Definition at line 509 of file TDGen.hh.

Referenced by operandChar(), and operandToString().

◆ packOperations_

std::map<TCEString, TCEString> TDGen::packOperations_
protected

Contains machine's PACK instructions (<ValueType, InstrName>).

Definition at line 547 of file TDGen.hh.

◆ prebypassStackIndeces_

bool TDGen::prebypassStackIndeces_
protected

Definition at line 632 of file TDGen.hh.

Referenced by TDGen(), and write32bitRegisterInfo().

◆ registerInfo_

std::string TDGen::registerInfo_
protected

Definition at line 469 of file TDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ registerLoads_

std::map<TCEString, TDGenerator::InstructionInfo> TDGen::registerLoads_
protected

All register load operations (<ValueType, InstrInfo>).

Definition at line 540 of file TDGen.hh.

Referenced by genGeneratedTCEPlugin_getLoad(), genGeneratedTCEPlugin_getLoadOpcode(), and writeVectorLoadStoreOperationExploitations().

◆ registers_

std::map<int, std::vector<TDGenerator::RegisterInfo> > TDGen::registers_
protected

Contains registers fit for being vector registers (<Width, Registers>).

Definition at line 532 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), associateRegistersWithVectorRegisterClasses(), orderEqualWidthRegistersToRoundRobin(), writeCallDefRegs(), and writeVectorRegisterNames().

◆ registerStores_

std::map<TCEString, TDGenerator::InstructionInfo> TDGen::registerStores_
protected

All register store operations (<ValueType, InstrInfo>).

Definition at line 538 of file TDGen.hh.

Referenced by genGeneratedTCEPlugin_getStore(), writeVectorLoadStoreOperationExploitations(), and writeVectorTruncStoreDefs().

◆ regs16bit_

std::vector<RegInfo> TDGen::regs16bit_
protected

Definition at line 593 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), and write16bitRegisterInfo().

◆ regs1bit_

std::vector<RegInfo> TDGen::regs1bit_
protected

Definition at line 589 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), analyzeRegisters(), createSelectPatterns(), and write1bitRegisterInfo().

◆ regs32bit_

std::vector<RegInfo> TDGen::regs32bit_
protected

Definition at line 595 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), analyzeRegisters(), checkRequiredRegisters(), write32bitRegisterInfo(), and writeRegisterInfo().

◆ regs64bit_

std::vector<RegInfo> TDGen::regs64bit_
protected

Definition at line 597 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), analyzeRegisters(), checkRequiredRegisters(), and write64bitRegisterInfo().

◆ regs8bit_

std::vector<RegInfo> TDGen::regs8bit_
protected

Definition at line 591 of file TDGen.hh.

Referenced by analyzeRegisters().

◆ regs_

std::map<std::string, RegInfo> TDGen::regs_
protected

Map of generated llvm register names to physical register in the machine.

Definition at line 603 of file TDGen.hh.

Referenced by writeBackendCode(), and writeRegisterDef().

◆ regsInClasses_

RegClassMap TDGen::regsInClasses_
protected

All registers in certain group.

Definition at line 645 of file TDGen.hh.

Referenced by genGeneratedTCEPlugin_getLoad(), genGeneratedTCEPlugin_getStore(), write16bitRegisterInfo(), write1bitRegisterInfo(), write32bitRegisterInfo(), and writeRegisterDef().

◆ regsInRFClasses_

RegClassMap TDGen::regsInRFClasses_
protected

Definition at line 647 of file TDGen.hh.

Referenced by write32bitRegisterInfo().

◆ requiredI32Regs_

unsigned int TDGen::requiredI32Regs_
protected

Minimum number of 32 bit registers.

Definition at line 630 of file TDGen.hh.

Referenced by checkRequiredRegisters(), TDGen(), and writeRegisterInfo().

◆ requiredI64Regs_

unsigned int TDGen::requiredI64Regs_
protected

Definition at line 631 of file TDGen.hh.

Referenced by checkRequiredRegisters(), and TDGen().

◆ resRegNames_

std::vector<std::string> TDGen::resRegNames_
protected

Definition at line 606 of file TDGen.hh.

Referenced by writeCallDefRegs(), and writeRegisterDef().

◆ scalarOps_

std::map<TCEString, Operation*> TDGen::scalarOps_
protected

Contains all scalar operations (<Name, Operation>).

Definition at line 523 of file TDGen.hh.

Referenced by gatherAllMachineOperations().

◆ shlOperations_

std::map<TCEString, TCEString> TDGen::shlOperations_
protected

Contains machine's shl instructions (<ValueType, InstrName>).

Definition at line 581 of file TDGen.hh.

Referenced by genGeneratedTCEPlugin_getShlOpcode().

◆ shlSameOperations_

std::map<TCEString, TCEString> TDGen::shlSameOperations_
protected

Contains machine's SHLSAME instructions (<ValueType, InstrName>).

Definition at line 565 of file TDGen.hh.

◆ shrSameOperations_

std::map<TCEString, TCEString> TDGen::shrSameOperations_
protected

Contains machine's SHRSAME instructions (<ValueType, InstrName>).

Definition at line 567 of file TDGen.hh.

◆ shruSameOperations_

std::map<TCEString, TCEString> TDGen::shruSameOperations_
protected

Contains machine's SHRUSAME instructions (<ValueType, InstrName>).

Definition at line 569 of file TDGen.hh.

◆ tempRegFiles_

std::set< const TTAMachine::RegisterFile*, TTAMachine::MachinePart::Comparator> TDGen::tempRegFiles_
protected

Register files whose last reg reserved for temp reg copies.

Definition at line 641 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), analyzeRegisters(), checkRequiredRegisters(), and TDGen().

◆ topLevelTD_

std::string TDGen::topLevelTD_
protected

Definition at line 477 of file TDGen.hh.

Referenced by generateBackend(), generateBackend(), and initializeBackendContents().

◆ truePredOps_

std::map<std::string, std::string> TDGen::truePredOps_
protected

Definition at line 611 of file TDGen.hh.

Referenced by writeBackendCode(), writeInstrInfo(), writeOperationDef(), and writeVectorRegisterMoveDefs().

◆ truncOperations_

std::vector<std::pair<const Operation*, TCEString> > TDGen::truncOperations_
protected

Contains machine's TRUNCxx/CFH instructions (<ValueType, InstrName>).

Definition at line 551 of file TDGen.hh.

Referenced by writeVectorTruncStoreDefs().

◆ use64bitForFP_

bool TDGen::use64bitForFP_
protected

Definition at line 633 of file TDGen.hh.

Referenced by genGeneratedTCEPlugin_getLoad(), genGeneratedTCEPlugin_getStore(), write32bitRegisterInfo(), and write64bitRegisterInfo().

◆ vbcastOperations_

std::map<TCEString, TCEString> TDGen::vbcastOperations_
protected

Contains machine's VBCAST instructions (<ValueType, InstrName>).

Definition at line 549 of file TDGen.hh.

Referenced by writeScalarToVectorDefs().

◆ vcshuffleOperations_

std::map<std::pair<TCEString, std::vector<int> >, TCEString> TDGen::vcshuffleOperations_
protected

Contains machine's VCSHUFFLE instructions (<<ValueType, ConstantSelects>, InstrName>).

Definition at line 561 of file TDGen.hh.

◆ vectorOps_

std::map<TCEString, Operation*> TDGen::vectorOps_
protected

Contains all vector operations (<Name, Operation>).

Definition at line 526 of file TDGen.hh.

Referenced by gatherAllMachineOperations().

◆ vRegClasses_

std::map<TCEString, TDGenerator::RegisterClass> TDGen::vRegClasses_
protected

Contains required vector register classes (<ValueType, RegClass>).

Definition at line 535 of file TDGen.hh.

Referenced by analyzeMachineRegisters(), analyzeMachineVectorRegisterClasses(), associatedVectorRegisterClass(), associateRegistersWithVectorRegisterClasses(), createSelectPatterns(), createVectorRVDRegNums(), genGeneratedTCEPlugin_getLoad(), genGeneratedTCEPlugin_getStore(), genGeneratedTCEPlugin_getVectorImmediateOpcode(), genTCEInstrInfoSIMD_copyPhysVectorReg(), genTCERegisterInfo_setReservedVectorRegs(), genTCETargetLoweringSIMD_addVectorRegisterClasses(), genTCETargetLoweringSIMD_associatedVectorRegClass(), hasRegisterClassSupport(), hasRegisterClassSupport(), writeCallingConv(), writeVectorBitConversions(), writeVectorImmediateWriteDefs(), writeVectorLoadStoreOperationExploitations(), writeVectorRegisterClasses(), writeVectorRegisterMoveDefs(), and writeVectorTruncStoreDefs().

◆ vselectOperations_

std::map<TCEString, TCEString> TDGen::vselectOperations_
protected

Contains machine's VSELECT instructions (<instrName, ValueType>).

Definition at line 553 of file TDGen.hh.

◆ vshuffle1Operations_

std::map<TCEString, TCEString> TDGen::vshuffle1Operations_
protected

Contains machine's VSHUFFLE1 instructions (<ValueType, InstrName>).

Definition at line 555 of file TDGen.hh.

◆ vshuffle2Operations_

std::map<TCEString, TCEString> TDGen::vshuffle2Operations_
protected

Contains machine's VSHUFFLE2 instructions (<ValueType, InstrName>).

Definition at line 557 of file TDGen.hh.

◆ xorSameOperations_

std::map<TCEString, TCEString> TDGen::xorSameOperations_
protected

Contains machine's XORSAME instructions (<ValueType, InstrName>).

Definition at line 575 of file TDGen.hh.

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