#include <Stratix2DSPBoardIntegrator.hh>

Inheritance diagram for Stratix2DSPBoardIntegrator:

Collaboration diagram for Stratix2DSPBoardIntegrator:

Public Member Functions
	Stratix2DSPBoardIntegrator ()

	Stratix2DSPBoardIntegrator (const TTAMachine::Machine machine, const IDF::MachineImplementation idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString coreEntityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)

virtual	~Stratix2DSPBoardIntegrator ()

virtual void	integrateProcessor (const ProGe::NetlistBlock *ttaCore)

virtual TCEString	deviceFamily () const

virtual void	setDeviceFamily (TCEString devFamily)

virtual TCEString	devicePackage () const

virtual TCEString	deviceSpeedClass () const

virtual int	targetClockFrequency () const

virtual void	printInfo (std::ostream &stream) const

Public Member Functions inherited from AlteraIntegrator
	AlteraIntegrator ()

	AlteraIntegrator (const TTAMachine::Machine machine, const IDF::MachineImplementation idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString entityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)

virtual	~AlteraIntegrator ()

Public Member Functions inherited from PlatformIntegrator
	PlatformIntegrator ()

	PlatformIntegrator (const TTAMachine::Machine machine, const IDF::MachineImplementation idf, ProGe::HDL hdl, TCEString progeOutputDir, TCEString coreEntityName, TCEString outputDir, TCEString programName, int targetClockFreq, std::ostream &warningStream, std::ostream &errorStream, const MemInfo &imem, MemType dmemType)

virtual	~PlatformIntegrator ()

void	setDeviceName (TCEString devName)

TCEString	deviceName () const

const ProGe::NetlistBlock &	progeBlock () const

const ProGe::NetlistBlock &	toplevelBlock () const

void	setSharedOutputDir (const TCEString &sharedDir)

TCEString	outputPath () const

TCEString	outputFilePath (TCEString fileName, bool absolute=false) const

TCEString	coreEntityName () const

const TTAMachine::Machine *	machine () const

const IDF::MachineImplementation *	idf () const

const MemInfo &	imemInfo () const

const MemInfo &	dmemInfo (TTAMachine::AddressSpace *as) const

const MemInfo &	dmemInfo (int index) const

int	dmemCount () const

ProGe::NetlistPort *	clockPort () const

ProGe::NetlistPort *	resetPort () const

Protected Member Functions
virtual MemoryGenerator &	dmemInstance (MemInfo dmem, TTAMachine::FunctionUnit &lsuArch, std::vector< std::string > lsuPorts)

virtual TCEString	pinTag () const

virtual bool	chopTaggedSignals () const

virtual ProjectFileGenerator *	projectFileGenerator () const

Protected Member Functions inherited from AlteraIntegrator
virtual MemoryGenerator &	imemInstance (MemInfo imem, int coreId)

Protected Member Functions inherited from PlatformIntegrator
ProGe::NetlistBlock *	integratorBlock ()

virtual void	initPlatformNetlist (const ProGe::NetlistBlock *progeBlock)

virtual bool	integrateCore (const ProGe::NetlistBlock &cores, int coreId)

virtual void	exportUnconnectedPorts (int coreId)

virtual void	connectToplevelPort (const ProGe::NetlistPort &corePort, const TCEString signalPrefix="")

virtual bool	hasPinTag (const TCEString &signal) const

void	copyProgeBlockToNetlist (const ProGe::NetlistBlock *progeBlock)

virtual bool	createMemories (int coreId)

virtual bool	generateMemory (MemoryGenerator &memGen, std::vector< TCEString > &generatedFiles, int memIndex, int coreId)

virtual void	writeNewToplevel ()

void	addProGeFiles () const

TCEString	programName () const

TCEString	progeFilePath (TCEString fileName, bool absolute=false) const

TCEString	tbFilePath (TCEString fileName, bool absolute=false) const

TCEString	chopSignalToTag (const TCEString &original, const TCEString &tag) const

void	progeOutputHdlFiles (std::vector< TCEString > &files) const

std::ostream &	warningStream () const

std::ostream &	errorStream () const

TCEString	platformEntityName () const

void	parseDataMemories ()

void	clearDataMemories ()

MemInfo	readLsuParameters (const TTAMachine::FunctionUnit &lsu)

Private Member Functions
void	generatePinMap ()

void	mapToplevelPorts ()

void	addSignalMapping (const TCEString &signal)

Private Attributes
QuartusProjectGenerator *	quartusGen_

MemoryGenerator *	dmemGen_

PlatInt::PinMap	stratix2Pins_

Static Private Attributes
static const TCEString	DEVICE_FAMILY_ = "Stratix II"

static const TCEString	DEVICE_NAME_

static const TCEString	DEVICE_PACKAGE_ = "F1020"

static const TCEString	DEVICE_SPEED_CLASS_ = "3"

static const TCEString	PIN_TAG_ = "STRATIXII"

static const int	DEFAULT_FREQ_ = 100

Additional Inherited Members
Static Protected Attributes inherited from PlatformIntegrator
static const TCEString	TTA_CORE_CLK = "clk"

static const TCEString	TTA_CORE_RSTX = "rstx"

Detailed Description

Definition at line 52 of file Stratix2DSPBoardIntegrator.hh.

Constructor & Destructor Documentation

◆ Stratix2DSPBoardIntegrator() [1/2]

Stratix2DSPBoardIntegrator::Stratix2DSPBoardIntegrator ( )

Definition at line 63 of file Stratix2DSPBoardIntegrator.cc.

                                                      :
    AlteraIntegrator(), quartusGen_(NULL) {
 
}

◆ Stratix2DSPBoardIntegrator() [2/2]

Stratix2DSPBoardIntegrator::Stratix2DSPBoardIntegrator	(	const TTAMachine::Machine *	machine,
		const IDF::MachineImplementation *	idf,
		ProGe::HDL	hdl,
		TCEString	progeOutputDir,
		TCEString	coreEntityName,
		TCEString	outputDir,
		TCEString	programName,
		int	targetClockFreq,
		std::ostream &	warningStream,
		std::ostream &	errorStream,
		const MemInfo &	imem,
		MemType	dmemType
	)

Definition at line 68 of file Stratix2DSPBoardIntegrator.cc.

                     :
    AlteraIntegrator(machine, idf, hdl, progeOutputDir, coreEntityName,
                     outputDir, programName, targetClockFreq, warningStream,
                     errorStream, imem, dmemType),
    quartusGen_(new QuartusProjectGenerator(coreEntityName, this)),
    dmemGen_(NULL) {
    setDeviceName(DEVICE_NAME_);
}

References DEVICE_NAME_, and PlatformIntegrator::setDeviceName().

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◆ ~Stratix2DSPBoardIntegrator()

Stratix2DSPBoardIntegrator::~Stratix2DSPBoardIntegrator ( )

virtual

Definition at line 90 of file Stratix2DSPBoardIntegrator.cc.

                                                        {
 
    for (PlatInt::PinMap::iterator iter = stratix2Pins_.begin();
         iter != stratix2Pins_.end(); iter++) {
        if (iter->second != NULL) {
            for (unsigned int i = 0; i < iter->second->size(); i++) {
                delete iter->second->at(i);
            }
            delete iter->second;
        }
    }
    if (quartusGen_ != NULL) {
        delete quartusGen_;
    }
 
    if (dmemGen_ != NULL) {
        delete dmemGen_;
    }
}

References dmemGen_, quartusGen_, and stratix2Pins_.

Member Function Documentation

◆ addSignalMapping()

void Stratix2DSPBoardIntegrator::addSignalMapping ( const TCEString & signal )

private

Definition at line 169 of file Stratix2DSPBoardIntegrator.cc.

                                                                    {
    
    if (stratix2Pins_.find(signal) == stratix2Pins_.end()) {
        warningStream() << "Warning: didn't find mapping for signal name "
                        << signal << endl;
        return;
    }
 
    SignalMappingList* mappings = stratix2Pins_.find(signal)->second;
    for (unsigned int i = 0; i < mappings->size(); i++) {
        quartusGen_->addSignalMapping(*mappings->at(i));
    }
}

References ProjectFileGenerator::addSignalMapping(), quartusGen_, stratix2Pins_, and PlatformIntegrator::warningStream().

Referenced by mapToplevelPorts().

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◆ chopTaggedSignals()

bool Stratix2DSPBoardIntegrator::chopTaggedSignals ( ) const

protectedvirtual

Implements PlatformIntegrator.

Definition at line 192 of file Stratix2DSPBoardIntegrator.cc.

                                                    {
 
    return true;
}

◆ deviceFamily()

TCEString Stratix2DSPBoardIntegrator::deviceFamily ( ) const

virtual

Returns the FPGA device family

Implements PlatformIntegrator.

Definition at line 207 of file Stratix2DSPBoardIntegrator.cc.

                                               {
    
    return DEVICE_FAMILY_;
}

References DEVICE_FAMILY_.

◆ devicePackage()

TCEString Stratix2DSPBoardIntegrator::devicePackage ( ) const

virtual

Returns the device package name

Implements PlatformIntegrator.

Definition at line 225 of file Stratix2DSPBoardIntegrator.cc.

                                                {
 
    return DEVICE_PACKAGE_;
}

References DEVICE_PACKAGE_.

◆ deviceSpeedClass()

TCEString Stratix2DSPBoardIntegrator::deviceSpeedClass ( ) const

virtual

Returns the device speed class

Implements PlatformIntegrator.

Definition at line 232 of file Stratix2DSPBoardIntegrator.cc.

                                                   {
 
    return DEVICE_SPEED_CLASS_;
}

References DEVICE_SPEED_CLASS_.

◆ dmemInstance()

MemoryGenerator & Stratix2DSPBoardIntegrator::dmemInstance	(	MemInfo	dmem,
		TTAMachine::FunctionUnit &	lsuArch,
		std::vector< std::string >	lsuPorts
	)

protectedvirtual

Reimplemented from AlteraIntegrator.

Definition at line 134 of file Stratix2DSPBoardIntegrator.cc.

                                   {
    if (dmem.type == ONCHIP) {
        return AlteraIntegrator::dmemInstance(dmem, lsuArch, lsuPorts);
    } else if (dmem.type == SRAM) {
        if (dmemGen_ == NULL) {
            TCEString initFile = programName() + "_" + dmem.asName + ".img";
            // SRAM component has fixed size, thus use the addr width from hdb
            int addrw = dmem.portAddrw;
            dmemGen_ =
                new Stratix2SramGenerator(
                    dmem.mauWidth, dmem.widthInMaus, addrw, initFile,
                    this, warningStream(), errorStream());
            warningStream() << "Warning: Data memory is not initialized "
                            << "during FPGA programming." << endl;
            dmemGen_->addLsu(lsuArch, lsuPorts);
        }
    } else {
        TCEString msg = "Unsupported data memory type";
        throw InvalidData(__FILE__, __LINE__, "Stratix2DSPBoardIntegrator",
                          msg);
    }
    return *dmemGen_;
}

References MemoryGenerator::addLsu(), MemInfo::asName, dmemGen_, AlteraIntegrator::dmemInstance(), PlatformIntegrator::errorStream(), MemInfo::mauWidth, ONCHIP, MemInfo::portAddrw, PlatformIntegrator::programName(), SRAM, MemInfo::type, PlatformIntegrator::warningStream(), and MemInfo::widthInMaus.

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◆ generatePinMap()

void Stratix2DSPBoardIntegrator::generatePinMap ( )

private

Definition at line 268 of file Stratix2DSPBoardIntegrator.cc.

                                           {
 
    // clk
    SignalMappingList* clk = new SignalMappingList;
    clk->push_back(new SignalMapping("PIN_AM17","clk"));
    stratix2Pins_["clk"] = clk;
 
    // reset to push button CPU_RESET
    SignalMappingList* rstx = new SignalMappingList;
    rstx->push_back(new SignalMapping("PIN_AG19","rstx"));
    stratix2Pins_["rstx"] = rstx;
    
    // leds
    SignalMappingList* ledMapping = new SignalMappingList;
    ledMapping->push_back(new SignalMapping("PIN_B4","STRATIXII_LED[0]"));
    ledMapping->push_back(new SignalMapping("PIN_D5","STRATIXII_LED[1]"));
    ledMapping->push_back(new SignalMapping("PIN_E5","STRATIXII_LED[2]"));
    ledMapping->push_back(new SignalMapping("PIN_A4","STRATIXII_LED[3]"));
    ledMapping->push_back(new SignalMapping("PIN_A5","STRATIXII_LED[4]"));
    ledMapping->push_back(new SignalMapping("PIN_D6","STRATIXII_LED[5]"));
    ledMapping->push_back(new SignalMapping("PIN_C6","STRATIXII_LED[6]"));
    ledMapping->push_back(new SignalMapping("PIN_A6","STRATIXII_LED[7]"));
    stratix2Pins_["STRATIXII_LED"] = ledMapping;
 
    // sram data signals
    SignalMappingList* sramData = new SignalMappingList;
    sramData->push_back(new SignalMapping("PIN_AD18","STRATIXII_SRAM_DQ[0]"));
    sramData->push_back(new SignalMapping("PIN_AB18","STRATIXII_SRAM_DQ[1]"));
    sramData->push_back(new SignalMapping("PIN_AB19","STRATIXII_SRAM_DQ[2]"));
    sramData->push_back(new SignalMapping("PIN_AC20","STRATIXII_SRAM_DQ[3]"));
    sramData->push_back(new SignalMapping("PIN_AD20","STRATIXII_SRAM_DQ[4]"));
    sramData->push_back(new SignalMapping("PIN_AE20","STRATIXII_SRAM_DQ[5]"));
    sramData->push_back(new SignalMapping("PIN_AB20","STRATIXII_SRAM_DQ[6]"));
    sramData->push_back(new SignalMapping("PIN_AF20","STRATIXII_SRAM_DQ[7]"));
    sramData->push_back(new SignalMapping("PIN_AC21","STRATIXII_SRAM_DQ[8]"));
    sramData->push_back(new SignalMapping("PIN_AD21","STRATIXII_SRAM_DQ[9]"));
    sramData->push_back(
        new SignalMapping("PIN_AB21","STRATIXII_SRAM_DQ[10]"));
    sramData->push_back(
        new SignalMapping("PIN_AE21","STRATIXII_SRAM_DQ[11]"));
    sramData->push_back(
        new SignalMapping("PIN_AG20","STRATIXII_SRAM_DQ[12]"));
    sramData->push_back(
        new SignalMapping("PIN_AF21","STRATIXII_SRAM_DQ[13]"));
    sramData->push_back(
        new SignalMapping("PIN_AD22","STRATIXII_SRAM_DQ[14]"));
    sramData->push_back(
        new SignalMapping("PIN_AF22","STRATIXII_SRAM_DQ[15]"));
    sramData->push_back(
        new SignalMapping("PIN_AE22","STRATIXII_SRAM_DQ[16]"));
    sramData->push_back(
        new SignalMapping("PIN_AC17","STRATIXII_SRAM_DQ[17]"));
    sramData->push_back(
        new SignalMapping("PIN_AE19","STRATIXII_SRAM_DQ[18]"));
    sramData->push_back(
        new SignalMapping("PIN_AD19","STRATIXII_SRAM_DQ[19]"));
    sramData->push_back(
        new SignalMapping("PIN_AC18","STRATIXII_SRAM_DQ[20]"));
    sramData->push_back(
        new SignalMapping("PIN_AB17","STRATIXII_SRAM_DQ[21]"));
    sramData->push_back(
        new SignalMapping("PIN_AC19","STRATIXII_SRAM_DQ[22]"));
    sramData->push_back(
        new SignalMapping("PIN_AL26","STRATIXII_SRAM_DQ[23]"));
    sramData->push_back(
        new SignalMapping("PIN_AL27","STRATIXII_SRAM_DQ[24]"));
    sramData->push_back(
        new SignalMapping("PIN_AL28","STRATIXII_SRAM_DQ[25]"));
    sramData->push_back(
        new SignalMapping("PIN_AK28","STRATIXII_SRAM_DQ[26]"));
    sramData->push_back(
        new SignalMapping("PIN_AK29","STRATIXII_SRAM_DQ[27]"));
    sramData->push_back(
        new SignalMapping("PIN_AC13","STRATIXII_SRAM_DQ[28]"));
    sramData->push_back(
        new SignalMapping("PIN_AD10","STRATIXII_SRAM_DQ[29]"));
    sramData->push_back(
        new SignalMapping("PIN_AC11","STRATIXII_SRAM_DQ[30]"));
    sramData->push_back(
        new SignalMapping("PIN_AE11","STRATIXII_SRAM_DQ[31]"));
    stratix2Pins_["STRATIXII_SRAM_DQ"] = sramData;
 
     // sram address signals
    SignalMappingList* sramAddr = new SignalMappingList;
    sramAddr->push_back(
        new SignalMapping("PIN_AM28","STRATIXII_SRAM_ADDR[0]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AJ27","STRATIXII_SRAM_ADDR[1]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AK27","STRATIXII_SRAM_ADDR[2]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AL29","STRATIXII_SRAM_ADDR[3]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AM29","STRATIXII_SRAM_ADDR[4]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AJ28","STRATIXII_SRAM_ADDR[5]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AH28","STRATIXII_SRAM_ADDR[6]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AK20","STRATIXII_SRAM_ADDR[7]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AJ20","STRATIXII_SRAM_ADDR[8]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AL21","STRATIXII_SRAM_ADDR[9]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AL22","STRATIXII_SRAM_ADDR[10]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AJ22","STRATIXII_SRAM_ADDR[11]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AH22","STRATIXII_SRAM_ADDR[12]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AL23","STRATIXII_SRAM_ADDR[13]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AL24","STRATIXII_SRAM_ADDR[14]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AJ25","STRATIXII_SRAM_ADDR[15]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AH25","STRATIXII_SRAM_ADDR[16]"));
    sramAddr->push_back(
        new SignalMapping("PIN_AL25","STRATIXII_SRAM_ADDR[17]"));
    stratix2Pins_["STRATIXII_SRAM_ADDR"] = sramAddr;
 
    // sram control signals
    SignalMappingList* sramWe = new SignalMappingList;
    sramWe->push_back(new SignalMapping("PIN_AH14","STRATIXII_SRAM_WE_N"));
    stratix2Pins_["STRATIXII_SRAM_WE_N"] = sramWe;
 
    SignalMappingList* sramOe = new SignalMappingList;
    sramOe->push_back(new SignalMapping("PIN_AG14","STRATIXII_SRAM_OE_N"));
    stratix2Pins_["STRATIXII_SRAM_OE_N"] = sramOe;
 
    SignalMappingList* sramCs = new SignalMappingList;
    sramCs->push_back(new SignalMapping("PIN_AL12","STRATIXII_SRAM_CS_N"));
    stratix2Pins_["STRATIXII_SRAM_CS_N"] = sramCs;
 
    SignalMappingList* sramB0 = new SignalMappingList;
    SignalMappingList* sramB1 = new SignalMappingList;
    SignalMappingList* sramB2 = new SignalMappingList;
    SignalMappingList* sramB3 = new SignalMappingList;
    sramB0->push_back(new SignalMapping("PIN_AG11","STRATIXII_SRAM_BE_N0"));
    sramB1->push_back(new SignalMapping("PIN_AK10","STRATIXII_SRAM_BE_N1"));
    sramB2->push_back(new SignalMapping("PIN_AK11","STRATIXII_SRAM_BE_N2"));
    sramB3->push_back(new SignalMapping("PIN_AL11","STRATIXII_SRAM_BE_N3"));
    stratix2Pins_["STRATIXII_SRAM_BE_N0"] = sramB0;
    stratix2Pins_["STRATIXII_SRAM_BE_N1"] = sramB1;
    stratix2Pins_["STRATIXII_SRAM_BE_N2"] = sramB2;
    stratix2Pins_["STRATIXII_SRAM_BE_N3"] = sramB3;
}

References stratix2Pins_.

Referenced by integrateProcessor().

◆ integrateProcessor()

void Stratix2DSPBoardIntegrator::integrateProcessor ( const ProGe::NetlistBlock * progeBlock )

virtual

Integrates the TTA core(s) generated by ProGe

Parameters

progeBlock The toplevel netlist block created by ProGe

Reimplemented from AlteraIntegrator.

Definition at line 111 of file Stratix2DSPBoardIntegrator.cc.

                                      {
 
    generatePinMap();
 
    initPlatformNetlist(ttaCore);
    
    const NetlistBlock& core = progeBlock();
    int coreId = -1;
    if (!integrateCore(core, coreId)) {
        return;
    }
 
    mapToplevelPorts();
 
    writeNewToplevel();
    
    addProGeFiles();
 
    projectFileGenerator()->writeProjectFiles();
}

References PlatformIntegrator::addProGeFiles(), generatePinMap(), PlatformIntegrator::initPlatformNetlist(), PlatformIntegrator::integrateCore(), mapToplevelPorts(), PlatformIntegrator::progeBlock(), projectFileGenerator(), PlatformIntegrator::writeNewToplevel(), and ProjectFileGenerator::writeProjectFiles().

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◆ mapToplevelPorts()

void Stratix2DSPBoardIntegrator::mapToplevelPorts ( )

private

Definition at line 161 of file Stratix2DSPBoardIntegrator.cc.

                                             {
    NetlistBlock& tl = *integratorBlock();
    for (size_t i = 0; i < tl.portCount(); i++) {
        addSignalMapping(tl.port(i).name());
    }
}

References addSignalMapping(), PlatformIntegrator::integratorBlock(), ProGe::NetlistPort::name(), ProGe::NetlistBlock::port(), and ProGe::NetlistBlock::portCount().

Referenced by integrateProcessor().

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◆ pinTag()

TCEString Stratix2DSPBoardIntegrator::pinTag ( ) const

protectedvirtual

Implements PlatformIntegrator.

Definition at line 185 of file Stratix2DSPBoardIntegrator.cc.

                                         {
 
    return PIN_TAG_;
}

References PIN_TAG_.

◆ printInfo()

void Stratix2DSPBoardIntegrator::printInfo ( std::ostream & stream ) const

virtual

Prints information about the platform

Implements PlatformIntegrator.

Definition at line 249 of file Stratix2DSPBoardIntegrator.cc.

                                                              {
    
    stream 
        << "Integrator name: Stratix2DSP" << std::endl
        << "-----------------------------" << std::endl
        << "Integrates the processor core to Altera Stratix II DSP board "
        << "with EP2S180F1020C3 device." << std::endl
        << "Creates project files for QuartusII v8.0 program." << std::endl
        << "Supported instruction memory types are 'onchip' and 'vhdl_array."
        << std::endl
        << "Supported data memory types are 'onchip' and 'sram'." << std::endl
        << "Default clock frequency is 100 MHz." << std::endl 
        << "Active low reset is connected to CPU RESET button." << std::endl
        << std::endl;
}

◆ projectFileGenerator()

ProjectFileGenerator * Stratix2DSPBoardIntegrator::projectFileGenerator ( ) const

protectedvirtual

Implements PlatformIntegrator.

Definition at line 199 of file Stratix2DSPBoardIntegrator.cc.

                                                       {
 
    return quartusGen_;
}

References quartusGen_.

Referenced by integrateProcessor().

◆ setDeviceFamily()

void Stratix2DSPBoardIntegrator::setDeviceFamily ( TCEString devFamily )

virtual

Set the FPGA device family.

Intended for TTA IP integration. Integrator can device whether this overrides the default device family.

Implements PlatformIntegrator.

Definition at line 214 of file Stratix2DSPBoardIntegrator.cc.

                                                               {
    
    if (devFamily != DEVICE_FAMILY_) {
        warningStream() 
            << "Warning: Refusing to change device family!" << endl
            << "- Original device family: " << DEVICE_FAMILY_ << endl
            << "- New device family: " << devFamily << endl;
    }
}

References DEVICE_FAMILY_, and PlatformIntegrator::warningStream().

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◆ targetClockFrequency()

int Stratix2DSPBoardIntegrator::targetClockFrequency ( ) const

virtual

Returns the target clock frequency in MHz

Reimplemented from PlatformIntegrator.

Definition at line 238 of file Stratix2DSPBoardIntegrator.cc.

                                                       {
 
    int freq = DEFAULT_FREQ_;
 
    if (PlatformIntegrator::targetClockFrequency() > 0) {
        freq = PlatformIntegrator::targetClockFrequency();
    }
    return freq;
}