#include <TestBenchBlock.hh>

Inheritance diagram for ProGe::TestBenchBlock:

Collaboration diagram for ProGe::TestBenchBlock:

Public Member Functions
	TestBenchBlock ()=delete

	TestBenchBlock (const ProGeContext &context, const BaseNetlistBlock &coreBlock)

virtual	~TestBenchBlock ()

virtual void	write (const Path &targetBaseDir, HDL targetLang=VHDL) const override

Public Member Functions inherited from ProGe::BaseNetlistBlock
	BaseNetlistBlock ()

	BaseNetlistBlock (BaseNetlistBlock *parent)

	BaseNetlistBlock (const std::string &moduleName, const std::string &instanceName, BaseNetlistBlock *parent=nullptr)

virtual	~BaseNetlistBlock ()

const std::string &	instanceName () const

void	setInstanceName (const std::string &name)

const std::string &	moduleName () const

const std::string	name () const

virtual size_t	subBlockCount () const

virtual const BaseNetlistBlock &	subBlock (size_t index) const

virtual bool	hasSubBlock (const std::string &instanceName) const

virtual bool	isSubBlock (const BaseNetlistBlock &block) const

virtual bool	hasParameter (const std::string &name) const

virtual const Parameter &	parameter (const std::string &name) const

virtual size_t	parameterCount () const

virtual const Parameter &	parameter (size_t index) const

virtual size_t	portCount () const

virtual const NetlistPort &	port (size_t index) const

virtual std::vector< const NetlistPort * >	portsBy (SignalType type) const

virtual const NetlistPort &	portBy (SignalType type, size_t index=0) const

virtual bool	hasPortsBy (SignalType type) const

virtual const NetlistPort *	port (const std::string &portName, bool partialMatch=true) const

virtual size_t	portGroupCount () const

virtual const NetlistPortGroup &	portGroup (size_t index) const

virtual std::vector< const NetlistPortGroup * >	portGroupsBy (SignalGroupType type) const

virtual const Netlist &	netlist () const

virtual bool	hasParentBlock () const

virtual const BaseNetlistBlock &	parentBlock () const

virtual bool	isVirtual () const

virtual void	build () override

virtual void	connect () override

virtual void	finalize () override

virtual void	writeSelf (const Path &targetBaseDir, HDL targetLang=VHDL) const

virtual size_t	packageCount () const

virtual const std::string &	package (size_t idx) const

PortContainerType &	ports ()

virtual bool	isLeaf () const

BaseNetlistBlock *	shallowCopy (const std::string &instanceName="") const

Public Member Functions inherited from ProGe::IGenerationPhases
virtual	~IGenerationPhases ()

Private Attributes
const ProGeContext &	context_
	The ProGe context for additional information. More...

ProcessorWrapperBlock *	proc_
	The block that wraps the processor and instantiates memories for the GCU and LSUs. More...

Additional Inherited Members
Public Types inherited from ProGe::BaseNetlistBlock
typedef std::vector< BaseNetlistBlock * >	BlockContainerType

typedef std::vector< Parameter >	ParameterContainerType

typedef std::vector< NetlistPort * >	PortContainerType

typedef std::vector< NetlistPortGroup * >	PortGroupContainerType

Protected Member Functions inherited from ProGe::BaseNetlistBlock
Netlist &	netlist ()

virtual NetlistPort &	port (size_t index)

virtual BaseNetlistBlock &	subBlock (size_t index)

virtual BaseNetlistBlock &	parentBlock ()

void	setModuleName (const std::string &name)

void	addSubBlock (BaseNetlistBlock *subBlock, const std::string &instanceName="")

void	deleteSubBlock (BaseNetlistBlock *subBlock)

void	removeSubBlock (BaseNetlistBlock *subBlock)

NetlistPort *	addPort (NetlistPort *port)

void	removePort (NetlistPort *port)

void	addPortGroup (NetlistPortGroup *portGroup)

void	removePortGroup (NetlistPortGroup *portGroup)

void	setParameter (const Parameter &param)

void	addParameter (const Parameter &param)

Parameter &	parameter (const std::string &name)

NetlistPort *	findPort (const std::string &portName, bool recursiveSearch=false, bool partialMatch=true) const

void	addPackage (const std::string &packageName)

void	connectClocks ()

void	connectResets ()

Detailed Description

Definition at line 50 of file TestBenchBlock.hh.

Constructor & Destructor Documentation

◆ TestBenchBlock() [1/2]

ProGe::TestBenchBlock::TestBenchBlock ( )

delete

◆ TestBenchBlock() [2/2]

ProGe::TestBenchBlock::TestBenchBlock	(	const ProGeContext &	context,
		const BaseNetlistBlock &	coreBlock
	)

Construct The test bench for the core TTA processor.

The test bench creation is limited to TTAs with one address space for instruction and address spaces for data shared by one LSU at most.

Parameters

context	The context for deriving necessary information about the core.
coreBlock	The DUT for test bench

Exceptions

Thrown if the test bench can not be created.

Definition at line 59 of file TestBenchBlock.cc.

     : BaseNetlistBlock("testbench", ""), context_(context), proc_(nullptr) {
     using namespace TTAMachine;
  
     std::map<std::string, unsigned> ASUserCounts;
     std::map<std::string, unsigned> lockFUCounts;
  
     for (auto fu : MachineInfo::findLockUnits(context.adf())) {
         if (fu->hasAddressSpace()) {
             lockFUCounts[fu->addressSpace()->name()]++;
         }
     }
  
     for (auto fu : context.adf().functionUnitNavigator()) {
         if (fu->hasAddressSpace()) {
             ASUserCounts[fu->addressSpace()->name()]++;
         }
     }
  
     for (auto asUserCount : ASUserCounts) {
         unsigned LSUCount(asUserCount.second);
  
         if (lockFUCounts.count(asUserCount.first) > 0) {
             LSUCount -= lockFUCounts[asUserCount.first];
         }
  
         if (LSUCount > 1) {
             THROW_EXCEPTION(NotAvailable,
                 "Can not create test bench for TTA address spaces shared by "
                 "multiple LSUs.");
         }
     }
     try {
         proc_ = new ProcessorWrapperBlock(context, coreBlock);
     } catch (Exception& e) {
         THROW_EXCEPTION(NotAvailable, e.errorMessage());
     }
 }

References ProGe::ProGeContext::adf(), Exception::errorMessage(), MachineInfo::findLockUnits(), TTAMachine::Machine::functionUnitNavigator(), proc_, and THROW_EXCEPTION.

Here is the call graph for this function:

◆ ~TestBenchBlock()

ProGe::TestBenchBlock::~TestBenchBlock ( )

virtual

Definition at line 99 of file TestBenchBlock.cc.

99 {

100 }

Member Function Documentation

◆ write()

void ProGe::TestBenchBlock::write	(	const Path &	targetBaseDir,
		HDL	targetLang = `VHDL`
	)		const

overridevirtual

Does nothing on self but calls write function on each sub block.

Reimplemented from ProGe::BaseNetlistBlock.

Definition at line 103 of file TestBenchBlock.cc.

                                                                      {
     // Check language compatibility //
     if (targetLang != VHDL) {
         THROW_EXCEPTION(NotAvailable, "Only VHDL is supported.");
     }
  
     HDLTemplateInstantiator instantiator(context_.coreEntityName());
  
     instantiator.replacePlaceholder("dut-entity", proc_->moduleName());
  
     if (context_.idf().icDecoderParameterValue("debugger") == "external") {
         instantiator.replacePlaceholder("proc-entity-db-signals",
                 "db_pc_start : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);\n"
                 "db_tta_nreset : in std_logic;\n"
                 "db_lockrq     : in std_logic;");
  
         instantiator.replacePlaceholder("proc-instance-db-signals",
                 "db_pc_start   => (others => '0'),\n"
                 "db_tta_nreset => '1',\n"
                 "db_lockrq     => '0',");
     }
  
     FileSystem::createDirectory(targetBaseDir/"tb");
  
     Path progeDataDir(Environment::dataDirPath("ProGe"));
     instantiator.instantiateTemplateFile(
         progeDataDir/"tb"/"testbench.vhdl.tmpl",
         targetBaseDir/"tb"/"testbench.vhdl");
     instantiator.instantiateTemplateFile(
         progeDataDir/"tb"/"clkgen.vhdl",
         targetBaseDir/"tb"/"clkgen.vhdl");
  
     proc_->write(targetBaseDir, targetLang);
 }